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verific: Fix conditions of SVAs with explicit clocks within procedures

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For SVAs that have an explicit clock and are contained in a procedure
which conditionally executes the assertion, verific expresses this using
a mux with one input connected to constant 1 and the other output
connected to an SVA_AT. The existing code only handled the case where
the first input is connected to 1. This patch also handles the other
case.
This commit is contained in:
Jannis Harder 2022-05-03 13:22:18 +02:00
parent 11e75bc27c
commit 96f64f4788
4 changed files with 27 additions and 5 deletions
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8
frontends/verific/verific.cc
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@ -1873,15 +1873,19 @@ VerificClocking::VerificClocking(VerificImporter *importer, Net *net, bool sva_a
if (inst_mux == nullptr || inst_mux->Type() != PRIM_MUX)
break;
if (!inst_mux->GetInput1()->IsPwr())
bool pwr1 = inst_mux->GetInput1()->IsPwr();
bool pwr2 = inst_mux->GetInput2()->IsPwr();
if (!pwr1 && !pwr2)
break;
Net *sva_net = inst_mux->GetInput2();
Net *sva_net = pwr1 ? inst_mux->GetInput2() : inst_mux->GetInput1();
if (!verific_is_sva_net(importer, sva_net))
break;
body_net = sva_net;
cond_net = inst_mux->GetControl();
cond_pol = pwr1;
} while (0);
clock_net = net;