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https://github.com/YosysHQ/yosys
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parse_xaiger to not take box_lookup
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parent
e5ed8e8e21
commit
96db05aaef
4 changed files with 37 additions and 63 deletions
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@ -340,7 +340,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
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return wire;
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}
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void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
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void AigerReader::parse_xaiger()
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{
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std::string header;
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f >> header;
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@ -382,6 +382,21 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
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if (f.peek() == '\n')
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f.get();
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dict<int,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find(ID(abc9_box_id));
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if (it == m->attributes.end())
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continue;
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if (m->name.begins_with("$paramod"))
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continue;
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auto id = it->second.as_int();
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auto r = box_lookup.insert(std::make_pair(id, m->name));
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if (!r.second)
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log_error("Module '%s' has the same abc9_box_id = %d value as '%s'.\n",
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log_id(m), id, log_id(r.first->second));
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log_assert(r.second);
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}
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// Parse footer (symbol table, comments, etc.)
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std::string s;
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for (int c = f.get(); c != EOF; c = f.get()) {
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@ -456,7 +471,7 @@ void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
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uint32_t boxUniqueId = parse_xaiger_literal(f);
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log_assert(boxUniqueId > 0);
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uint32_t oldBoxNum = parse_xaiger_literal(f);
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RTLIL::Cell* cell = module->addCell(stringf("$__box%u", oldBoxNum), box_lookup.at(boxUniqueId));
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RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), box_lookup.at(boxUniqueId));
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boxes.emplace_back(cell);
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}
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}
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@ -720,25 +735,12 @@ void AigerReader::parse_aiger_binary()
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void AigerReader::post_process()
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{
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pool<IdString> seen_boxes;
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pool<IdString> flops;
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dict<IdString, std::vector<IdString>> box_ports;
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unsigned ci_count = 0, co_count = 0, flop_count = 0;
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for (auto cell : boxes) {
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RTLIL::Module* box_module = design->module(cell->type);
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log_assert(box_module);
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bool is_flop = false;
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if (seen_boxes.insert(cell->type).second) {
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if (box_module->attributes.count("\\abc9_flop")) {
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log_assert(flop_count < flopNum);
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flops.insert(cell->type);
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is_flop = true;
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}
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}
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else
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is_flop = flops.count(cell->type);
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auto r = box_ports.insert(cell->type);
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if (r.second) {
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// Make carry in the last PI, and carry out the last PO
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@ -788,7 +790,7 @@ void AigerReader::post_process()
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cell->setPort(port_name, rhs);
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}
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if (is_flop) {
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if (box_module->attributes.count("\\abc9_flop")) {
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log_assert(co_count < outputs.size());
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Wire *wire = outputs[co_count++];
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log_assert(wire);
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@ -900,7 +902,7 @@ void AigerReader::post_process()
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wire->attributes["\\init"] = init;
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}
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$__box%d", variable));
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RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
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if (cell) { // ABC could have optimised this box away
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module->rename(cell, escaped_s);
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for (const auto &i : cell->connections()) {
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@ -47,7 +47,7 @@ struct AigerReader
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AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
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void parse_aiger();
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void parse_xaiger(const dict<int,IdString> &box_lookup);
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void parse_xaiger();
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void parse_aiger_ascii();
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void parse_aiger_binary();
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void post_process();
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