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Fix bug in #1078, add entry to CHANGELOG

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This commit is contained in:
Eddie Hung 2019-06-19 09:51:11 -07:00
parent 8395f837c3
commit 96ade54993
2 changed files with 4 additions and 3 deletions
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1
CHANGELOG
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@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- Extended "muxcover -mux{4,8,16}=<cost>"
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"

6
passes/techmap/muxcover.cc
View file

@ -610,7 +610,7 @@ struct MuxcoverPass : public Pass {
use_mux4 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
cost_mux4 = atoi(arg.substr(5).c_str());
cost_mux4 = atoi(arg.substr(6).c_str());
}
continue;
}
@ -618,7 +618,7 @@ struct MuxcoverPass : public Pass {
use_mux8 = true;
if (arg.size() > 5) {
if (arg[5] != '=') break;
cost_mux8 = atoi(arg.substr(5).c_str());
cost_mux8 = atoi(arg.substr(6).c_str());
}
continue;
}
@ -626,7 +626,7 @@ struct MuxcoverPass : public Pass {
use_mux16 = true;
if (arg.size() > 6) {
if (arg[6] != '=') break;
cost_mux16 = atoi(arg.substr(6).c_str());
cost_mux16 = atoi(arg.substr(7).c_str());
}
continue;
}