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Fix bug in #1078, add entry to CHANGELOG

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Eddie Hung 2019-06-19 09:51:11 -07:00
parent 8395f837c3
commit 96ade54993
2 changed files with 4 additions and 3 deletions
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CHANGELOG
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@ -17,6 +17,7 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "rename -src"
- Added "equiv_opt" pass
- Added "read_aiger" frontend
- Extended "muxcover -mux{4,8,16}=<cost>"
- "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"