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Promote output wires in sigmap so that can be detected

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This commit is contained in:
Eddie Hung 2019-11-26 23:39:14 -08:00
parent 6318e3ce6d
commit 969f511415
1 changed files with 4 additions and 8 deletions
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12
passes/hierarchy/submod.cc
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@ -34,7 +34,6 @@ struct SubmodWorker
RTLIL::Design *design; RTLIL::Design *design;
RTLIL::Module *module; RTLIL::Module *module;
SigMap sigmap; SigMap sigmap;
pool<SigBit> outputs;
bool copy_mode; bool copy_mode;
bool hidden_mode; bool hidden_mode;
@ -124,13 +123,13 @@ struct SubmodWorker
for (auto &it : bit_flags) for (auto &it : bit_flags)
{ {
const RTLIL::SigBit &bit = it.first; const RTLIL::SigBit &bit = sigmap(it.first);
RTLIL::Wire *wire = bit.wire; RTLIL::Wire *wire = bit.wire;
bit_flags_t &flags = it.second; bit_flags_t &flags = it.second;
if (wire->port_input) if (wire->port_input)
flags.is_ext_driven = true; flags.is_ext_driven = true;
if (outputs.count(bit)) if (wire->port_output)
flags.is_ext_used = true; flags.is_ext_used = true;
bool new_wire_port_input = false; bool new_wire_port_input = false;
@ -240,11 +239,8 @@ struct SubmodWorker
for (auto port : module->ports) { for (auto port : module->ports) {
auto wire = module->wire(port); auto wire = module->wire(port);
if (!wire->port_output) if (wire->port_output)
continue; sigmap.add(wire);
for (auto b : sigmap(wire))
if (b.wire)
outputs.insert(b);
} }
if (opt_name.empty()) if (opt_name.empty())