mirror of
https://github.com/YosysHQ/yosys
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ff: split out type-only information
This commit is contained in:
parent
c768d5e8d2
commit
95ed267960
2 changed files with 323 additions and 244 deletions
489
kernel/ff.cc
489
kernel/ff.cc
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@ -21,245 +21,316 @@
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USING_YOSYS_NAMESPACE
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FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name)
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{
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cell = cell_;
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sig_q = cell->getPort(ID::Q);
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width = GetSize(sig_q);
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attributes = cell->attributes;
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// sorry
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template<typename InputType, typename OutputType, typename = std::enable_if_t<std::is_base_of_v<FfTypeData, OutputType>>>
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void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
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Cell* cell = nullptr;
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IdString type;
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constexpr bool have_cell = std::is_same_v<InputType, Cell*>;
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if constexpr (std::is_same_v<InputType, IdString>) {
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type = flop;
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} else {
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static_assert(std::is_same_v<InputType, Cell*>);
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cell = flop;
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type = flop->type;
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}
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if constexpr (have_cell) {
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info.sig_q = cell->getPort(ID::Q);
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info.width = GetSize(info.sig_q);
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info.attributes = cell->attributes;
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if (initvals)
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info.val_init = (*initvals)(info.sig_q);
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}
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if (initvals)
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val_init = (*initvals)(sig_q);
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std::string type_str = cell->type.str();
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std::string type_str = type.str();
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if (cell->type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
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if (cell->type.in(ID($anyinit), ID($ff))) {
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has_gclk = true;
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sig_d = cell->getPort(ID::D);
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if (cell->type == ID($anyinit)) {
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is_anyinit = true;
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log_assert(val_init.is_fully_undef());
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if (type.in(ID($anyinit), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($dlatchsr), ID($sr))) {
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if (type.in(ID($anyinit), ID($ff))) {
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info.has_gclk = true;
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if constexpr (have_cell)
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info.sig_d = cell->getPort(ID::D);
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if (type == ID($anyinit)) {
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info.is_anyinit = true;
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if constexpr (have_cell)
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log_assert(info.val_init.is_fully_undef());
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}
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} else if (cell->type == ID($sr)) {
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} else if (type == ID($sr)) {
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// No data input at all.
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} else if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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has_aload = true;
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sig_aload = cell->getPort(ID::EN);
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pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
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sig_ad = cell->getPort(ID::D);
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} else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
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info.has_aload = true;
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if constexpr (have_cell) {
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info.sig_aload = cell->getPort(ID::EN);
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info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
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info.sig_ad = cell->getPort(ID::D);
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}
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} else {
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has_clk = true;
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sig_clk = cell->getPort(ID::CLK);
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pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
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sig_d = cell->getPort(ID::D);
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info.has_clk = true;
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if constexpr (have_cell) {
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info.sig_clk = cell->getPort(ID::CLK);
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info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
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info.sig_d = cell->getPort(ID::D);
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}
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}
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if (cell->type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
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has_ce = true;
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sig_ce = cell->getPort(ID::EN);
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pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
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if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
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info.has_ce = true;
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if constexpr (have_cell) {
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info.sig_ce = cell->getPort(ID::EN);
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info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
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}
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}
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if (cell->type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
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has_sr = true;
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sig_clr = cell->getPort(ID::CLR);
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sig_set = cell->getPort(ID::SET);
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pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
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pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
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if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
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info.has_sr = true;
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if constexpr (have_cell) {
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info.sig_clr = cell->getPort(ID::CLR);
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info.sig_set = cell->getPort(ID::SET);
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info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
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info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
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}
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}
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if (cell->type.in(ID($aldff), ID($aldffe))) {
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has_aload = true;
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sig_aload = cell->getPort(ID::ALOAD);
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pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
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sig_ad = cell->getPort(ID::AD);
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if (type.in(ID($aldff), ID($aldffe))) {
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info.has_aload = true;
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if constexpr (have_cell) {
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info.sig_aload = cell->getPort(ID::ALOAD);
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info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
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info.sig_ad = cell->getPort(ID::AD);
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}
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}
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if (cell->type.in(ID($adff), ID($adffe), ID($adlatch))) {
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has_arst = true;
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sig_arst = cell->getPort(ID::ARST);
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pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
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val_arst = cell->getParam(ID::ARST_VALUE);
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if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
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info.has_arst = true;
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if constexpr (have_cell) {
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info.sig_arst = cell->getPort(ID::ARST);
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info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
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info.val_arst = cell->getParam(ID::ARST_VALUE);
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}
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}
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if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
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has_srst = true;
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sig_srst = cell->getPort(ID::SRST);
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pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
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val_srst = cell->getParam(ID::SRST_VALUE);
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ce_over_srst = cell->type == ID($sdffce);
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if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
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info.has_srst = true;
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if constexpr (have_cell) {
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info.sig_srst = cell->getPort(ID::SRST);
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info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
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info.val_srst = cell->getParam(ID::SRST_VALUE);
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}
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info.ce_over_srst = type == ID($sdffce);
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}
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} else if (cell->type == ID($_FF_)) {
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is_fine = true;
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has_gclk = true;
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sig_d = cell->getPort(ID::D);
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} else if (type == ID($_FF_)) {
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info.is_fine = true;
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info.has_gclk = true;
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if constexpr (have_cell)
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info.sig_d = cell->getPort(ID::D);
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} else if (type_str.substr(0, 5) == "$_SR_") {
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is_fine = true;
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has_sr = true;
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pol_set = type_str[5] == 'P';
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pol_clr = type_str[6] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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info.is_fine = true;
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info.has_sr = true;
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info.pol_set = type_str[5] == 'P';
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info.pol_clr = type_str[6] == 'P';
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if constexpr (have_cell) {
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info.sig_set = cell->getPort(ID::S);
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info.sig_clr = cell->getPort(ID::R);
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}
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} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[6] == 'P';
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sig_clk = cell->getPort(ID::C);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[6] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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}
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} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_ce = true;
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pol_ce = type_str[8] == 'P';
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sig_ce = cell->getPort(ID::E);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[7] == 'P';
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info.has_ce = true;
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info.pol_ce = type_str[8] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_ce = cell->getPort(ID::E);
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}
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} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[6] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_arst = true;
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pol_arst = type_str[7] == 'P';
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sig_arst = cell->getPort(ID::R);
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val_arst = type_str[8] == '1' ? State::S1 : State::S0;
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[6] == 'P';
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info.has_arst = true;
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info.pol_arst = type_str[7] == 'P';
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info.val_arst = type_str[8] == '1' ? State::S1 : State::S0;
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_arst = cell->getPort(ID::R);
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}
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} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_arst = true;
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pol_arst = type_str[8] == 'P';
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sig_arst = cell->getPort(ID::R);
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val_arst = type_str[9] == '1' ? State::S1 : State::S0;
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has_ce = true;
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pol_ce = type_str[10] == 'P';
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sig_ce = cell->getPort(ID::E);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[7] == 'P';
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info.has_arst = true;
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info.pol_arst = type_str[8] == 'P';
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info.val_arst = type_str[9] == '1' ? State::S1 : State::S0;
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info.has_ce = true;
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info.pol_ce = type_str[10] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_arst = cell->getPort(ID::R);
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info.sig_ce = cell->getPort(ID::E);
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}
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} else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[8] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_aload = true;
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pol_aload = type_str[9] == 'P';
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sig_aload = cell->getPort(ID::L);
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sig_ad = cell->getPort(ID::AD);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[8] == 'P';
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info.has_aload = true;
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info.pol_aload = type_str[9] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_aload = cell->getPort(ID::L);
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info.sig_ad = cell->getPort(ID::AD);
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}
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} else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[9] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_aload = true;
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pol_aload = type_str[10] == 'P';
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sig_aload = cell->getPort(ID::L);
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sig_ad = cell->getPort(ID::AD);
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has_ce = true;
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pol_ce = type_str[11] == 'P';
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sig_ce = cell->getPort(ID::E);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[9] == 'P';
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info.has_aload = true;
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info.pol_aload = type_str[10] == 'P';
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info.has_ce = true;
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info.pol_ce = type_str[11] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_aload = cell->getPort(ID::L);
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info.sig_ad = cell->getPort(ID::AD);
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info.sig_ce = cell->getPort(ID::E);
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}
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} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[8] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_sr = true;
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pol_set = type_str[9] == 'P';
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pol_clr = type_str[10] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[8] == 'P';
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info.has_sr = true;
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info.pol_set = type_str[9] == 'P';
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info.pol_clr = type_str[10] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_set = cell->getPort(ID::S);
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info.sig_clr = cell->getPort(ID::R);
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}
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} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[9] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_sr = true;
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pol_set = type_str[10] == 'P';
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pol_clr = type_str[11] == 'P';
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sig_set = cell->getPort(ID::S);
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sig_clr = cell->getPort(ID::R);
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has_ce = true;
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pol_ce = type_str[12] == 'P';
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sig_ce = cell->getPort(ID::E);
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[9] == 'P';
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info.has_sr = true;
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info.pol_set = type_str[10] == 'P';
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info.pol_clr = type_str[11] == 'P';
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info.has_ce = true;
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info.pol_ce = type_str[12] == 'P';
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if constexpr (have_cell) {
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info.sig_d = cell->getPort(ID::D);
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info.sig_clk = cell->getPort(ID::C);
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info.sig_set = cell->getPort(ID::S);
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info.sig_clr = cell->getPort(ID::R);
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info.sig_ce = cell->getPort(ID::E);
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}
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} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
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is_fine = true;
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sig_d = cell->getPort(ID::D);
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has_clk = true;
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pol_clk = type_str[7] == 'P';
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sig_clk = cell->getPort(ID::C);
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has_srst = true;
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pol_srst = type_str[8] == 'P';
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sig_srst = cell->getPort(ID::R);
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val_srst = type_str[9] == '1' ? State::S1 : State::S0;
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info.is_fine = true;
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info.has_clk = true;
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info.pol_clk = type_str[7] == 'P';
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info.has_srst = true;
|
||||
info.pol_srst = type_str[8] == 'P';
|
||||
info.val_srst = type_str[9] == '1' ? State::S1 : State::S0;
|
||||
if constexpr (have_cell) {
|
||||
info.sig_d = cell->getPort(ID::D);
|
||||
info.sig_clk = cell->getPort(ID::C);
|
||||
info.sig_srst = cell->getPort(ID::R);
|
||||
}
|
||||
} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
|
||||
is_fine = true;
|
||||
sig_d = cell->getPort(ID::D);
|
||||
has_clk = true;
|
||||
pol_clk = type_str[8] == 'P';
|
||||
sig_clk = cell->getPort(ID::C);
|
||||
has_srst = true;
|
||||
pol_srst = type_str[9] == 'P';
|
||||
sig_srst = cell->getPort(ID::R);
|
||||
val_srst = type_str[10] == '1' ? State::S1 : State::S0;
|
||||
has_ce = true;
|
||||
pol_ce = type_str[11] == 'P';
|
||||
sig_ce = cell->getPort(ID::E);
|
||||
info.is_fine = true;
|
||||
info.has_clk = true;
|
||||
info.pol_clk = type_str[8] == 'P';
|
||||
info.has_srst = true;
|
||||
info.pol_srst = type_str[9] == 'P';
|
||||
info.val_srst = type_str[10] == '1' ? State::S1 : State::S0;
|
||||
info.has_ce = true;
|
||||
info.pol_ce = type_str[11] == 'P';
|
||||
if constexpr (have_cell) {
|
||||
info.sig_d = cell->getPort(ID::D);
|
||||
info.sig_clk = cell->getPort(ID::C);
|
||||
info.sig_srst = cell->getPort(ID::R);
|
||||
info.sig_ce = cell->getPort(ID::E);
|
||||
}
|
||||
} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
|
||||
is_fine = true;
|
||||
sig_d = cell->getPort(ID::D);
|
||||
has_clk = true;
|
||||
pol_clk = type_str[9] == 'P';
|
||||
sig_clk = cell->getPort(ID::C);
|
||||
has_srst = true;
|
||||
pol_srst = type_str[10] == 'P';
|
||||
sig_srst = cell->getPort(ID::R);
|
||||
val_srst = type_str[11] == '1' ? State::S1 : State::S0;
|
||||
has_ce = true;
|
||||
pol_ce = type_str[12] == 'P';
|
||||
sig_ce = cell->getPort(ID::E);
|
||||
ce_over_srst = true;
|
||||
info.is_fine = true;
|
||||
info.has_clk = true;
|
||||
info.pol_clk = type_str[9] == 'P';
|
||||
info.has_srst = true;
|
||||
info.pol_srst = type_str[10] == 'P';
|
||||
info.val_srst = type_str[11] == '1' ? State::S1 : State::S0;
|
||||
info.has_ce = true;
|
||||
info.pol_ce = type_str[12] == 'P';
|
||||
info.ce_over_srst = true;
|
||||
if constexpr (have_cell) {
|
||||
info.sig_d = cell->getPort(ID::D);
|
||||
info.sig_clk = cell->getPort(ID::C);
|
||||
info.sig_srst = cell->getPort(ID::R);
|
||||
info.sig_ce = cell->getPort(ID::E);
|
||||
}
|
||||
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
|
||||
is_fine = true;
|
||||
has_aload = true;
|
||||
sig_ad = cell->getPort(ID::D);
|
||||
has_aload = true;
|
||||
pol_aload = type_str[9] == 'P';
|
||||
sig_aload = cell->getPort(ID::E);
|
||||
info.is_fine = true;
|
||||
info.has_aload = true;
|
||||
info.has_aload = true;
|
||||
info.pol_aload = type_str[9] == 'P';
|
||||
if constexpr (have_cell) {
|
||||
info.sig_ad = cell->getPort(ID::D);
|
||||
info.sig_aload = cell->getPort(ID::E);
|
||||
}
|
||||
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
|
||||
is_fine = true;
|
||||
has_aload = true;
|
||||
sig_ad = cell->getPort(ID::D);
|
||||
has_aload = true;
|
||||
pol_aload = type_str[9] == 'P';
|
||||
sig_aload = cell->getPort(ID::E);
|
||||
has_arst = true;
|
||||
pol_arst = type_str[10] == 'P';
|
||||
sig_arst = cell->getPort(ID::R);
|
||||
val_arst = type_str[11] == '1' ? State::S1 : State::S0;
|
||||
info.is_fine = true;
|
||||
info.has_aload = true;
|
||||
info.has_aload = true;
|
||||
info.pol_aload = type_str[9] == 'P';
|
||||
info.has_arst = true;
|
||||
info.pol_arst = type_str[10] == 'P';
|
||||
info.val_arst = type_str[11] == '1' ? State::S1 : State::S0;
|
||||
if constexpr (have_cell) {
|
||||
info.sig_ad = cell->getPort(ID::D);
|
||||
info.sig_aload = cell->getPort(ID::E);
|
||||
info.sig_arst = cell->getPort(ID::R);
|
||||
}
|
||||
} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
|
||||
is_fine = true;
|
||||
has_aload = true;
|
||||
sig_ad = cell->getPort(ID::D);
|
||||
has_aload = true;
|
||||
pol_aload = type_str[11] == 'P';
|
||||
sig_aload = cell->getPort(ID::E);
|
||||
has_sr = true;
|
||||
pol_set = type_str[12] == 'P';
|
||||
pol_clr = type_str[13] == 'P';
|
||||
sig_set = cell->getPort(ID::S);
|
||||
sig_clr = cell->getPort(ID::R);
|
||||
info.is_fine = true;
|
||||
info.has_aload = true;
|
||||
info.has_aload = true;
|
||||
info.pol_aload = type_str[11] == 'P';
|
||||
info.has_sr = true;
|
||||
info.pol_set = type_str[12] == 'P';
|
||||
info.pol_clr = type_str[13] == 'P';
|
||||
if constexpr (have_cell) {
|
||||
info.sig_ad = cell->getPort(ID::D);
|
||||
info.sig_aload = cell->getPort(ID::E);
|
||||
info.sig_set = cell->getPort(ID::S);
|
||||
info.sig_clr = cell->getPort(ID::R);
|
||||
}
|
||||
} else {
|
||||
log_assert(0);
|
||||
}
|
||||
if (has_aload && !has_clk && !has_sr && !has_arst && sig_ad.is_fully_const()) {
|
||||
// Plain D latches with const D treated specially.
|
||||
has_aload = false;
|
||||
has_arst = true;
|
||||
sig_arst = sig_aload;
|
||||
pol_arst = pol_aload;
|
||||
val_arst = sig_ad.as_const();
|
||||
}
|
||||
if constexpr (have_cell)
|
||||
if (info.has_aload && !info.has_clk && !info.has_sr && !info.has_arst && info.sig_ad.is_fully_const()) {
|
||||
// Plain D latches with const D treated specially.
|
||||
info.has_aload = false;
|
||||
info.has_arst = true;
|
||||
info.sig_arst = info.sig_aload;
|
||||
info.pol_arst = info.pol_aload;
|
||||
info.val_arst = info.sig_ad.as_const();
|
||||
}
|
||||
}
|
||||
|
||||
FfTypeData::FfTypeData(IdString type) : FfTypeData()
|
||||
{
|
||||
manufacture_info(type, *this, nullptr);
|
||||
}
|
||||
|
||||
FfData::FfData(FfInitVals *initvals, Cell *cell_) : FfData(cell_->module, initvals, cell_->name)
|
||||
{
|
||||
cell = cell_;
|
||||
manufacture_info(cell, *this, initvals);
|
||||
}
|
||||
|
||||
FfData FfData::slice(const std::vector<int> &bits) {
|
||||
|
|
78
kernel/ff.h
78
kernel/ff.h
|
@ -78,31 +78,20 @@ YOSYS_NAMESPACE_BEGIN
|
|||
// - has_arst [does not correspond to a native cell, represented as dlatch with const D input]
|
||||
// - empty set [not a cell — will be emitted as a simple direct connection]
|
||||
|
||||
struct FfData {
|
||||
Module *module;
|
||||
FfInitVals *initvals;
|
||||
Cell *cell;
|
||||
IdString name;
|
||||
// The FF output.
|
||||
SigSpec sig_q;
|
||||
// The sync data input, present if has_clk or has_gclk.
|
||||
SigSpec sig_d;
|
||||
// The async data input, present if has_aload.
|
||||
SigSpec sig_ad;
|
||||
// The sync clock, present if has_clk.
|
||||
SigSpec sig_clk;
|
||||
// The clock enable, present if has_ce.
|
||||
SigSpec sig_ce;
|
||||
// The async load enable, present if has_aload.
|
||||
SigSpec sig_aload;
|
||||
// The async reset, preset if has_arst.
|
||||
SigSpec sig_arst;
|
||||
// The sync reset, preset if has_srst.
|
||||
SigSpec sig_srst;
|
||||
// The async clear (per-lane), present if has_sr.
|
||||
SigSpec sig_clr;
|
||||
// The async set (per-lane), present if has_sr.
|
||||
SigSpec sig_set;
|
||||
struct FfTypeData {
|
||||
FfTypeData(IdString type);
|
||||
FfTypeData() {
|
||||
has_clk = false;
|
||||
has_gclk = false;
|
||||
has_ce = false;
|
||||
has_aload = false;
|
||||
has_srst = false;
|
||||
has_arst = false;
|
||||
has_sr = false;
|
||||
ce_over_srst = false;
|
||||
is_fine = false;
|
||||
is_anyinit = false;
|
||||
}
|
||||
// True if this is a clocked (edge-sensitive) flip-flop.
|
||||
bool has_clk;
|
||||
// True if this is a $ff, exclusive with every other has_*.
|
||||
|
@ -143,9 +132,38 @@ struct FfData {
|
|||
bool pol_clr;
|
||||
bool pol_set;
|
||||
// The value loaded by sig_arst.
|
||||
// Zero length if unknowable from just type
|
||||
Const val_arst;
|
||||
// The value loaded by sig_srst.
|
||||
// Zero length if unknowable from just type
|
||||
Const val_srst;
|
||||
};
|
||||
|
||||
struct FfData : FfTypeData {
|
||||
Module *module;
|
||||
FfInitVals *initvals;
|
||||
Cell *cell;
|
||||
IdString name;
|
||||
// The FF output.
|
||||
SigSpec sig_q;
|
||||
// The sync data input, present if has_clk or has_gclk.
|
||||
SigSpec sig_d;
|
||||
// The async data input, present if has_aload.
|
||||
SigSpec sig_ad;
|
||||
// The sync clock, present if has_clk.
|
||||
SigSpec sig_clk;
|
||||
// The clock enable, present if has_ce.
|
||||
SigSpec sig_ce;
|
||||
// The async load enable, present if has_aload.
|
||||
SigSpec sig_aload;
|
||||
// The async reset, preset if has_arst.
|
||||
SigSpec sig_arst;
|
||||
// The sync reset, preset if has_srst.
|
||||
SigSpec sig_srst;
|
||||
// The async clear (per-lane), present if has_sr.
|
||||
SigSpec sig_clr;
|
||||
// The async set (per-lane), present if has_sr.
|
||||
SigSpec sig_set;
|
||||
// The initial value at power-up.
|
||||
Const val_init;
|
||||
// The FF data width in bits.
|
||||
|
@ -154,16 +172,6 @@ struct FfData {
|
|||
|
||||
FfData(Module *module = nullptr, FfInitVals *initvals = nullptr, IdString name = IdString()) : module(module), initvals(initvals), cell(nullptr), name(name) {
|
||||
width = 0;
|
||||
has_clk = false;
|
||||
has_gclk = false;
|
||||
has_ce = false;
|
||||
has_aload = false;
|
||||
has_srst = false;
|
||||
has_arst = false;
|
||||
has_sr = false;
|
||||
ce_over_srst = false;
|
||||
is_fine = false;
|
||||
is_anyinit = false;
|
||||
pol_clk = false;
|
||||
pol_aload = false;
|
||||
pol_ce = false;
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue