mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-05 02:40:25 +00:00
Code Activity

Revert "SigSet<Cell*> to use stable compare class"

Browse source 
This reverts commit 4ea34aaacd.
This commit is contained in:
Eddie Hung 2019-09-13 09:49:15 -07:00
parent c487a8ff25
commit 95e80809a5
5 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/opt/opt_reduce.cc
View file

@ -37,7 +37,7 @@ struct OptReduceWorker
int total_count;
bool did_something;
void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> &drivers, RTLIL::Cell *cell)
void opt_reduce(pool<RTLIL::Cell*> &cells, SigSet<RTLIL::Cell*> &drivers, RTLIL::Cell *cell)
{
if (cells.count(cell) == 0)
return;
@ -289,7 +289,7 @@ struct OptReduceWorker
const IdString type_list[] = { ID($reduce_or), ID($reduce_and) };
for (auto type : type_list)
{
SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> drivers;
SigSet<RTLIL::Cell*> drivers;
pool<RTLIL::Cell*> cells;
for (auto &cell_it : module->cells_) {