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https://github.com/YosysHQ/yosys
synced 2025-04-26 18:45:34 +00:00
formalff: New -setundef option
Find FFs with undefined initialization values for which changing the initialization does not change the observable behavior and initialize them. For -ff2anyinit, this reduces the number of generated $anyinit cells that drive wires with private names.
This commit is contained in:
Jannis Harder
parent
a5e1d3b997
commit
95db5a9d38
1 changed files with 335 additions and 0 deletions
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@ -21,10 +21,302 @@
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#include "kernel/sigtools.h"
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#include "kernel/ffinit.h"
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#include "kernel/ff.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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// Finds signal values with known constant or known unused values in the initial state
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struct InitValWorker
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{
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Module *module;
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ModWalker modwalker;
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SigMap &sigmap;
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FfInitVals initvals;
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dict<RTLIL::SigBit, RTLIL::State> initconst_bits;
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dict<RTLIL::SigBit, bool> used_bits;
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InitValWorker(Module *module) : module(module), modwalker(module->design), sigmap(modwalker.sigmap)
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{
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modwalker.setup(module);
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initvals.set(&modwalker.sigmap, module);
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for (auto wire : module->wires())
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if (wire->name.isPublic() || wire->get_bool_attribute(ID::keep))
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for (auto bit : SigSpec(wire))
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used_bits[sigmap(bit)] = true;
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}
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// Sign/Zero-extended indexing of individual port bits
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static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::IdString sign, int index)
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{
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auto sig_port = cell->getPort(port);
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if (index < GetSize(sig_port))
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return sig_port[index];
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else if (cell->getParam(sign).as_bool())
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return GetSize(sig_port) > 0 ? sig_port[GetSize(sig_port) - 1] : State::Sx;
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else
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return State::S0;
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}
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// Has the signal a known constant value in the initial state?
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//
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// For sync-only FFs outputs, this is their initval. For logic loops,
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// multiple drivers or unknown cells this is Sx. For a small number of
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// handled cells we recurse through their inputs. All results are cached.
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RTLIL::State initconst(SigBit bit)
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{
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sigmap.apply(bit);
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if (!bit.is_wire())
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return bit.data;
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auto it = initconst_bits.find(bit);
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if (it != initconst_bits.end())
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return it->second;
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// Setting this temporarily to x takes care of any logic loops
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initconst_bits[bit] = State::Sx;
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pool<ModWalker::PortBit> portbits;
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modwalker.get_drivers(portbits, {bit});
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if (portbits.size() != 1)
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return State::Sx;
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ModWalker::PortBit portbit = *portbits.begin();
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RTLIL::Cell *cell = portbit.cell;
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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{
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FfData ff(&initvals, cell);
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if (ff.has_aload || ff.has_sr || ff.has_arst || (!ff.has_clk && !ff.has_gclk)) {
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for (auto bit_q : ff.sig_q) {
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initconst_bits[sigmap(bit_q)] = State::Sx;
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}
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return State::Sx;
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}
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for (int i = 0; i < ff.width; i++) {
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initconst_bits[sigmap(ff.sig_q[i])] = ff.val_init[i];
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}
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return ff.val_init[portbit.offset];
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}
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if (cell->type.in(ID($mux), ID($and), ID($or), ID($eq), ID($eqx), ID($initstate)))
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{
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if (cell->type == ID($mux))
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{
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SigBit sig_s = sigmap(cell->getPort(ID::S));
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State init_s = initconst(sig_s);
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State init_y;
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if (init_s == State::S0) {
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init_y = initconst(cell->getPort(ID::A)[portbit.offset]);
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} else if (init_s == State::S1) {
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init_y = initconst(cell->getPort(ID::B)[portbit.offset]);
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} else {
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State init_a = initconst(cell->getPort(ID::A)[portbit.offset]);
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State init_b = initconst(cell->getPort(ID::B)[portbit.offset]);
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init_y = init_a == init_b ? init_a : State::Sx;
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}
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type.in(ID($and), ID($or)))
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{
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State init_a = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, portbit.offset));
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State init_b = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, portbit.offset));
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State init_y;
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if (init_a == init_b)
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init_y = init_a;
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else if (cell->type == ID($and) && (init_a == State::S0 || init_b == State::S0))
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init_y = State::S0;
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else if (cell->type == ID($or) && (init_a == State::S1 || init_b == State::S1))
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init_y = State::S1;
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else
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init_y = State::Sx;
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type.in(ID($eq), ID($eqx))) // Treats $eqx as $eq
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{
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if (portbit.offset > 0) {
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initconst_bits[bit] = State::S0;
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return State::S0;
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}
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SigSpec sig_a = cell->getPort(ID::A);
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SigSpec sig_b = cell->getPort(ID::B);
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State init_y = State::S1;
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for (int i = 0; init_y != State::S0 && i < GetSize(sig_a); i++) {
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State init_ai = initconst(bit_in_port(cell, ID::A, ID::A_SIGNED, i));
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if (init_ai == State::Sx) {
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init_y = State::Sx;
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continue;
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}
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State init_bi = initconst(bit_in_port(cell, ID::B, ID::B_SIGNED, i));
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if (init_bi == State::Sx)
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init_y = State::Sx;
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else if (init_ai != init_bi)
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init_y = State::S0;
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}
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initconst_bits[bit] = init_y;
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return init_y;
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}
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if (cell->type == ID($initstate))
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{
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initconst_bits[bit] = State::S1;
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return State::S1;
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}
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log_assert(false);
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}
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return State::Sx;
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}
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RTLIL::Const initconst(SigSpec sig)
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{
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std::vector<RTLIL::State> bits;
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for (auto bit : sig)
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bits.push_back(initconst(bit));
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return bits;
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}
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// Is the initial value of this signal used?
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//
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// An initial value of a signal is considered as used if it a) aliases a
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// wire with a public name, an output wire or with a keep attribute b)
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// combinationally drives such a wire or c) drive an input to an unknown
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// cell.
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//
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// This recurses into driven cells for a small number of known handled
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// celltypes. Results are cached and initconst is used to detect unused
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// inputs for the handled celltypes.
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bool is_initval_used(SigBit bit)
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{
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if (!bit.is_wire())
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return false;
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auto it = used_bits.find(bit);
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if (it != used_bits.end())
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return it->second;
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used_bits[bit] = true; // Temporarily set to guard against logic loops
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pool<ModWalker::PortBit> portbits;
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modwalker.get_consumers(portbits, {bit});
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for (auto portbit : portbits) {
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RTLIL::Cell *cell = portbit.cell;
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if (!cell->type.in(ID($mux), ID($and), ID($or), ID($mem_v2)) && !RTLIL::builtin_ff_cell_types().count(cell->type)) {
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return true;
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}
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}
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for (auto portbit : portbits)
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{
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RTLIL::Cell *cell = portbit.cell;
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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{
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FfData ff(&initvals, cell);
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if (ff.has_aload || ff.has_sr || ff.has_arst || ff.has_gclk || !ff.has_clk)
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return true;
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if (ff.has_ce && initconst(ff.sig_ce.as_bit()) == (ff.pol_ce ? State::S0 : State::S1))
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continue;
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if (ff.has_srst && initconst(ff.sig_ce.as_bit()) == (ff.pol_srst ? State::S1 : State::S0))
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continue;
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return true;
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}
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else if (cell->type == ID($mux))
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{
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State init_s = initconst(cell->getPort(ID::S).as_bit());
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if (init_s == State::S0 && portbit.port == ID::B)
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continue;
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if (init_s == State::S1 && portbit.port == ID::A)
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continue;
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auto sig_y = cell->getPort(ID::Y);
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if (is_initval_used(sig_y[portbit.offset]))
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return true;
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}
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else if (cell->type.in(ID($and), ID($or)))
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{
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auto sig_a = cell->getPort(ID::A);
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auto sig_b = cell->getPort(ID::B);
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auto sig_y = cell->getPort(ID::Y);
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if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b))
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return true; // TODO handle more of this
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State absorbing = cell->type == ID($and) ? State::S0 : State::S1;
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if (portbit.port == ID::A && initconst(sig_b[portbit.offset]) == absorbing)
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continue;
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if (portbit.port == ID::B && initconst(sig_a[portbit.offset]) == absorbing)
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continue;
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if (is_initval_used(sig_y[portbit.offset]))
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return true;
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}
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else if (cell->type == ID($mem_v2))
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{
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// TODO Use mem.h instead to uniformily cover all cases, most
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// likely requires processing all memories when initializing
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// the worker
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if (!portbit.port.in(ID::WR_DATA, ID::WR_ADDR, ID::RD_ADDR))
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return true;
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if (portbit.port == ID::WR_DATA)
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{
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if (initconst(cell->getPort(ID::WR_EN)[portbit.offset]) == State::S0)
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continue;
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}
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else if (portbit.port == ID::WR_ADDR)
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{
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int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
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auto sig_en = cell->getPort(ID::WR_EN);
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int width = cell->getParam(ID::WIDTH).as_int();
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for (int i = port * width; i < (port + 1) * width; i++)
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if (initconst(sig_en[i]) != State::S0)
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return true;
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continue;
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}
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else if (portbit.port == ID::RD_ADDR)
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{
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int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
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auto sig_en = cell->getPort(ID::RD_EN);
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if (initconst(sig_en[port]) != State::S0)
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return true;
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continue;
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}
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else
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return true;
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}
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else
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log_assert(false);
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}
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used_bits[bit] = false;
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return false;
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}
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};
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struct FormalFfPass : public Pass {
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FormalFfPass() : Pass("formalff", "prepare FFs for formal") { }
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void help() override
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@ -64,6 +356,12 @@ struct FormalFfPass : public Pass {
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log(" Emit fine-grained $_FF_ cells instead of coarse-grained $ff cells for\n");
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log(" -anyinit2ff. Cannot be combined with -clk2ff or -ff2anyinit.\n");
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log("\n");
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log(" -setundef\n");
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log(" Find FFs with undefined initialization values for which changing the\n");
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log(" initialization does not change the observable behavior and initialize\n");
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log(" them. For -ff2anyinit, this reduces the number of generated $anyinit\n");
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log(" cells that drive wires with private names.\n");
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log("\n");
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// TODO: An option to check whether all FFs use the same clock before changing it to the global clock
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}
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@ -73,6 +371,7 @@ struct FormalFfPass : public Pass {
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bool flag_ff2anyinit = false;
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bool flag_anyinit2ff = false;
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bool flag_fine = false;
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bool flag_setundef = false;
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log_header(design, "Executing FORMALFF pass.\n");
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@ -95,6 +394,10 @@ struct FormalFfPass : public Pass {
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flag_fine = true;
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continue;
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}
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if (args[argidx] == "-setundef") {
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flag_setundef = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -113,6 +416,38 @@ struct FormalFfPass : public Pass {
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for (auto module : design->selected_modules())
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{
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if (flag_setundef)
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{
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InitValWorker worker(module);
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for (auto cell : module->selected_cells())
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{
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if (RTLIL::builtin_ff_cell_types().count(cell->type))
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{
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FfData ff(&worker.initvals, cell);
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if (ff.has_aload || ff.has_sr || ff.has_arst || ff.val_init.is_fully_def())
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continue;
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if (ff.has_ce && // CE can make the initval stick around
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worker.initconst(ff.sig_ce.as_bit()) != (ff.pol_ce ? State::S1 : State::S0) && // unless it's known active
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(!ff.has_srst || ff.ce_over_srst ||
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worker.initconst(ff.sig_srst.as_bit()) != (ff.pol_srst ? State::S1 : State::S0))) // or a srst with priority is known active
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continue;
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auto before = ff.val_init;
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for (int i = 0; i < ff.width; i++)
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if (ff.val_init[i] == State::Sx && !worker.is_initval_used(ff.sig_q[i]))
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ff.val_init[i] = State::S0;
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if (ff.val_init != before) {
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log("Setting unused undefined initial value of %s.%s (%s) from %s to %s\n",
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log_id(module), log_id(cell), log_id(cell->type),
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log_const(before), log_const(ff.val_init));
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worker.initvals.set_init(ff.sig_q, ff.val_init);
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}
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}
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}
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}
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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