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					 3 changed files with 39 additions and 1 deletions
				
			
		|  | @ -27,6 +27,7 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk | |||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_brams.txt)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) | ||||
| $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) | ||||
|  |  | |||
|  | @ -438,7 +438,12 @@ struct SynthXilinxPass : public ScriptPass | |||
| 				run("memory_bram -rules +/xilinx/{family}_brams.txt"); | ||||
| 				run("techmap -map +/xilinx/{family}_brams_map.v"); | ||||
| 			} else if (!nobram) { | ||||
| 				if (family == "xc6s") { | ||||
| 				if (family == "xc3sda") { | ||||
| 					// Supported block RAMs for Spartan 3A DSP are
 | ||||
| 					// a subset of Spartan 6's ones.
 | ||||
| 					run("memory_bram -rules +/xilinx/xc3sda_brams.txt"); | ||||
| 					run("techmap -map +/xilinx/xc6s_brams_map.v"); | ||||
| 				} else if (family == "xc6s") { | ||||
| 					run("memory_bram -rules +/xilinx/xc6s_brams.txt"); | ||||
| 					run("techmap -map +/xilinx/xc6s_brams_map.v"); | ||||
| 				} else if (family == "xc6v" || family == "xc7") { | ||||
|  |  | |||
							
								
								
									
										32
									
								
								techlibs/xilinx/xc3sda_brams.txt
									
										
									
									
									
										Normal file
									
								
							
							
						
						
									
										32
									
								
								techlibs/xilinx/xc3sda_brams.txt
									
										
									
									
									
										Normal file
									
								
							|  | @ -0,0 +1,32 @@ | |||
| 
 | ||||
| bram $__XILINX_RAMB16BWER_TDP | ||||
|   init 1 | ||||
|   abits  9     @a9d36 | ||||
|   dbits 36     @a9d36 | ||||
|   abits 10     @a10d18 | ||||
|   dbits 18     @a10d18 | ||||
|   abits 11     @a11d9 | ||||
|   dbits  9     @a11d9 | ||||
|   abits 12     @a12d4 | ||||
|   dbits  4     @a12d4 | ||||
|   abits 13     @a13d2 | ||||
|   dbits  2     @a13d2 | ||||
|   abits 14     @a14d1 | ||||
|   dbits  1     @a14d1 | ||||
|   groups 2 | ||||
|   ports  1 1 | ||||
|   wrmode 0 1 | ||||
|   enable 1 4   @a9d36 | ||||
|   enable 1 2   @a10d18 | ||||
|   enable 1 1   @a11d9 @a12d4 @a13d2 @a14d1 | ||||
|   transp 0 0 | ||||
|   clocks 2 3 | ||||
|   clkpol 2 3 | ||||
| endbram | ||||
| 
 | ||||
| match $__XILINX_RAMB16BWER_TDP | ||||
|   min bits 4096 | ||||
|   min efficiency 5 | ||||
|   shuffle_enable B | ||||
|   make_transp | ||||
| endmatch | ||||
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