From 95a313e8379d3e876f24398612231152ef105966 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 22 Jan 2020 08:49:34 -0800
Subject: [PATCH] Revert "read_verilog: simplify ternary condition early,
 ignore unreach children"

This reverts commit dd3c3c0bdceb10bf960a77113131baf537859f04.
---
 frontends/ast/genrtlil.cc | 37 +++++++++++--------------------------
 frontends/ast/simplify.cc |  9 +++------
 2 files changed, 14 insertions(+), 32 deletions(-)

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index c6fd62ecf..94f5c0a04 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -769,10 +769,8 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
 		break;
 
 	case AST_TERNARY:
-		if (children.at(0)->type != AST_CONSTANT || children.at(0)->asBool())
-			children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
-		if (children.at(0)->type != AST_CONSTANT || !children.at(0)->asBool())
-			children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
+		children.at(1)->detectSignWidthWorker(width_hint, sign_hint, found_real);
+		children.at(2)->detectSignWidthWorker(width_hint, sign_hint, found_real);
 		break;
 
 	case AST_MEMRD:
@@ -1336,31 +1334,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				detectSignWidth(width_hint, sign_hint);
 
 			RTLIL::SigSpec cond = children[0]->genRTLIL();
-			RTLIL::SigSpec sig;
-			if (cond.is_fully_const()) {
-				if (cond.as_bool()) {
-					sig = children[1]->genRTLIL(width_hint, sign_hint);
-					widthExtend(this, sig, sig.size(), children[1]->is_signed);
-				}
-				else {
-					sig = children[2]->genRTLIL(width_hint, sign_hint);
-					widthExtend(this, sig, sig.size(), children[2]->is_signed);
-				}
-			}
-			else {
-				RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
-				RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
+			RTLIL::SigSpec val1 = children[1]->genRTLIL(width_hint, sign_hint);
+			RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
 
-				if (cond.size() > 1)
-					cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
+			if (cond.size() > 1)
+				cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false);
 
-				int width = max(val1.size(), val2.size());
-				is_signed = children[1]->is_signed && children[2]->is_signed;
-				widthExtend(this, val1, width, is_signed);
-				widthExtend(this, val2, width, is_signed);
+			int width = max(val1.size(), val2.size());
+			is_signed = children[1]->is_signed && children[2]->is_signed;
+			widthExtend(this, val1, width, is_signed);
+			widthExtend(this, val2, width, is_signed);
 
-				sig = mux2rtlil(this, cond, val1, val2);
-			}
+			RTLIL::SigSpec sig = mux2rtlil(this, cond, val1, val2);
 
 			if (sig.size() < width_hint)
 				sig.extend_u0(width_hint, sign_hint);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index e35168a2c..b94a8d710 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -572,7 +572,6 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	case AST_TERNARY:
 		detect_width_simple = true;
 		child_0_is_self_determined = true;
-		while (children[0]->simplify(true, false, false, 1, -1, false, false)) { }
 		break;
 
 	case AST_MEMRD:
@@ -606,11 +605,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
 	if (type == AST_TERNARY) {
 		int width_hint_left, width_hint_right;
 		bool sign_hint_left, sign_hint_right;
-		bool found_real_left = false, found_real_right = false;
-		if (children[0]->type != AST_CONSTANT || children[0]->asBool())
-			children[1]->detectSignWidth(width_hint_left, sign_hint_left, &found_real_left);
-		if (children[0]->type != AST_CONSTANT || !children[0]->asBool())
-			children[2]->detectSignWidth(width_hint_right, sign_hint_right, &found_real_right);
+		bool found_real_left, found_real_right;
+		children[1]->detectSignWidth(width_hint_left, sign_hint_left, &found_real_left);
+		children[2]->detectSignWidth(width_hint_right, sign_hint_right, &found_real_right);
 		if (found_real_left || found_real_right) {
 			child_1_is_self_determined = true;
 			child_2_is_self_determined = true;