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Another bugfix for ice40 and xilinx brams_init make rules
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parent
aedcfd6fd3
commit
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4 changed files with 9 additions and 9 deletions
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@ -3,7 +3,7 @@
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from __future__ import division
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from __future__ import print_function
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with open("brams_init_18.vh", "w") as f:
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with open("techlibs/xilinx/brams_init_18.vh", "w") as f:
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for i in range(8):
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init_snippets = ["INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
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for k in range(4, 256, 4):
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@ -15,7 +15,7 @@ with open("brams_init_18.vh", "w") as f:
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
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with open("brams_init_36.vh", "w") as f:
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with open("techlibs/xilinx/brams_init_36.vh", "w") as f:
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for i in range(16):
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init_snippets = ["INIT[%3d*9+8]" % (k+256*i,) for k in range(255, -1, -1)]
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for k in range(4, 256, 4):
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@ -27,11 +27,11 @@ with open("brams_init_36.vh", "w") as f:
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init_snippets[k] = "\n " + init_snippets[k]
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print(".INIT_%02X({%s})," % (i, ", ".join(init_snippets)), file=f)
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with open("brams_init_16.vh", "w") as f:
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with open("techlibs/xilinx/brams_init_16.vh", "w") as f:
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for i in range(64):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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with open("brams_init_32.vh", "w") as f:
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with open("techlibs/xilinx/brams_init_32.vh", "w") as f:
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for i in range(128):
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print(".INIT_%02X(INIT[%3d*256 +: 256])," % (i, i), file=f)
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