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Revert to pre-muxcover approach
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Eddie Hung
parent
d05ac7257e
commit
95867109ea
2 changed files with 84 additions and 27 deletions
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@ -150,24 +150,84 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
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endgenerate
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endgenerate
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endmodule
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endmodule
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`ifndef NO_MUXFN
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module \$shiftx (A, B, Y);
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module \$_MUX8_ (A, B, C, D, E, F, G, H, S, T, U, Y);
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parameter A_SIGNED = 0;
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input A, B, C, D, E, F, G, H, S, T, U;
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parameter B_SIGNED = 0;
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output Y;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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wire [1:0] Z;
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input [A_WIDTH-1:0] A;
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assign Z = T ? (S ? {D,H} : {C,G}) :
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input [B_WIDTH-1:0] B;
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(S ? {B,F} : {A,E});
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output [Y_WIDTH-1:0] Y;
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MUXF7 fpga_muxf7 (.I0(Z[0]), .I1(Z[1]), .S(U), .O(Y));
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
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parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
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generate
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genvar i, j;
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if (B_SIGNED) begin
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if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
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// Optimisation to remove B_SIGNED if sign bit of B is constant-0
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
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else
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wire _TECHMAP_FAIL_ = 1;
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end
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else if (Y_WIDTH > 1) begin
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for (i = 0; i < Y_WIDTH; i++)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
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end
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// If the LSB of B is constant zero (and Y_WIDTH is 1) then
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// we can optimise by removing every other entry from A
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// and popping the constant zero from B
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else if (_TECHMAP_CONSTMSK_B_[0] && !_TECHMAP_CONSTVAL_B_[0]) begin
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wire [(A_WIDTH+1)/2-1:0] A_i;
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for (i = 0; i < (A_WIDTH+1)/2; i++)
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assign A_i[i] = A[i*2];
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
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end
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else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
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wire _TECHMAP_FAIL_ = 1;
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end
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else if (B_WIDTH == 3) begin
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localparam a_width0 = 2 ** 2;
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localparam a_widthN = A_WIDTH - a_width0;
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wire T0, T1;
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
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MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
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end
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else if (B_WIDTH == 4) begin
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localparam a_width0 = 2 ** 2;
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localparam num_mux8 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux8*a_width0;
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wire [4-1:0] T;
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wire T0, T1;
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for (i = 0; i < 4; i++)
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if (i < num_mux8)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
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else if (i == num_mux8 && a_widthN > 0)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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else
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assign T[i] = 1'bx;
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MUXF7 fpga_mux_0 (.I0(T[0]), .I1(T[1]), .S(B[2]), .O(T0));
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MUXF7 fpga_mux_1 (.I0(T[2]), .I1(T[3]), .S(B[2]), .O(T1));
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MUXF8 fpga_mux_2 (.I0(T0), .I1(T1), .S(B[3]), .O(Y));
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end
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else begin
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localparam a_width0 = 2 ** 4;
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localparam num_mux16 = A_WIDTH / a_width0;
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localparam a_widthN = A_WIDTH - num_mux16*a_width0;
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wire [(2**(B_WIDTH-4))-1:0] T;
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for (i = 0; i < 2 ** (B_WIDTH-4); i++)
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if (i < num_mux16)
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
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else if (i == num_mux16 && a_widthN > 0) begin
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
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end
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else
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assign T[i] = 1'bx;
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\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
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end
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endgenerate
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endmodule
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endmodule
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module \$_MUX16_ (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V, Y);
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input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V;
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output Y;
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wire [1:0] Z;
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\$_MUX8_ fpga_mux8_0 (.A(A), .B(B), .C(C), .D(D), .E(E), .F(F), .G(G), .H(H), .S(S), .T(T), .U(U), .Y(Z[0]));
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\$_MUX8_ fpga_mux8_1 (.A(I), .B(J), .C(K), .D(L), .E(M), .F(N), .G(O), .H(P), .S(S), .T(T), .U(U), .Y(Z[1]));
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MUXF8 fpga_muxf8 (.I0(Z[0]), .I1(Z[1]), .S(V), .O(Y));
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endmodule
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`endif // NO_MUXFN
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@ -232,7 +232,7 @@ struct SynthXilinxPass : public ScriptPass
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// cells for identifying variable-length shift registers,
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// cells for identifying variable-length shift registers,
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// so attempt to convert $pmux-es to the former
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// so attempt to convert $pmux-es to the former
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// Also: wide multiplexer inference benefits from this too
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// Also: wide multiplexer inference benefits from this too
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if (!nosrl || !nomux || help_mode)
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if ((!nosrl && !nomux) || help_mode)
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run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
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run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
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run("opt -fast -full");
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run("opt -fast -full");
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@ -254,18 +254,15 @@ struct SynthXilinxPass : public ScriptPass
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run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
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run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
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}
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}
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if (!nomux || help_mode)
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run("techmap -map +/xilinx/cells_map.v");
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run("techmap");
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run("techmap");
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run("opt -fast");
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run("opt -fast");
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if (!nomux || help_mode)
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run("muxcover -mux8 -mux16");
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}
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}
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if (check_label("map_cells")) {
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if (check_label("map_cells")) {
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std::string define;
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run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
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if (nomux)
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define += " -D NO_MUXFN";
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run("techmap -map +/techmap.v -map +/xilinx/cells_map.v" + define);
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run("clean");
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run("clean");
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}
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}
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