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Support extended aiw format

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This commit is contained in:
Miodrag Milanovic 2022-02-27 16:37:40 +01:00
parent fca168797e
commit 9571acc0bf
1 changed files with 44 additions and 23 deletions
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67
passes/sat/sim.cc
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@ -1192,7 +1192,8 @@ struct SimWorker : SimShared
if (f.fail() || GetSize(sim_filename) == 0) if (f.fail() || GetSize(sim_filename) == 0)
log_error("Can not open file `%s`\n", sim_filename.c_str()); log_error("Can not open file `%s`\n", sim_filename.c_str());
bool init = true; int state = 0;
std::string status;
int cycle = 0; int cycle = 0;
top = new SimInstance(this, scope, topmod); top = new SimInstance(this, scope, topmod);
while (!f.eof()) while (!f.eof())
@ -1200,30 +1201,50 @@ struct SimWorker : SimShared
std::string line; std::string line;
std::getline(f, line); std::getline(f, line);
if (line.size()==0 || line[0]=='#') continue; if (line.size()==0 || line[0]=='#') continue;
if (init) { if (line[0]=='.') break;
if (state==0 && line.size()!=1) {
// old format detected, latch data
state = 2;
}
if (state==1 && line[0]!='b' && line[0]!='c') {
write_output_header(); write_output_header();
top->setState(latches, line); // was old format but with 1 bit latch
init = false; top->setState(latches, status);
} else { state = 3;
log("Simulating cycle %d.\n", cycle); }
top->setState(inputs, line);
if (cycle) { switch(state)
set_inports(clock, State::S1); {
set_inports(clockn, State::S0); case 0:
} else { status = line;
top->setState(inits, line); state = 1;
set_inports(clock, State::S0); break;
set_inports(clockn, State::S1); case 1:
} state = 2;
update(); break;
write_output_step(10*cycle); case 2:
if (cycle) { write_output_header();
set_inports(clock, State::S0); top->setState(latches, line);
set_inports(clockn, State::S1); break;
default:
if (cycle) {
set_inports(clock, State::S1);
set_inports(clockn, State::S0);
} else {
top->setState(inits, line);
set_inports(clock, State::S0);
set_inports(clockn, State::S1);
}
update(); update();
write_output_step(10*cycle + 5); write_output_step(10*cycle);
} if (cycle) {
cycle++; set_inports(clock, State::S0);
set_inports(clockn, State::S1);
update();
write_output_step(10*cycle + 5);
}
cycle++;
break;
} }
} }
write_output_step(10*cycle); write_output_step(10*cycle);