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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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36
backends/aiger/aiger.cc
View file

@ -126,9 +126,9 @@ struct AigerWriter
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(wire) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
init_map[initsig[i]] = initval[i] == State::S1; init_map[initsig[i]] = initval[i] == State::S1;
@ -169,7 +169,7 @@ struct AigerWriter
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "$_NOT_") if (cell->type == ID($_NOT_))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
@ -179,17 +179,17 @@ struct AigerWriter
continue; continue;
} }
if (cell->type.in("$_FF_", "$_DFF_N_", "$_DFF_P_")) if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
{ {
SigBit D = sigmap(cell->getPort("\\D").as_bit()); SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D); unused_bits.erase(D);
undriven_bits.erase(Q); undriven_bits.erase(Q);
ff_map[Q] = D; ff_map[Q] = D;
continue; continue;
} }
if (cell->type == "$_AND_") if (cell->type == ID($_AND_))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit()); SigBit B = sigmap(cell->getPort(ID::B).as_bit());
@ -201,7 +201,7 @@ struct AigerWriter
continue; continue;
} }
if (cell->type == "$initstate") if (cell->type == ID($initstate))
{ {
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
undriven_bits.erase(Y); undriven_bits.erase(Y);
@ -209,47 +209,47 @@ struct AigerWriter
continue; continue;
} }
if (cell->type == "$assert") if (cell->type == ID($assert))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A); unused_bits.erase(A);
unused_bits.erase(EN); unused_bits.erase(EN);
asserts.push_back(make_pair(A, EN)); asserts.push_back(make_pair(A, EN));
continue; continue;
} }
if (cell->type == "$assume") if (cell->type == ID($assume))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A); unused_bits.erase(A);
unused_bits.erase(EN); unused_bits.erase(EN);
assumes.push_back(make_pair(A, EN)); assumes.push_back(make_pair(A, EN));
continue; continue;
} }
if (cell->type == "$live") if (cell->type == ID($live))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A); unused_bits.erase(A);
unused_bits.erase(EN); unused_bits.erase(EN);
liveness.push_back(make_pair(A, EN)); liveness.push_back(make_pair(A, EN));
continue; continue;
} }
if (cell->type == "$fair") if (cell->type == ID($fair))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort("\\EN").as_bit()); SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
unused_bits.erase(A); unused_bits.erase(A);
unused_bits.erase(EN); unused_bits.erase(EN);
fairness.push_back(make_pair(A, EN)); fairness.push_back(make_pair(A, EN));
continue; continue;
} }
if (cell->type == "$anyconst") if (cell->type == ID($anyconst))
{ {
for (auto bit : sigmap(cell->getPort(ID::Y))) { for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit); undriven_bits.erase(bit);
@ -258,7 +258,7 @@ struct AigerWriter
continue; continue;
} }
if (cell->type == "$anyseq") if (cell->type == ID($anyseq))
{ {
for (auto bit : sigmap(cell->getPort(ID::Y))) { for (auto bit : sigmap(cell->getPort(ID::Y))) {
undriven_bits.erase(bit); undriven_bits.erase(bit);

36
backends/aiger/xaiger.cc
View file

@ -174,7 +174,7 @@ struct XAigerWriter
undriven_bits.insert(bit); undriven_bits.insert(bit);
unused_bits.insert(bit); unused_bits.insert(bit);
bool scc = wire->attributes.count(ID(abc9_scc)); bool scc = wire->attributes.count(ID::abc9_scc);
if (wire->port_input || scc) if (wire->port_input || scc)
input_bits.insert(bit); input_bits.insert(bit);
@ -190,7 +190,7 @@ struct XAigerWriter
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (!cell->has_keep_attr()) { if (!cell->has_keep_attr()) {
if (cell->type == "$_NOT_") if (cell->type == ID($_NOT_))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit()); SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
@ -200,7 +200,7 @@ struct XAigerWriter
continue; continue;
} }
if (cell->type == "$_AND_") if (cell->type == ID($_AND_))
{ {
SigBit A = sigmap(cell->getPort(ID::A).as_bit()); SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit()); SigBit B = sigmap(cell->getPort(ID::B).as_bit());
@ -212,13 +212,13 @@ struct XAigerWriter
continue; continue;
} }
if (cell->type == "$__ABC9_FF_" && if (cell->type == ID($__ABC9_FF_) &&
// The presence of an abc9_mergeability attribute indicates // The presence of an abc9_mergeability attribute indicates
// that we do want to pass this flop to ABC // that we do want to pass this flop to ABC
cell->attributes.count("\\abc9_mergeability")) cell->attributes.count(ID::abc9_mergeability))
{ {
SigBit D = sigmap(cell->getPort("\\D").as_bit()); SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort("\\Q").as_bit()); SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
unused_bits.erase(D); unused_bits.erase(D);
undriven_bits.erase(Q); undriven_bits.erase(Q);
alias_map[Q] = D; alias_map[Q] = D;
@ -227,7 +227,7 @@ struct XAigerWriter
continue; continue;
} }
if (cell->type.in("$specify2", "$specify3", "$specrule")) if (cell->type.in(ID($specify2), ID($specify3), ID($specrule)))
continue; continue;
} }
@ -239,7 +239,7 @@ struct XAigerWriter
bool abc9_flop = false; bool abc9_flop = false;
if (!cell->has_keep_attr()) { if (!cell->has_keep_attr()) {
auto it = cell->attributes.find("\\abc9_box_seq"); auto it = cell->attributes.find(ID::abc9_box_seq);
if (it != cell->attributes.end()) { if (it != cell->attributes.end()) {
int abc9_box_seq = it->second.as_int(); int abc9_box_seq = it->second.as_int();
if (GetSize(box_list) <= abc9_box_seq) if (GetSize(box_list) <= abc9_box_seq)
@ -247,7 +247,7 @@ struct XAigerWriter
box_list[abc9_box_seq] = cell; box_list[abc9_box_seq] = cell;
// Only flop boxes may have arrival times // Only flop boxes may have arrival times
// (all others are combinatorial) // (all others are combinatorial)
abc9_flop = inst_module->get_bool_attribute("\\abc9_flop"); abc9_flop = inst_module->get_bool_attribute(ID::abc9_flop);
if (!abc9_flop) if (!abc9_flop)
continue; continue;
} }
@ -315,7 +315,7 @@ struct XAigerWriter
RTLIL::Module* box_module = module->design->module(cell->type); RTLIL::Module* box_module = module->design->module(cell->type);
log_assert(box_module); log_assert(box_module);
log_assert(box_module->attributes.count("\\abc9_box_id") || box_module->get_bool_attribute("\\abc9_flop")); log_assert(box_module->attributes.count(ID::abc9_box_id) || box_module->get_bool_attribute(ID::abc9_flop));
auto r = box_ports.insert(cell->type); auto r = box_ports.insert(cell->type);
if (r.second) { if (r.second) {
@ -325,7 +325,7 @@ struct XAigerWriter
for (const auto &port_name : box_module->ports) { for (const auto &port_name : box_module->ports) {
auto w = box_module->wire(port_name); auto w = box_module->wire(port_name);
log_assert(w); log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) { if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) { if (w->port_input) {
if (carry_in != IdString()) if (carry_in != IdString())
log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module)); log_error("Module '%s' contains more than one 'abc9_carry' input port.\n", log_id(box_module));
@ -381,7 +381,7 @@ struct XAigerWriter
} }
// Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box // Connect <cell>.abc9_ff.Q (inserted by abc9_map.v) as the last input to the flop box
if (box_module->get_bool_attribute("\\abc9_flop")) { if (box_module->get_bool_attribute(ID::abc9_flop)) {
SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str())); SigSpec rhs = module->wire(stringf("%s.abc9_ff.Q", cell->name.c_str()));
if (rhs.empty()) if (rhs.empty())
log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module)); log_error("'%s.abc9_ff.Q' is not a wire present in module '%s'.\n", log_id(cell), log_id(module));
@ -437,7 +437,7 @@ struct XAigerWriter
for (const auto &i : ff_bits) { for (const auto &i : ff_bits) {
const Cell *cell = i.second; const Cell *cell = i.second;
const SigBit &q = sigmap(cell->getPort("\\Q")); const SigBit &q = sigmap(cell->getPort(ID::Q));
aig_m++, aig_i++; aig_m++, aig_i++;
log_assert(!aig_map.count(q)); log_assert(!aig_map.count(q));
aig_map[q] = 2*aig_m; aig_map[q] = 2*aig_m;
@ -608,12 +608,12 @@ struct XAigerWriter
// For flops only, create an extra 1-bit input that drives a new wire // For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below // called "<cell>.abc9_ff.Q" that is used below
if (box_module->get_bool_attribute("\\abc9_flop")) if (box_module->get_bool_attribute(ID::abc9_flop))
box_inputs++; box_inputs++;
std::get<0>(v) = box_inputs; std::get<0>(v) = box_inputs;
std::get<1>(v) = box_outputs; std::get<1>(v) = box_outputs;
std::get<2>(v) = box_module->attributes.at("\\abc9_box_id").as_int(); std::get<2>(v) = box_module->attributes.at(ID::abc9_box_id).as_int();
} }
write_h_buffer(std::get<0>(v)); write_h_buffer(std::get<0>(v));
@ -635,11 +635,11 @@ struct XAigerWriter
const SigBit &d = i.first; const SigBit &d = i.first;
const Cell *cell = i.second; const Cell *cell = i.second;
int mergeability = cell->attributes.at(ID(abc9_mergeability)).as_int(); int mergeability = cell->attributes.at(ID::abc9_mergeability).as_int();
log_assert(mergeability > 0); log_assert(mergeability > 0);
write_r_buffer(mergeability); write_r_buffer(mergeability);
Const init = cell->attributes.at(ID(abc9_init), State::Sx); Const init = cell->attributes.at(ID::abc9_init, State::Sx);
log_assert(GetSize(init) == 1); log_assert(GetSize(init) == 1);
if (init == State::S1) if (init == State::S1)
write_s_buffer(1); write_s_buffer(1);

86
backends/blif/blif.cc
View file

@ -69,9 +69,9 @@ struct BlifDumper
f(f), module(module), design(design), config(config), ct(design), sigmap(module) f(f), module(module), design(design), config(config), ct(design), sigmap(module)
{ {
for (Wire *wire : module->wires()) for (Wire *wire : module->wires())
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
switch (initval[i]) { switch (initval[i]) {
case State::S0: case State::S0:
@ -237,134 +237,134 @@ struct BlifDumper
continue; continue;
} }
if (!config->icells_mode && cell->type == "$_NOT_") { if (!config->icells_mode && cell->type == ID($_NOT_)) {
f << stringf(".names %s %s\n0 1\n", f << stringf(".names %s %s\n0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_AND_") { if (!config->icells_mode && cell->type == ID($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n", f << stringf(".names %s %s %s\n11 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_OR_") { if (!config->icells_mode && cell->type == ID($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n", f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_XOR_") { if (!config->icells_mode && cell->type == ID($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n", f << stringf(".names %s %s %s\n10 1\n01 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_NAND_") { if (!config->icells_mode && cell->type == ID($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n", f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_NOR_") { if (!config->icells_mode && cell->type == ID($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n", f << stringf(".names %s %s %s\n00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_XNOR_") { if (!config->icells_mode && cell->type == ID($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n", f << stringf(".names %s %s %s\n11 1\n00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_ANDNOT_") { if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n", f << stringf(".names %s %s %s\n10 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_ORNOT_") { if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n", f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_AOI3_") { if (!config->icells_mode && cell->type == ID($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n", f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_OAI3_") { if (!config->icells_mode && cell->type == ID($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n", f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort("\\C")), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_AOI4_") { if (!config->icells_mode && cell->type == ID($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n", f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_OAI4_") { if (!config->icells_mode && cell->type == ID($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n", f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort("\\C")), cstr(cell->getPort("\\D")), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::C)), cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_MUX_") { if (!config->icells_mode && cell->type == ID($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n", f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_NMUX_") { if (!config->icells_mode && cell->type == ID($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n", f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)), cstr(cell->getPort(ID::A)), cstr(cell->getPort(ID::B)),
cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y))); cstr(cell->getPort(ID::S)), cstr(cell->getPort(ID::Y)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_FF_") { if (!config->icells_mode && cell->type == ID($_FF_)) {
f << stringf(".latch %s %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), f << stringf(".latch %s %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
cstr_init(cell->getPort("\\Q"))); cstr_init(cell->getPort(ID::Q)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_DFF_N_") { if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), f << stringf(".latch %s %s fe %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_DFF_P_") { if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), f << stringf(".latch %s %s re %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
cstr(cell->getPort("\\C")), cstr_init(cell->getPort("\\Q"))); cstr(cell->getPort(ID::C)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_DLATCH_N_") { if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), f << stringf(".latch %s %s al %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$_DLATCH_P_") { if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort("\\D")), cstr(cell->getPort("\\Q")), f << stringf(".latch %s %s ah %s%s\n", cstr(cell->getPort(ID::D)), cstr(cell->getPort(ID::Q)),
cstr(cell->getPort("\\E")), cstr_init(cell->getPort("\\Q"))); cstr(cell->getPort(ID::E)), cstr_init(cell->getPort(ID::Q)));
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$lut") { if (!config->icells_mode && cell->type == ID($lut)) {
f << stringf(".names"); f << stringf(".names");
auto &inputs = cell->getPort(ID::A); auto &inputs = cell->getPort(ID::A);
auto width = cell->parameters.at("\\WIDTH").as_int(); auto width = cell->parameters.at(ID::WIDTH).as_int();
log_assert(inputs.size() == width); log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--) for (int i = width-1; i >= 0; i--)
f << stringf(" %s", cstr(inputs.extract(i, 1))); f << stringf(" %s", cstr(inputs.extract(i, 1)));
@ -372,7 +372,7 @@ struct BlifDumper
log_assert(output.size() == 1); log_assert(output.size() == 1);
f << stringf(" %s", cstr(output)); f << stringf(" %s", cstr(output));
f << stringf("\n"); f << stringf("\n");
RTLIL::SigSpec mask = cell->parameters.at("\\LUT"); RTLIL::SigSpec mask = cell->parameters.at(ID::LUT);
for (int i = 0; i < (1 << width); i++) for (int i = 0; i < (1 << width); i++)
if (mask[i] == State::S1) { if (mask[i] == State::S1) {
for (int j = width-1; j >= 0; j--) { for (int j = width-1; j >= 0; j--) {
@ -383,12 +383,12 @@ struct BlifDumper
goto internal_cell; goto internal_cell;
} }
if (!config->icells_mode && cell->type == "$sop") { if (!config->icells_mode && cell->type == ID($sop)) {
f << stringf(".names"); f << stringf(".names");
auto &inputs = cell->getPort(ID::A); auto &inputs = cell->getPort(ID::A);
auto width = cell->parameters.at("\\WIDTH").as_int(); auto width = cell->parameters.at(ID::WIDTH).as_int();
auto depth = cell->parameters.at("\\DEPTH").as_int(); auto depth = cell->parameters.at(ID::DEPTH).as_int();
vector<State> table = cell->parameters.at("\\TABLE").bits; vector<State> table = cell->parameters.at(ID::TABLE).bits;
while (GetSize(table) < 2*width*depth) while (GetSize(table) < 2*width*depth)
table.push_back(State::S0); table.push_back(State::S0);
log_assert(inputs.size() == width); log_assert(inputs.size() == width);

212
backends/btor/btor.cc
View file

@ -98,8 +98,8 @@ struct BtorWorker
string getinfo(T *obj, bool srcsym = false) string getinfo(T *obj, bool srcsym = false)
{ {
string infostr = log_id(obj); string infostr = log_id(obj);
if (obj->attributes.count("\\src")) { if (obj->attributes.count(ID::src)) {
string src = obj->attributes.at("\\src").decode_string().c_str(); string src = obj->attributes.at(ID::src).decode_string().c_str();
if (srcsym && infostr[0] == '$') { if (srcsym && infostr[0] == '$') {
std::replace(src.begin(), src.end(), ' ', '_'); std::replace(src.begin(), src.end(), ' ', '_');
if (srcsymbols.count(src) || module->count_id("\\" + src)) { if (srcsymbols.count(src) || module->count_id("\\" + src)) {
@ -183,40 +183,40 @@ struct BtorWorker
cell_recursion_guard.insert(cell); cell_recursion_guard.insert(cell);
btorf_push(log_id(cell)); btorf_push(log_id(cell));
if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx", if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
"$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_")) ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
{ {
string btor_op; string btor_op;
if (cell->type == "$add") btor_op = "add"; if (cell->type == ID($add)) btor_op = "add";
if (cell->type == "$sub") btor_op = "sub"; if (cell->type == ID($sub)) btor_op = "sub";
if (cell->type == "$mul") btor_op = "mul"; if (cell->type == ID($mul)) btor_op = "mul";
if (cell->type.in("$shl", "$sshl")) btor_op = "sll"; if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
if (cell->type == "$shr") btor_op = "srl"; if (cell->type == ID($shr)) btor_op = "srl";
if (cell->type == "$sshr") btor_op = "sra"; if (cell->type == ID($sshr)) btor_op = "sra";
if (cell->type.in("$shift", "$shiftx")) btor_op = "shift"; if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
if (cell->type.in("$and", "$_AND_")) btor_op = "and"; if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
if (cell->type.in("$or", "$_OR_")) btor_op = "or"; if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor"; if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
if (cell->type == "$concat") btor_op = "concat"; if (cell->type == ID($concat)) btor_op = "concat";
if (cell->type == "$_NAND_") btor_op = "nand"; if (cell->type == ID($_NAND_)) btor_op = "nand";
if (cell->type == "$_NOR_") btor_op = "nor"; if (cell->type == ID($_NOR_)) btor_op = "nor";
if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor"; if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A))); width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B))); width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
if (btor_op == "shift" && !b_signed) if (btor_op == "shift" && !b_signed)
btor_op = "srl"; btor_op = "srl";
if (cell->type.in("$shl", "$sshl", "$shr", "$sshr")) if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
b_signed = false; b_signed = false;
if (cell->type == "$sshr" && !a_signed) if (cell->type == ID($sshr) && !a_signed)
btor_op = "srl"; btor_op = "srl";
int sid = get_bv_sid(width); int sid = get_bv_sid(width);
@ -266,19 +266,19 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$div", "$mod")) if (cell->type.in(ID($div), ID($mod)))
{ {
string btor_op; string btor_op;
if (cell->type == "$div") btor_op = "div"; if (cell->type == ID($div)) btor_op = "div";
if (cell->type == "$mod") btor_op = "rem"; if (cell->type == ID($mod)) btor_op = "rem";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A))); width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B))); width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
@ -300,7 +300,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
{ {
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_a = get_sig_nid(cell->getPort(ID::A));
@ -309,12 +309,12 @@ struct BtorWorker
int nid1 = next_nid++; int nid1 = next_nid++;
int nid2 = next_nid++; int nid2 = next_nid++;
if (cell->type == "$_ANDNOT_") { if (cell->type == ID($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b); btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
} }
if (cell->type == "$_ORNOT_") { if (cell->type == ID($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b); btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str()); btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
} }
@ -324,24 +324,24 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$_OAI3_", "$_AOI3_")) if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
{ {
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C")); int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid1 = next_nid++; int nid1 = next_nid++;
int nid2 = next_nid++; int nid2 = next_nid++;
int nid3 = next_nid++; int nid3 = next_nid++;
if (cell->type == "$_OAI3_") { if (cell->type == ID($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c); btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str()); btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
} }
if (cell->type == "$_AOI3_") { if (cell->type == ID($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c); btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str()); btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
@ -352,27 +352,27 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$_OAI4_", "$_AOI4_")) if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
{ {
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B)); int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C")); int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_d = get_sig_nid(cell->getPort("\\D")); int nid_d = get_sig_nid(cell->getPort(ID::D));
int nid1 = next_nid++; int nid1 = next_nid++;
int nid2 = next_nid++; int nid2 = next_nid++;
int nid3 = next_nid++; int nid3 = next_nid++;
int nid4 = next_nid++; int nid4 = next_nid++;
if (cell->type == "$_OAI4_") { if (cell->type == ID($_OAI4_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2); btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str()); btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
} }
if (cell->type == "$_AOI4_") { if (cell->type == ID($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b); btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d); btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2); btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
@ -384,30 +384,30 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt")) if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
{ {
string btor_op; string btor_op;
if (cell->type == "$lt") btor_op = "lt"; if (cell->type == ID($lt)) btor_op = "lt";
if (cell->type == "$le") btor_op = "lte"; if (cell->type == ID($le)) btor_op = "lte";
if (cell->type.in("$eq", "$eqx")) btor_op = "eq"; if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
if (cell->type.in("$ne", "$nex")) btor_op = "neq"; if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
if (cell->type == "$ge") btor_op = "gte"; if (cell->type == ID($ge)) btor_op = "gte";
if (cell->type == "$gt") btor_op = "gt"; if (cell->type == ID($gt)) btor_op = "gt";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int width = 1; int width = 1;
width = std::max(width, GetSize(cell->getPort(ID::A))); width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B))); width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false; bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed); int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid = next_nid++; int nid = next_nid++;
if (cell->type.in("$lt", "$le", "$ge", "$gt")) { if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
} else { } else {
btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str()); btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
@ -426,16 +426,16 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$not", "$neg", "$_NOT_")) if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
{ {
string btor_op; string btor_op;
if (cell->type.in("$not", "$_NOT_")) btor_op = "not"; if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
if (cell->type == "$neg") btor_op = "neg"; if (cell->type == ID($neg)) btor_op = "neg";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y))); int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false; bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
int sid = get_bv_sid(width); int sid = get_bv_sid(width);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed); int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
@ -456,12 +456,12 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$logic_and", "$logic_or", "$logic_not")) if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
{ {
string btor_op; string btor_op;
if (cell->type == "$logic_and") btor_op = "and"; if (cell->type == ID($logic_and)) btor_op = "and";
if (cell->type == "$logic_or") btor_op = "or"; if (cell->type == ID($logic_or)) btor_op = "or";
if (cell->type == "$logic_not") btor_op = "not"; if (cell->type == ID($logic_not)) btor_op = "not";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
@ -500,12 +500,12 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor")) if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
{ {
string btor_op; string btor_op;
if (cell->type == "$reduce_and") btor_op = "redand"; if (cell->type == ID($reduce_and)) btor_op = "redand";
if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor"; if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor"; if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
log_assert(!btor_op.empty()); log_assert(!btor_op.empty());
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
@ -513,7 +513,7 @@ struct BtorWorker
int nid = next_nid++; int nid = next_nid++;
if (cell->type == "$reduce_xnor") { if (cell->type == ID($reduce_xnor)) {
int nid2 = next_nid++; int nid2 = next_nid++;
btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str()); btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d not %d %d %d\n", nid2, sid, nid); btorf("%d not %d %d %d\n", nid2, sid, nid);
@ -536,7 +536,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$mux", "$_MUX_", "$_NMUX_")) if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{ {
SigSpec sig_a = sigmap(cell->getPort(ID::A)); SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B)); SigSpec sig_b = sigmap(cell->getPort(ID::B));
@ -550,7 +550,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig_y)); int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++; int nid = next_nid++;
if (cell->type == "$_NMUX_") { if (cell->type == ID($_NMUX_)) {
int tmp = nid; int tmp = nid;
nid = next_nid++; nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a); btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
@ -563,7 +563,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type == "$pmux") if (cell->type == ID($pmux))
{ {
SigSpec sig_a = sigmap(cell->getPort(ID::A)); SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B)); SigSpec sig_b = sigmap(cell->getPort(ID::B));
@ -589,21 +589,21 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N_", "$_FF_")) if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
{ {
SigSpec sig_d = sigmap(cell->getPort("\\D")); SigSpec sig_d = sigmap(cell->getPort(ID::D));
SigSpec sig_q = sigmap(cell->getPort("\\Q")); SigSpec sig_q = sigmap(cell->getPort(ID::Q));
if (!info_filename.empty() && cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_")) if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
{ {
SigSpec sig_c = sigmap(cell->getPort(cell->type == "$dff" ? "\\CLK" : "\\C")); SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
int nid = get_sig_nid(sig_c); int nid = get_sig_nid(sig_c);
bool negedge = false; bool negedge = false;
if (cell->type == "$_DFF_N_") if (cell->type == ID($_DFF_N_))
negedge = true; negedge = true;
if (cell->type == "$dff" && !cell->getParam("\\CLK_POLARITY").as_bool()) if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
negedge = true; negedge = true;
info_clocks[nid] |= negedge ? 2 : 1; info_clocks[nid] |= negedge ? 2 : 1;
@ -651,7 +651,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type.in("$anyconst", "$anyseq")) if (cell->type.in(ID($anyconst), ID($anyseq)))
{ {
SigSpec sig_y = sigmap(cell->getPort(ID::Y)); SigSpec sig_y = sigmap(cell->getPort(ID::Y));
@ -660,7 +660,7 @@ struct BtorWorker
btorf("%d state %d\n", nid, sid); btorf("%d state %d\n", nid, sid);
if (cell->type == "$anyconst") { if (cell->type == ID($anyconst)) {
int nid2 = next_nid++; int nid2 = next_nid++;
btorf("%d next %d %d %d\n", nid2, sid, nid, nid); btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
} }
@ -669,7 +669,7 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type == "$initstate") if (cell->type == ID($initstate))
{ {
SigSpec sig_y = sigmap(cell->getPort(ID::Y)); SigSpec sig_y = sigmap(cell->getPort(ID::Y));
@ -688,16 +688,16 @@ struct BtorWorker
goto okay; goto okay;
} }
if (cell->type == "$mem") if (cell->type == ID($mem))
{ {
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int nwords = cell->getParam("\\SIZE").as_int(); int nwords = cell->getParam(ID::SIZE).as_int();
int rdports = cell->getParam("\\RD_PORTS").as_int(); int rdports = cell->getParam(ID::RD_PORTS).as_int();
int wrports = cell->getParam("\\WR_PORTS").as_int(); int wrports = cell->getParam(ID::WR_PORTS).as_int();
Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE"); Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE"); Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
bool asyncwr = wr_clk_en.is_fully_zero(); bool asyncwr = wr_clk_en.is_fully_zero();
@ -709,18 +709,18 @@ struct BtorWorker
log_error("Memory %s.%s has sync read ports.\n", log_error("Memory %s.%s has sync read ports.\n",
log_id(module), log_id(cell)); log_id(module), log_id(cell));
SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR")); SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA")); SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR")); SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA")); SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN")); SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width); int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1); int bool_sid = get_bv_sid(1);
int sid = get_mem_sid(abits, width); int sid = get_mem_sid(abits, width);
Const initdata = cell->getParam("\\INIT"); Const initdata = cell->getParam(ID::INIT);
initdata.exts(nwords*width); initdata.exts(nwords*width);
int nid_init_val = -1; int nid_init_val = -1;
@ -1053,8 +1053,8 @@ struct BtorWorker
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
Const attrval = wire->attributes.at("\\init"); Const attrval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++) for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
if (attrval[i] == State::S0 || attrval[i] == State::S1) if (attrval[i] == State::S0 || attrval[i] == State::S1)
initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1); initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
@ -1098,13 +1098,13 @@ struct BtorWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "$assume") if (cell->type == ID($assume))
{ {
btorf_push(log_id(cell)); btorf_push(log_id(cell));
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN")); int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_en = next_nid++; int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++; int nid_a_or_not_en = next_nid++;
int nid = next_nid++; int nid = next_nid++;
@ -1116,13 +1116,13 @@ struct BtorWorker
btorf_pop(log_id(cell)); btorf_pop(log_id(cell));
} }
if (cell->type == "$assert") if (cell->type == ID($assert))
{ {
btorf_push(log_id(cell)); btorf_push(log_id(cell));
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A)); int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN")); int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_a = next_nid++; int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++; int nid_en_and_not_a = next_nid++;
@ -1143,13 +1143,13 @@ struct BtorWorker
btorf_pop(log_id(cell)); btorf_pop(log_id(cell));
} }
if (cell->type == "$cover" && cover_mode) if (cell->type == ID($cover) && cover_mode)
{ {
btorf_push(log_id(cell)); btorf_push(log_id(cell));
int sid = get_bv_sid(1); int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort("\\A")); int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN")); int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_en_and_a = next_nid++; int nid_en_and_a = next_nid++;
btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a); btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
@ -1197,15 +1197,15 @@ struct BtorWorker
btorf_push(stringf("next %s", log_id(cell))); btorf_push(stringf("next %s", log_id(cell)));
if (cell->type == "$mem") if (cell->type == ID($mem))
{ {
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int wrports = cell->getParam("\\WR_PORTS").as_int(); int wrports = cell->getParam(ID::WR_PORTS).as_int();
SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR")); SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA")); SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN")); SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width); int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1); int bool_sid = get_bv_sid(1);
@ -1254,7 +1254,7 @@ struct BtorWorker
} }
else else
{ {
SigSpec sig = sigmap(cell->getPort("\\D")); SigSpec sig = sigmap(cell->getPort(ID::D));
int nid_q = get_sig_nid(sig); int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig)); int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str()); btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());

176
backends/firrtl/firrtl.cc
View file

@ -401,9 +401,9 @@ struct FirrtlWorker
{ {
const auto wireName = make_id(wire->name); const auto wireName = make_id(wire->name);
// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it. // If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
log_warning("Initial value (%s) for (%s.%s) not supported\n", log_warning("Initial value (%s) for (%s.%s) not supported\n",
wire->attributes.at("\\init").as_string().c_str(), wire->attributes.at(ID::init).as_string().c_str(),
log_id(module), log_id(wire)); log_id(module), log_id(wire));
} }
if (wire->port_id) if (wire->port_id)
@ -431,18 +431,18 @@ struct FirrtlWorker
} }
// Not a module instance. Set up cell properties // Not a module instance. Set up cell properties
bool extract_y_bits = false; // Assume no extraction of final bits will be required. bool extract_y_bits = false; // Assume no extraction of final bits will be required.
int a_width = cell->parameters.at("\\A_WIDTH", ndef).as_int(); // The width of "A" int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
int b_width = cell->parameters.at("\\B_WIDTH", ndef).as_int(); // The width of "A" int b_width = cell->parameters.at(ID::B_WIDTH, ndef).as_int(); // The width of "A"
const int y_width = cell->parameters.at("\\Y_WIDTH", ndef).as_int(); // The width of the result const int y_width = cell->parameters.at(ID::Y_WIDTH, ndef).as_int(); // The width of the result
const bool a_signed = cell->parameters.at("\\A_SIGNED", ndef).as_bool(); const bool a_signed = cell->parameters.at(ID::A_SIGNED, ndef).as_bool();
const bool b_signed = cell->parameters.at("\\B_SIGNED", ndef).as_bool(); const bool b_signed = cell->parameters.at(ID::B_SIGNED, ndef).as_bool();
bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this). bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this).
int firrtl_width = 0; int firrtl_width = 0;
string primop; string primop;
bool always_uint = false; bool always_uint = false;
string y_id = make_id(cell->name); string y_id = make_id(cell->name);
if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor")) if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{ {
string a_expr = make_expr(cell->getPort(ID::A)); string a_expr = make_expr(cell->getPort(ID::A));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
@ -452,29 +452,29 @@ struct FirrtlWorker
} }
// Don't use the results of logical operations (a single bit) to control padding // Don't use the results of logical operations (a single bit) to control padding
if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) { if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
} }
// Assume the FIRRTL width is a single bit. // Assume the FIRRTL width is a single bit.
firrtl_width = 1; firrtl_width = 1;
if (cell->type == "$not") primop = "not"; if (cell->type == ID($not)) primop = "not";
else if (cell->type == "$neg") { else if (cell->type == ID($neg)) {
primop = "neg"; primop = "neg";
firrtl_is_signed = true; // Result of "neg" is signed (an SInt). firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
firrtl_width = a_width; firrtl_width = a_width;
} else if (cell->type == "$logic_not") { } else if (cell->type == ID($logic_not)) {
primop = "eq"; primop = "eq";
a_expr = stringf("%s, UInt(0)", a_expr.c_str()); a_expr = stringf("%s, UInt(0)", a_expr.c_str());
} }
else if (cell->type == "$reduce_and") primop = "andr"; else if (cell->type == ID($reduce_and)) primop = "andr";
else if (cell->type == "$reduce_or") primop = "orr"; else if (cell->type == ID($reduce_or)) primop = "orr";
else if (cell->type == "$reduce_xor") primop = "xorr"; else if (cell->type == ID($reduce_xor)) primop = "xorr";
else if (cell->type == "$reduce_xnor") { else if (cell->type == ID($reduce_xnor)) {
primop = "not"; primop = "not";
a_expr = stringf("xorr(%s)", a_expr.c_str()); a_expr = stringf("xorr(%s)", a_expr.c_str());
} }
else if (cell->type == "$reduce_bool") { else if (cell->type == ID($reduce_bool)) {
primop = "neq"; primop = "neq";
// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand. // Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width); a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
@ -490,9 +490,9 @@ struct FirrtlWorker
continue; continue;
} }
if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx", if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl", ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
"$logic_and", "$logic_or", "$pow")) ID($logic_and), ID($logic_or), ID($pow)))
{ {
string a_expr = make_expr(cell->getPort(ID::A)); string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B)); string b_expr = make_expr(cell->getPort(ID::B));
@ -508,7 +508,7 @@ struct FirrtlWorker
} }
// Shift amount is always unsigned, and needn't be padded to result width, // Shift amount is always unsigned, and needn't be padded to result width,
// otherwise, we need to cast the b_expr appropriately // otherwise, we need to cast the b_expr appropriately
if (b_signed && !cell->type.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) { if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
b_expr = "asSInt(" + b_expr + ")"; b_expr = "asSInt(" + b_expr + ")";
// Expand the "B" operand to the result width // Expand the "B" operand to the result width
if (b_width < y_width) { if (b_width < y_width) {
@ -519,7 +519,7 @@ struct FirrtlWorker
// For the arithmetic ops, expand operand widths to result widths befor performing the operation. // For the arithmetic ops, expand operand widths to result widths befor performing the operation.
// This corresponds (according to iverilog) to what verilog compilers implement. // This corresponds (according to iverilog) to what verilog compilers implement.
if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or")) if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or)))
{ {
if (a_width < y_width) { if (a_width < y_width) {
a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width); a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
@ -534,78 +534,78 @@ struct FirrtlWorker
firrtl_width = a_width; firrtl_width = a_width;
auto a_sig = cell->getPort(ID::A); auto a_sig = cell->getPort(ID::A);
if (cell->type == "$add") { if (cell->type == ID($add)) {
primop = "add"; primop = "add";
firrtl_is_signed = a_signed | b_signed; firrtl_is_signed = a_signed | b_signed;
firrtl_width = max(a_width, b_width); firrtl_width = max(a_width, b_width);
} else if (cell->type == "$sub") { } else if (cell->type == ID($sub)) {
primop = "sub"; primop = "sub";
firrtl_is_signed = true; firrtl_is_signed = true;
int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0; int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0; int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc); firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
} else if (cell->type == "$mul") { } else if (cell->type == ID($mul)) {
primop = "mul"; primop = "mul";
firrtl_is_signed = a_signed | b_signed; firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width + b_width; firrtl_width = a_width + b_width;
} else if (cell->type == "$div") { } else if (cell->type == ID($div)) {
primop = "div"; primop = "div";
firrtl_is_signed = a_signed | b_signed; firrtl_is_signed = a_signed | b_signed;
firrtl_width = a_width; firrtl_width = a_width;
} else if (cell->type == "$mod") { } else if (cell->type == ID($mod)) {
primop = "rem"; primop = "rem";
firrtl_width = min(a_width, b_width); firrtl_width = min(a_width, b_width);
} else if (cell->type == "$and") { } else if (cell->type == ID($and)) {
primop = "and"; primop = "and";
always_uint = true; always_uint = true;
firrtl_width = max(a_width, b_width); firrtl_width = max(a_width, b_width);
} }
else if (cell->type == "$or" ) { else if (cell->type == ID($or) ) {
primop = "or"; primop = "or";
always_uint = true; always_uint = true;
firrtl_width = max(a_width, b_width); firrtl_width = max(a_width, b_width);
} }
else if (cell->type == "$xor") { else if (cell->type == ID($xor)) {
primop = "xor"; primop = "xor";
always_uint = true; always_uint = true;
firrtl_width = max(a_width, b_width); firrtl_width = max(a_width, b_width);
} }
else if (cell->type == "$xnor") { else if (cell->type == ID($xnor)) {
primop = "xnor"; primop = "xnor";
always_uint = true; always_uint = true;
firrtl_width = max(a_width, b_width); firrtl_width = max(a_width, b_width);
} }
else if ((cell->type == "$eq") | (cell->type == "$eqx")) { else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
primop = "eq"; primop = "eq";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if ((cell->type == "$ne") | (cell->type == "$nex")) { else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
primop = "neq"; primop = "neq";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if (cell->type == "$gt") { else if (cell->type == ID($gt)) {
primop = "gt"; primop = "gt";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if (cell->type == "$ge") { else if (cell->type == ID($ge)) {
primop = "geq"; primop = "geq";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if (cell->type == "$lt") { else if (cell->type == ID($lt)) {
primop = "lt"; primop = "lt";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if (cell->type == "$le") { else if (cell->type == ID($le)) {
primop = "leq"; primop = "leq";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if ((cell->type == "$shl") | (cell->type == "$sshl")) { else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
// FIRRTL will widen the result (y) by the amount of the shift. // FIRRTL will widen the result (y) by the amount of the shift.
// We'll need to offset this by extracting the un-widened portion as Verilog would do. // We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true; extract_y_bits = true;
@ -623,7 +623,7 @@ struct FirrtlWorker
firrtl_width = a_width + (1 << b_width) - 1; firrtl_width = a_width + (1 << b_width) - 1;
} }
} }
else if ((cell->type == "$shr") | (cell->type == "$sshr")) { else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
// We don't need to extract a specific range of bits. // We don't need to extract a specific range of bits.
extract_y_bits = false; extract_y_bits = false;
// Is the shift amount constant? // Is the shift amount constant?
@ -640,26 +640,26 @@ struct FirrtlWorker
// We'll need to do some special fixups if the source (and thus result) is signed. // We'll need to do some special fixups if the source (and thus result) is signed.
if (firrtl_is_signed) { if (firrtl_is_signed) {
// If this is a "logical" shift right, pretend the source is unsigned. // If this is a "logical" shift right, pretend the source is unsigned.
if (cell->type == "$shr") { if (cell->type == ID($shr)) {
a_expr = "asUInt(" + a_expr + ")"; a_expr = "asUInt(" + a_expr + ")";
} }
} }
} }
else if ((cell->type == "$logic_and")) { else if ((cell->type == ID($logic_and))) {
primop = "and"; primop = "and";
a_expr = "neq(" + a_expr + ", UInt(0))"; a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))"; b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if ((cell->type == "$logic_or")) { else if ((cell->type == ID($logic_or))) {
primop = "or"; primop = "or";
a_expr = "neq(" + a_expr + ", UInt(0))"; a_expr = "neq(" + a_expr + ", UInt(0))";
b_expr = "neq(" + b_expr + ", UInt(0))"; b_expr = "neq(" + b_expr + ", UInt(0))";
always_uint = true; always_uint = true;
firrtl_width = 1; firrtl_width = 1;
} }
else if ((cell->type == "$pow")) { else if ((cell->type == ID($pow))) {
if (a_sig.is_fully_const() && a_sig.as_int() == 2) { if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
// We'll convert this to a shift. To simplify things, change the a_expr to "1" // We'll convert this to a shift. To simplify things, change the a_expr to "1"
// so we can use b_expr directly as a shift amount. // so we can use b_expr directly as a shift amount.
@ -689,7 +689,7 @@ struct FirrtlWorker
} }
} }
if (!cell->parameters.at("\\B_SIGNED").as_bool()) { if (!cell->parameters.at(ID::B_SIGNED).as_bool()) {
b_expr = "asUInt(" + b_expr + ")"; b_expr = "asUInt(" + b_expr + ")";
} }
@ -718,9 +718,9 @@ struct FirrtlWorker
continue; continue;
} }
if (cell->type.in("$mux")) if (cell->type.in(ID($mux)))
{ {
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
string a_expr = make_expr(cell->getPort(ID::A)); string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B)); string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S)); string s_expr = make_expr(cell->getPort(ID::S));
@ -734,26 +734,26 @@ struct FirrtlWorker
continue; continue;
} }
if (cell->type.in("$mem")) if (cell->type.in(ID($mem)))
{ {
string mem_id = make_id(cell->name); string mem_id = make_id(cell->name);
int abits = cell->parameters.at("\\ABITS").as_int(); int abits = cell->parameters.at(ID::ABITS).as_int();
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
int size = cell->parameters.at("\\SIZE").as_int(); int size = cell->parameters.at(ID::SIZE).as_int();
memory m(cell, mem_id, abits, size, width); memory m(cell, mem_id, abits, size, width);
int rd_ports = cell->parameters.at("\\RD_PORTS").as_int(); int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
int wr_ports = cell->parameters.at("\\WR_PORTS").as_int(); int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
Const initdata = cell->parameters.at("\\INIT"); Const initdata = cell->parameters.at(ID::INIT);
for (State bit : initdata.bits) for (State bit : initdata.bits)
if (bit != State::Sx) if (bit != State::Sx)
log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell)); log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
Const rd_clk_enable = cell->parameters.at("\\RD_CLK_ENABLE"); Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
Const wr_clk_enable = cell->parameters.at("\\WR_CLK_ENABLE"); Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
Const wr_clk_polarity = cell->parameters.at("\\WR_CLK_POLARITY"); Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
int offset = cell->parameters.at("\\OFFSET").as_int(); int offset = cell->parameters.at(ID::OFFSET).as_int();
if (offset != 0) if (offset != 0)
log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell)); log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
@ -762,8 +762,8 @@ struct FirrtlWorker
if (rd_clk_enable[i] != State::S0) if (rd_clk_enable[i] != State::S0)
log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell)); log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits); SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width); SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
string addr_expr = make_expr(addr_sig); string addr_expr = make_expr(addr_sig);
string name(stringf("%s.r%d", m.name.c_str(), i)); string name(stringf("%s.r%d", m.name.c_str(), i));
bool clk_enable = false; bool clk_enable = false;
@ -789,14 +789,14 @@ struct FirrtlWorker
bool clk_enable = true; bool clk_enable = true;
bool clk_parity = true; bool clk_parity = true;
bool transparency = false; bool transparency = false;
SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits); SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
string addr_expr = make_expr(addr_sig); string addr_expr = make_expr(addr_sig);
SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width); SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
string data_expr = make_expr(data_sig); string data_expr = make_expr(data_sig);
SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i); SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
string clk_expr = make_expr(clk_sig); string clk_expr = make_expr(clk_sig);
SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width); SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
string wen_expr = make_expr(wen_sig[0]); string wen_expr = make_expr(wen_sig[0]);
for (int i = 1; i < GetSize(wen_sig); i++) for (int i = 1; i < GetSize(wen_sig); i++)
@ -813,23 +813,23 @@ struct FirrtlWorker
continue; continue;
} }
if (cell->type.in("$memwr", "$memrd", "$meminit")) if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
{ {
std::string cell_type = fid(cell->type); std::string cell_type = fid(cell->type);
std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string()); std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
int abits = cell->parameters.at("\\ABITS").as_int(); int abits = cell->parameters.at(ID::ABITS).as_int();
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
memory *mp = nullptr; memory *mp = nullptr;
if (cell->type == "$meminit" ) { if (cell->type == ID($meminit) ) {
log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str()); log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
} else { } else {
// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition. // It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
auto addrSig = cell->getPort("\\ADDR"); auto addrSig = cell->getPort(ID::ADDR);
auto dataSig = cell->getPort("\\DATA"); auto dataSig = cell->getPort(ID::DATA);
auto enableSig = cell->getPort("\\EN"); auto enableSig = cell->getPort(ID::EN);
auto clockSig = cell->getPort("\\CLK"); auto clockSig = cell->getPort(ID::CLK);
Const clk_enable = cell->parameters.at("\\CLK_ENABLE"); Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
Const clk_polarity = cell->parameters.at("\\CLK_POLARITY"); Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
// Do we already have an entry for this memory? // Do we already have an entry for this memory?
if (memories.count(mem_id) == 0) { if (memories.count(mem_id) == 0) {
@ -840,13 +840,13 @@ struct FirrtlWorker
int portNum = 0; int portNum = 0;
bool transparency = false; bool transparency = false;
string data_expr = make_expr(dataSig); string data_expr = make_expr(dataSig);
if (cell->type.in("$memwr")) { if (cell->type.in(ID($memwr))) {
portNum = (int) mp->write_ports.size(); portNum = (int) mp->write_ports.size();
write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig); write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
mp->add_memory_write_port(wp); mp->add_memory_write_port(wp);
cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str())); cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
cell_exprs.push_back(wp.gen_write(indent.c_str())); cell_exprs.push_back(wp.gen_write(indent.c_str()));
} else if (cell->type.in("$memrd")) { } else if (cell->type.in(ID($memrd))) {
portNum = (int) mp->read_ports.size(); portNum = (int) mp->read_ports.size();
read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig); read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
mp->add_memory_read_port(rp); mp->add_memory_read_port(rp);
@ -857,20 +857,20 @@ struct FirrtlWorker
continue; continue;
} }
if (cell->type.in("$dff")) if (cell->type.in(ID($dff)))
{ {
bool clkpol = cell->parameters.at("\\CLK_POLARITY").as_bool(); bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
if (clkpol == false) if (clkpol == false)
log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell)); log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
int width = cell->parameters.at("\\WIDTH").as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
string expr = make_expr(cell->getPort("\\D")); string expr = make_expr(cell->getPort(ID::D));
string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")"; string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str())); wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str())); cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
register_reverse_wire_map(y_id, cell->getPort("\\Q")); register_reverse_wire_map(y_id, cell->getPort(ID::Q));
continue; continue;
} }
@ -881,7 +881,7 @@ struct FirrtlWorker
process_instance(cell, wire_exprs); process_instance(cell, wire_exprs);
continue; continue;
} }
if (cell->type == "$shiftx") { if (cell->type == ID($shiftx)) {
// assign y = a[b +: y_width]; // assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop. // We'll extract the correct bits as part of the primop.
@ -890,10 +890,10 @@ struct FirrtlWorker
string b_expr = make_expr(cell->getPort(ID::B)); string b_expr = make_expr(cell->getPort(ID::B));
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
if (cell->getParam("\\B_SIGNED").as_bool()) { if (cell->getParam(ID::B_SIGNED).as_bool()) {
// Use validif to constrain the selection (test the sign bit) // Use validif to constrain the selection (test the sign bit)
auto b_string = b_expr.c_str(); auto b_string = b_expr.c_str();
int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1; int b_sign = cell->parameters.at(ID::B_WIDTH).as_int() - 1;
b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string); b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
} }
string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str()); string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
@ -902,7 +902,7 @@ struct FirrtlWorker
register_reverse_wire_map(y_id, cell->getPort(ID::Y)); register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue; continue;
} }
if (cell->type == "$shift") { if (cell->type == ID($shift)) {
// assign y = a >> b; // assign y = a >> b;
// where b may be negative // where b may be negative
@ -912,7 +912,7 @@ struct FirrtlWorker
string expr; string expr;
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width)); wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
if (cell->getParam("\\B_SIGNED").as_bool()) { if (cell->getParam(ID::B_SIGNED).as_bool()) {
// We generate a left or right shift based on the sign of b. // We generate a left or right shift based on the sign of b.
std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width); std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width);
std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string); std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
@ -928,7 +928,7 @@ struct FirrtlWorker
register_reverse_wire_map(y_id, cell->getPort(ID::Y)); register_reverse_wire_map(y_id, cell->getPort(ID::Y));
continue; continue;
} }
if (cell->type == "$pos") { if (cell->type == ID($pos)) {
// assign y = a; // assign y = a;
// printCell(cell); // printCell(cell);
string a_expr = make_expr(cell->getPort(ID::A)); string a_expr = make_expr(cell->getPort(ID::A));

52
backends/simplec/simplec.cc
View file

@ -378,7 +378,7 @@ struct SimplecWorker
void eval_cell(HierDirtyFlags *work, Cell *cell) void eval_cell(HierDirtyFlags *work, Cell *cell)
{ {
if (cell->type.in("$_BUF_", "$_NOT_")) if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{ {
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
@ -386,8 +386,8 @@ struct SimplecWorker
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr; string expr;
if (cell->type == "$_BUF_") expr = a_expr; if (cell->type == ID($_BUF_)) expr = a_expr;
if (cell->type == "$_NOT_") expr = "!" + a_expr; if (cell->type == ID($_NOT_)) expr = "!" + a_expr;
log_assert(y.wire); log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
@ -397,7 +397,7 @@ struct SimplecWorker
return; return;
} }
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{ {
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
@ -407,14 +407,14 @@ struct SimplecWorker
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0"; string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
string expr; string expr;
if (cell->type == "$_AND_") expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_AND_)) expr = stringf("%s & %s", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_NAND_") expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_NAND_)) expr = stringf("!(%s & %s)", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_OR_") expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_OR_)) expr = stringf("%s | %s", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_NOR_") expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_NOR_)) expr = stringf("!(%s | %s)", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_XOR_") expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_XOR_)) expr = stringf("%s ^ %s", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_XNOR_") expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_XNOR_)) expr = stringf("!(%s ^ %s)", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_ANDNOT_") expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_ANDNOT_)) expr = stringf("%s & (!%s)", a_expr.c_str(), b_expr.c_str());
if (cell->type == "$_ORNOT_") expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str()); if (cell->type == ID($_ORNOT_)) expr = stringf("%s | (!%s)", a_expr.c_str(), b_expr.c_str());
log_assert(y.wire); log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
@ -424,11 +424,11 @@ struct SimplecWorker
return; return;
} }
if (cell->type.in("$_AOI3_", "$_OAI3_")) if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{ {
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
@ -436,8 +436,8 @@ struct SimplecWorker
string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0"; string c_expr = c.wire ? util_get_bit(work->prefix + cid(c.wire->name), c.wire->width, c.offset) : c.data ? "1" : "0";
string expr; string expr;
if (cell->type == "$_AOI3_") expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); if (cell->type == ID($_AOI3_)) expr = stringf("!((%s & %s) | %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
if (cell->type == "$_OAI3_") expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str()); if (cell->type == ID($_OAI3_)) expr = stringf("!((%s | %s) & %s)", a_expr.c_str(), b_expr.c_str(), c_expr.c_str());
log_assert(y.wire); log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
@ -447,12 +447,12 @@ struct SimplecWorker
return; return;
} }
if (cell->type.in("$_AOI4_", "$_OAI4_")) if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{ {
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort("\\C")); SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit d = sigmaps.at(work->module)(cell->getPort("\\D")); SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y)); SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0"; string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
@ -461,8 +461,8 @@ struct SimplecWorker
string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0"; string d_expr = d.wire ? util_get_bit(work->prefix + cid(d.wire->name), d.wire->width, d.offset) : d.data ? "1" : "0";
string expr; string expr;
if (cell->type == "$_AOI4_") expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); if (cell->type == ID($_AOI4_)) expr = stringf("!((%s & %s) | (%s & %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
if (cell->type == "$_OAI4_") expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str()); if (cell->type == ID($_OAI4_)) expr = stringf("!((%s | %s) & (%s | %s))", a_expr.c_str(), b_expr.c_str(), c_expr.c_str(), d_expr.c_str());
log_assert(y.wire); log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
@ -472,7 +472,7 @@ struct SimplecWorker
return; return;
} }
if (cell->type.in("$_MUX_", "$_NMUX_")) if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{ {
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A)); SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B)); SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
@ -485,8 +485,8 @@ struct SimplecWorker
// casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933) // casts to bool are a workaround for CBMC bug (https://github.com/diffblue/cbmc/issues/933)
string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr.c_str(), string expr = stringf("%s ? %s(bool)%s : %s(bool)%s", s_expr.c_str(),
cell->type == "$_NMUX_" ? "!" : "", b_expr.c_str(), cell->type == ID($_NMUX_) ? "!" : "", b_expr.c_str(),
cell->type == "$_NMUX_" ? "!" : "", a_expr.c_str()); cell->type == ID($_NMUX_) ? "!" : "", a_expr.c_str());
log_assert(y.wire); log_assert(y.wire);
funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) + funct_declarations.push_back(util_set_bit(work->prefix + cid(y.wire->name), y.wire->width, y.offset, expr) +
@ -653,10 +653,10 @@ struct SimplecWorker
for (Wire *w : module->wires()) for (Wire *w : module->wires())
{ {
if (w->attributes.count("\\init")) if (w->attributes.count(ID::init))
{ {
SigSpec sig = sigmaps.at(module)(w); SigSpec sig = sigmaps.at(module)(w);
Const val = w->attributes.at("\\init"); Const val = w->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx); val.bits.resize(GetSize(sig), State::Sx);
for (int i = 0; i < GetSize(sig); i++) for (int i = 0; i < GetSize(sig); i++)

270
backends/smt2/smt2.cc
View file

@ -135,7 +135,7 @@ struct Smt2Worker
log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n", log_error("Unsupported or unknown directionality on port %s of cell %s.%s (%s).\n",
log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type)); log_id(conn.first), log_id(module), log_id(cell), log_id(cell->type));
if (cell->type.in("$mem") && conn.first.in("\\RD_CLK", "\\WR_CLK")) if (cell->type.in(ID($mem)) && conn.first.in(ID::RD_CLK, ID::WR_CLK))
{ {
SigSpec clk = sigmap(conn.second); SigSpec clk = sigmap(conn.second);
for (int i = 0; i < GetSize(clk); i++) for (int i = 0; i < GetSize(clk); i++)
@ -143,19 +143,19 @@ struct Smt2Worker
if (clk[i].wire == nullptr) if (clk[i].wire == nullptr)
continue; continue;
if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_ENABLE" : "\\WR_CLK_ENABLE")[i] != State::S1) if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_ENABLE : ID::WR_CLK_ENABLE)[i] != State::S1)
continue; continue;
if (cell->getParam(conn.first == "\\RD_CLK" ? "\\RD_CLK_POLARITY" : "\\WR_CLK_POLARITY")[i] == State::S1) if (cell->getParam(conn.first == ID::RD_CLK ? ID::RD_CLK_POLARITY : ID::WR_CLK_POLARITY)[i] == State::S1)
clock_posedge.insert(clk[i]); clock_posedge.insert(clk[i]);
else else
clock_negedge.insert(clk[i]); clock_negedge.insert(clk[i]);
} }
} }
else else
if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_") && conn.first.in("\\CLK", "\\C")) if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)) && conn.first.in(ID::CLK, ID::C))
{ {
bool posedge = (cell->type == "$_DFF_N_") || (cell->type == "$dff" && cell->getParam("\\CLK_POLARITY").as_bool()); bool posedge = (cell->type == ID($_DFF_N_)) || (cell->type == ID($dff) && cell->getParam(ID::CLK_POLARITY).as_bool());
for (auto bit : sigmap(conn.second)) { for (auto bit : sigmap(conn.second)) {
if (posedge) if (posedge)
clock_posedge.insert(bit); clock_posedge.insert(bit);
@ -373,8 +373,8 @@ struct Smt2Worker
for (char ch : expr) { for (char ch : expr) {
if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A)); if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B)); else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort("\\C")); else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C));
else if (ch == 'D') processed_expr += get_bool(cell->getPort("\\D")); else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S)); else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
else processed_expr += ch; else processed_expr += ch;
} }
@ -392,7 +392,7 @@ struct Smt2Worker
{ {
RTLIL::SigSpec sig_a, sig_b; RTLIL::SigSpec sig_a, sig_b;
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y)); RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int width = GetSize(sig_y); int width = GetSize(sig_y);
if (type == 's' || type == 'd' || type == 'b') { if (type == 's' || type == 'd' || type == 'b') {
@ -480,7 +480,7 @@ struct Smt2Worker
exported_cells.insert(cell); exported_cells.insert(cell);
recursive_cells.insert(cell); recursive_cells.insert(cell);
if (cell->type == "$initstate") if (cell->type == ID($initstate))
{ {
SigBit bit = sigmap(cell->getPort(ID::Y).as_bit()); SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n", decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
@ -490,80 +490,80 @@ struct Smt2Worker
return; return;
} }
if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_")) if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{ {
registers.insert(cell); registers.insert(cell);
makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort("\\Q"))); makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q)));
register_bool(cell->getPort("\\Q"), idcounter++); register_bool(cell->getPort(ID::Q), idcounter++);
recursive_cells.erase(cell); recursive_cells.erase(cell);
return; return;
} }
if (cell->type == "$_BUF_") return export_gate(cell, "A"); if (cell->type == ID($_BUF_)) return export_gate(cell, "A");
if (cell->type == "$_NOT_") return export_gate(cell, "(not A)"); if (cell->type == ID($_NOT_)) return export_gate(cell, "(not A)");
if (cell->type == "$_AND_") return export_gate(cell, "(and A B)"); if (cell->type == ID($_AND_)) return export_gate(cell, "(and A B)");
if (cell->type == "$_NAND_") return export_gate(cell, "(not (and A B))"); if (cell->type == ID($_NAND_)) return export_gate(cell, "(not (and A B))");
if (cell->type == "$_OR_") return export_gate(cell, "(or A B)"); if (cell->type == ID($_OR_)) return export_gate(cell, "(or A B)");
if (cell->type == "$_NOR_") return export_gate(cell, "(not (or A B))"); if (cell->type == ID($_NOR_)) return export_gate(cell, "(not (or A B))");
if (cell->type == "$_XOR_") return export_gate(cell, "(xor A B)"); if (cell->type == ID($_XOR_)) return export_gate(cell, "(xor A B)");
if (cell->type == "$_XNOR_") return export_gate(cell, "(not (xor A B))"); if (cell->type == ID($_XNOR_)) return export_gate(cell, "(not (xor A B))");
if (cell->type == "$_ANDNOT_") return export_gate(cell, "(and A (not B))"); if (cell->type == ID($_ANDNOT_)) return export_gate(cell, "(and A (not B))");
if (cell->type == "$_ORNOT_") return export_gate(cell, "(or A (not B))"); if (cell->type == ID($_ORNOT_)) return export_gate(cell, "(or A (not B))");
if (cell->type == "$_MUX_") return export_gate(cell, "(ite S B A)"); if (cell->type == ID($_MUX_)) return export_gate(cell, "(ite S B A)");
if (cell->type == "$_NMUX_") return export_gate(cell, "(not (ite S B A))"); if (cell->type == ID($_NMUX_)) return export_gate(cell, "(not (ite S B A))");
if (cell->type == "$_AOI3_") return export_gate(cell, "(not (or (and A B) C))"); if (cell->type == ID($_AOI3_)) return export_gate(cell, "(not (or (and A B) C))");
if (cell->type == "$_OAI3_") return export_gate(cell, "(not (and (or A B) C))"); if (cell->type == ID($_OAI3_)) return export_gate(cell, "(not (and (or A B) C))");
if (cell->type == "$_AOI4_") return export_gate(cell, "(not (or (and A B) (and C D)))"); if (cell->type == ID($_AOI4_)) return export_gate(cell, "(not (or (and A B) (and C D)))");
if (cell->type == "$_OAI4_") return export_gate(cell, "(not (and (or A B) (or C D)))"); if (cell->type == ID($_OAI4_)) return export_gate(cell, "(not (and (or A B) (or C D)))");
// FIXME: $lut // FIXME: $lut
if (bvmode) if (bvmode)
{ {
if (cell->type.in("$ff", "$dff")) if (cell->type.in(ID($ff), ID($dff)))
{ {
registers.insert(cell); registers.insert(cell);
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q"))); makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)));
register_bv(cell->getPort("\\Q"), idcounter++); register_bv(cell->getPort(ID::Q), idcounter++);
recursive_cells.erase(cell); recursive_cells.erase(cell);
return; return;
} }
if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq)))
{ {
registers.insert(cell); registers.insert(cell);
string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell); string infostr = cell->attributes.count(ID::src) ? cell->attributes.at(ID::src).decode_string().c_str() : get_id(cell);
if (cell->attributes.count("\\reg")) if (cell->attributes.count(ID::reg))
infostr += " " + cell->attributes.at("\\reg").decode_string(); infostr += " " + cell->attributes.at(ID::reg).decode_string();
decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str())); decls.push_back(stringf("; yosys-smt2-%s %s#%d %d %s\n", cell->type.c_str() + 1, get_id(module), idcounter, GetSize(cell->getPort(ID::Y)), infostr.c_str()));
if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\maximize")){ if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::maximize)){
decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter)); decls.push_back(stringf("; yosys-smt2-maximize %s#%d\n", get_id(module), idcounter));
log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); log("Wire %s is maximized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
} }
else if (cell->getPort("\\Y").is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute("\\minimize")){ else if (cell->getPort(ID::Y).is_wire() && cell->getPort(ID::Y).as_wire()->get_bool_attribute(ID::minimize)){
decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter)); decls.push_back(stringf("; yosys-smt2-minimize %s#%d\n", get_id(module), idcounter));
log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str()); log("Wire %s is minimized\n", cell->getPort(ID::Y).as_wire()->name.str().c_str());
} }
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y))); makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::Y)));
if (cell->type == "$anyseq") if (cell->type == ID($anyseq))
ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter)); ex_input_eq.push_back(stringf(" (= (|%s#%d| state) (|%s#%d| other_state))", get_id(module), idcounter, get_id(module), idcounter));
register_bv(cell->getPort(ID::Y), idcounter++); register_bv(cell->getPort(ID::Y), idcounter++);
recursive_cells.erase(cell); recursive_cells.erase(cell);
return; return;
} }
if (cell->type == "$and") return export_bvop(cell, "(bvand A B)"); if (cell->type == ID($and)) return export_bvop(cell, "(bvand A B)");
if (cell->type == "$or") return export_bvop(cell, "(bvor A B)"); if (cell->type == ID($or)) return export_bvop(cell, "(bvor A B)");
if (cell->type == "$xor") return export_bvop(cell, "(bvxor A B)"); if (cell->type == ID($xor)) return export_bvop(cell, "(bvxor A B)");
if (cell->type == "$xnor") return export_bvop(cell, "(bvxnor A B)"); if (cell->type == ID($xnor)) return export_bvop(cell, "(bvxnor A B)");
if (cell->type == "$shl") return export_bvop(cell, "(bvshl A B)", 's'); if (cell->type == ID($shl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == "$shr") return export_bvop(cell, "(bvlshr A B)", 's'); if (cell->type == ID($shr)) return export_bvop(cell, "(bvlshr A B)", 's');
if (cell->type == "$sshl") return export_bvop(cell, "(bvshl A B)", 's'); if (cell->type == ID($sshl)) return export_bvop(cell, "(bvshl A B)", 's');
if (cell->type == "$sshr") return export_bvop(cell, "(bvLshr A B)", 's'); if (cell->type == ID($sshr)) return export_bvop(cell, "(bvLshr A B)", 's');
if (cell->type.in("$shift", "$shiftx")) { if (cell->type.in(ID($shift), ID($shiftx))) {
if (cell->getParam("\\B_SIGNED").as_bool()) { if (cell->getParam(ID::B_SIGNED).as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) " return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvlshr A (bvneg B)))", "(bvlshr A B) (bvlshr A (bvneg B)))",
GetSize(cell->getPort(ID::B)), 0), 's'); GetSize(cell->getPort(ID::B)), 0), 's');
@ -572,44 +572,44 @@ struct Smt2Worker
} }
} }
if (cell->type == "$lt") return export_bvop(cell, "(bvUlt A B)", 'b'); if (cell->type == ID($lt)) return export_bvop(cell, "(bvUlt A B)", 'b');
if (cell->type == "$le") return export_bvop(cell, "(bvUle A B)", 'b'); if (cell->type == ID($le)) return export_bvop(cell, "(bvUle A B)", 'b');
if (cell->type == "$ge") return export_bvop(cell, "(bvUge A B)", 'b'); if (cell->type == ID($ge)) return export_bvop(cell, "(bvUge A B)", 'b');
if (cell->type == "$gt") return export_bvop(cell, "(bvUgt A B)", 'b'); if (cell->type == ID($gt)) return export_bvop(cell, "(bvUgt A B)", 'b');
if (cell->type == "$ne") return export_bvop(cell, "(distinct A B)", 'b'); if (cell->type == ID($ne)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == "$nex") return export_bvop(cell, "(distinct A B)", 'b'); if (cell->type == ID($nex)) return export_bvop(cell, "(distinct A B)", 'b');
if (cell->type == "$eq") return export_bvop(cell, "(= A B)", 'b'); if (cell->type == ID($eq)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == "$eqx") return export_bvop(cell, "(= A B)", 'b'); if (cell->type == ID($eqx)) return export_bvop(cell, "(= A B)", 'b');
if (cell->type == "$not") return export_bvop(cell, "(bvnot A)"); if (cell->type == ID($not)) return export_bvop(cell, "(bvnot A)");
if (cell->type == "$pos") return export_bvop(cell, "A"); if (cell->type == ID($pos)) return export_bvop(cell, "A");
if (cell->type == "$neg") return export_bvop(cell, "(bvneg A)"); if (cell->type == ID($neg)) return export_bvop(cell, "(bvneg A)");
if (cell->type == "$add") return export_bvop(cell, "(bvadd A B)"); if (cell->type == ID($add)) return export_bvop(cell, "(bvadd A B)");
if (cell->type == "$sub") return export_bvop(cell, "(bvsub A B)"); if (cell->type == ID($sub)) return export_bvop(cell, "(bvsub A B)");
if (cell->type == "$mul") return export_bvop(cell, "(bvmul A B)"); if (cell->type == ID($mul)) return export_bvop(cell, "(bvmul A B)");
if (cell->type == "$div") return export_bvop(cell, "(bvUdiv A B)", 'd'); if (cell->type == ID($div)) return export_bvop(cell, "(bvUdiv A B)", 'd');
if (cell->type == "$mod") return export_bvop(cell, "(bvUrem A B)", 'd'); if (cell->type == ID($mod)) return export_bvop(cell, "(bvUrem A B)", 'd');
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool") && if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) { 2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
bool is_and = cell->type == "$reduce_and"; bool is_and = cell->type == ID($reduce_and);
string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0'); string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b'); return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits.c_str()), 'b');
} }
if (cell->type == "$reduce_and") return export_reduce(cell, "(and A)", true); if (cell->type == ID($reduce_and)) return export_reduce(cell, "(and A)", true);
if (cell->type == "$reduce_or") return export_reduce(cell, "(or A)", false); if (cell->type == ID($reduce_or)) return export_reduce(cell, "(or A)", false);
if (cell->type == "$reduce_xor") return export_reduce(cell, "(xor A)", false); if (cell->type == ID($reduce_xor)) return export_reduce(cell, "(xor A)", false);
if (cell->type == "$reduce_xnor") return export_reduce(cell, "(not (xor A))", false); if (cell->type == ID($reduce_xnor)) return export_reduce(cell, "(not (xor A))", false);
if (cell->type == "$reduce_bool") return export_reduce(cell, "(or A)", false); if (cell->type == ID($reduce_bool)) return export_reduce(cell, "(or A)", false);
if (cell->type == "$logic_not") return export_reduce(cell, "(not (or A))", false); if (cell->type == ID($logic_not)) return export_reduce(cell, "(not (or A))", false);
if (cell->type == "$logic_and") return export_reduce(cell, "(and (or A) (or B))", false); if (cell->type == ID($logic_and)) return export_reduce(cell, "(and (or A) (or B))", false);
if (cell->type == "$logic_or") return export_reduce(cell, "(or A B)", false); if (cell->type == ID($logic_or)) return export_reduce(cell, "(or A B)", false);
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
std::string processed_expr = get_bv(cell->getPort(ID::A)); std::string processed_expr = get_bv(cell->getPort(ID::A));
@ -637,19 +637,19 @@ struct Smt2Worker
// FIXME: $slice $concat // FIXME: $slice $concat
} }
if (memmode && cell->type == "$mem") if (memmode && cell->type == ID($mem))
{ {
int arrayid = idcounter++; int arrayid = idcounter++;
memarrays[cell] = arrayid; memarrays[cell] = arrayid;
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int rd_ports = cell->getParam("\\RD_PORTS").as_int(); int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
int wr_ports = cell->getParam("\\WR_PORTS").as_int(); int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
bool async_read = false; bool async_read = false;
if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) { if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_zero()) if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero())
log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module)); log_error("Memory %s.%s has mixed clocked/nonclocked write ports. This is not supported by \"write_smt2\".\n", log_id(cell), log_id(module));
async_read = true; async_read = true;
} }
@ -665,8 +665,8 @@ struct Smt2Worker
if (statebv) if (statebv)
{ {
int mem_size = cell->getParam("\\SIZE").as_int(); int mem_size = cell->getParam(ID::SIZE).as_int();
int mem_offset = cell->getParam("\\OFFSET").as_int(); int mem_offset = cell->getParam(ID::OFFSET).as_int();
makebits(memstate, width*mem_size, get_id(cell)); makebits(memstate, width*mem_size, get_id(cell));
decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n", decls.push_back(stringf("(define-fun |%s_m %s| ((state |%s_s|)) (_ BitVec %d) (|%s| state))\n",
@ -674,11 +674,11 @@ struct Smt2Worker
for (int i = 0; i < rd_ports; i++) for (int i = 0; i < rd_ports; i++)
{ {
SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits); SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width); SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
std::string addr = get_bv(addr_sig); std::string addr = get_bv(addr_sig);
if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! " log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module)); "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
@ -717,11 +717,11 @@ struct Smt2Worker
for (int i = 0; i < rd_ports; i++) for (int i = 0; i < rd_ports; i++)
{ {
SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(abits*i, abits); SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(abits*i, abits);
SigSpec data_sig = cell->getPort("\\RD_DATA").extract(width*i, width); SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(width*i, width);
std::string addr = get_bv(addr_sig); std::string addr = get_bv(addr_sig);
if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! " log_error("Read port %d (%s) of memory %s.%s is clocked. This is not supported by \"write_smt2\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module)); "Call \"memory\" with -nordff to avoid this error.\n", i, log_signal(data_sig), log_id(cell), log_id(module));
@ -801,9 +801,9 @@ struct Smt2Worker
pool<SigBit> reg_bits; pool<SigBit> reg_bits;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type.in("$ff", "$dff", "$_FF_", "$_DFF_P_", "$_DFF_N_")) { if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_))) {
// not using sigmap -- we want the net directly at the dff output // not using sigmap -- we want the net directly at the dff output
for (auto bit : cell->getPort("\\Q")) for (auto bit : cell->getPort(ID::Q))
reg_bits.insert(bit); reg_bits.insert(bit);
} }
@ -812,7 +812,7 @@ struct Smt2Worker
for (auto bit : SigSpec(wire)) for (auto bit : SigSpec(wire))
if (reg_bits.count(bit)) if (reg_bits.count(bit))
is_register = true; is_register = true;
if (wire->port_id || is_register || wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) { if (wire->port_id || is_register || wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\')) {
RTLIL::SigSpec sig = sigmap(wire); RTLIL::SigSpec sig = sigmap(wire);
if (wire->port_input) if (wire->port_input)
decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width)); decls.push_back(stringf("; yosys-smt2-input %s %d\n", get_id(wire), wire->width));
@ -820,7 +820,7 @@ struct Smt2Worker
decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width)); decls.push_back(stringf("; yosys-smt2-output %s %d\n", get_id(wire), wire->width));
if (is_register) if (is_register)
decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width)); decls.push_back(stringf("; yosys-smt2-register %s %d\n", get_id(wire), wire->width));
if (wire->get_bool_attribute("\\keep") || (wiresmode && wire->name[0] == '\\')) if (wire->get_bool_attribute(ID::keep) || (wiresmode && wire->name[0] == '\\'))
decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width)); decls.push_back(stringf("; yosys-smt2-wire %s %d\n", get_id(wire), wire->width));
if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig))) if (GetSize(wire) == 1 && (clock_posedge.count(sig) || clock_negedge.count(sig)))
decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire), decls.push_back(stringf("; yosys-smt2-clock %s%s%s\n", get_id(wire),
@ -854,9 +854,9 @@ struct Smt2Worker
vector<string> init_list; vector<string> init_list;
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
RTLIL::SigSpec sig = sigmap(wire); RTLIL::SigSpec sig = sigmap(wire);
Const val = wire->attributes.at("\\init"); Const val = wire->attributes.at(ID::init);
val.bits.resize(GetSize(sig), State::Sx); val.bits.resize(GetSize(sig), State::Sx);
if (bvmode && GetSize(sig) > 1) { if (bvmode && GetSize(sig) > 1) {
Const mask(State::S1, GetSize(sig)); Const mask(State::S1, GetSize(sig));
@ -885,31 +885,31 @@ struct Smt2Worker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type.in("$assert", "$assume", "$cover")) if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{ {
int &id = cell->type == "$assert" ? assert_id : int &id = cell->type == ID($assert) ? assert_id :
cell->type == "$assume" ? assume_id : cell->type == ID($assume) ? assume_id :
cell->type == "$cover" ? cover_id : *(int*)nullptr; cell->type == ID($cover) ? cover_id : *(int*)nullptr;
char postfix = cell->type == "$assert" ? 'a' : char postfix = cell->type == ID($assert) ? 'a' :
cell->type == "$assume" ? 'u' : cell->type == ID($assume) ? 'u' :
cell->type == "$cover" ? 'c' : 0; cell->type == ID($cover) ? 'c' : 0;
string name_a = get_bool(cell->getPort(ID::A)); string name_a = get_bool(cell->getPort(ID::A));
string name_en = get_bool(cell->getPort("\\EN")); string name_en = get_bool(cell->getPort(ID::EN));
string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell); string infostr = (cell->name[0] == '$' && cell->attributes.count(ID::src)) ? cell->attributes.at(ID::src).decode_string() : get_id(cell);
decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str())); decls.push_back(stringf("; yosys-smt2-%s %d %s\n", cell->type.c_str() + 1, id, infostr.c_str()));
if (cell->type == "$cover") if (cell->type == ID($cover))
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n", decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (and %s %s)) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell))); get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
else else
decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n", decls.push_back(stringf("(define-fun |%s_%c %d| ((state |%s_s|)) Bool (or %s (not %s))) ; %s\n",
get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell))); get_id(module), postfix, id, get_id(module), name_a.c_str(), name_en.c_str(), get_id(cell)));
if (cell->type == "$assert") if (cell->type == ID($assert))
assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id)); assert_list.push_back(stringf("(|%s_a %d| state)", get_id(module), id));
else if (cell->type == "$assume") else if (cell->type == ID($assume))
assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id)); assume_list.push_back(stringf("(|%s_u %d| state)", get_id(module), id));
id++; id++;
@ -965,44 +965,44 @@ struct Smt2Worker
for (auto cell : this_regs) for (auto cell : this_regs)
{ {
if (cell->type.in("$_FF_", "$_DFF_P_", "$_DFF_N_")) if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{ {
std::string expr_d = get_bool(cell->getPort("\\D")); std::string expr_d = get_bool(cell->getPort(ID::D));
std::string expr_q = get_bool(cell->getPort("\\Q"), "next_state"); std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q")))); trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort("\\Q")).c_str(), get_bool(cell->getPort("\\Q"), "other_state").c_str())); ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)).c_str(), get_bool(cell->getPort(ID::Q), "other_state").c_str()));
} }
if (cell->type.in("$ff", "$dff")) if (cell->type.in(ID($ff), ID($dff)))
{ {
std::string expr_d = get_bv(cell->getPort("\\D")); std::string expr_d = get_bv(cell->getPort(ID::D));
std::string expr_q = get_bv(cell->getPort("\\Q"), "next_state"); std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort("\\Q")))); trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort("\\Q")).c_str(), get_bv(cell->getPort("\\Q"), "other_state").c_str())); ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)).c_str(), get_bv(cell->getPort(ID::Q), "other_state").c_str()));
} }
if (cell->type.in("$anyconst", "$allconst")) if (cell->type.in(ID($anyconst), ID($allconst)))
{ {
std::string expr_d = get_bv(cell->getPort(ID::Y)); std::string expr_d = get_bv(cell->getPort(ID::Y));
std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state"); std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y)))); trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d.c_str(), expr_q.c_str(), get_id(cell), log_signal(cell->getPort(ID::Y))));
if (cell->type == "$anyconst") if (cell->type == ID($anyconst))
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str())); ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)).c_str(), get_bv(cell->getPort(ID::Y), "other_state").c_str()));
} }
if (cell->type == "$mem") if (cell->type == ID($mem))
{ {
int arrayid = memarrays.at(cell); int arrayid = memarrays.at(cell);
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int wr_ports = cell->getParam("\\WR_PORTS").as_int(); int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
bool async_read = false; bool async_read = false;
string initial_memstate, final_memstate; string initial_memstate, final_memstate;
if (!cell->getParam("\\WR_CLK_ENABLE").is_fully_ones()) { if (!cell->getParam(ID::WR_CLK_ENABLE).is_fully_ones()) {
log_assert(cell->getParam("\\WR_CLK_ENABLE").is_fully_zero()); log_assert(cell->getParam(ID::WR_CLK_ENABLE).is_fully_zero());
async_read = true; async_read = true;
initial_memstate = stringf("%s#%d#0", get_id(module), arrayid); initial_memstate = stringf("%s#%d#0", get_id(module), arrayid);
final_memstate = stringf("%s#%d#final", get_id(module), arrayid); final_memstate = stringf("%s#%d#final", get_id(module), arrayid);
@ -1010,8 +1010,8 @@ struct Smt2Worker
if (statebv) if (statebv)
{ {
int mem_size = cell->getParam("\\SIZE").as_int(); int mem_size = cell->getParam(ID::SIZE).as_int();
int mem_offset = cell->getParam("\\OFFSET").as_int(); int mem_offset = cell->getParam(ID::OFFSET).as_int();
if (async_read) { if (async_read) {
makebits(final_memstate, width*mem_size, get_id(cell)); makebits(final_memstate, width*mem_size, get_id(cell));
@ -1019,9 +1019,9 @@ struct Smt2Worker
for (int i = 0; i < wr_ports; i++) for (int i = 0; i < wr_ports; i++)
{ {
SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits); SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width); SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width); SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
std::string addr = get_bv(addr_sig); std::string addr = get_bv(addr_sig);
std::string data = get_bv(data_sig); std::string data = get_bv(data_sig);
@ -1066,9 +1066,9 @@ struct Smt2Worker
for (int i = 0; i < wr_ports; i++) for (int i = 0; i < wr_ports; i++)
{ {
SigSpec addr_sig = cell->getPort("\\WR_ADDR").extract(abits*i, abits); SigSpec addr_sig = cell->getPort(ID::WR_ADDR).extract(abits*i, abits);
SigSpec data_sig = cell->getPort("\\WR_DATA").extract(width*i, width); SigSpec data_sig = cell->getPort(ID::WR_DATA).extract(width*i, width);
SigSpec mask_sig = cell->getPort("\\WR_EN").extract(width*i, width); SigSpec mask_sig = cell->getPort(ID::WR_EN).extract(width*i, width);
std::string addr = get_bv(addr_sig); std::string addr = get_bv(addr_sig);
std::string data = get_bv(data_sig); std::string data = get_bv(data_sig);
@ -1104,8 +1104,8 @@ struct Smt2Worker
if (async_read) if (async_read)
hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell))); hier.push_back(stringf(" (= %s (|%s| state)) ; %s\n", expr_d.c_str(), final_memstate.c_str(), get_id(cell)));
Const init_data = cell->getParam("\\INIT"); Const init_data = cell->getParam(ID::INIT);
int memsize = cell->getParam("\\SIZE").as_int(); int memsize = cell->getParam(ID::SIZE).as_int();
for (int i = 0; i < memsize; i++) for (int i = 0; i < memsize; i++)
{ {
@ -1540,7 +1540,7 @@ struct Smt2Backend : public Backend {
for (auto module : sorted_modules) for (auto module : sorted_modules)
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type.in("$allconst", "$allseq")) if (cell->type.in(ID($allconst), ID($allseq)))
goto found_forall; goto found_forall;
if (0) { if (0) {
found_forall: found_forall:

144
backends/smv/smv.cc
View file

@ -219,25 +219,25 @@ struct SmvWorker
if (wire->port_input) if (wire->port_input)
inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire))); inputvars.push_back(stringf("%s : unsigned word[%d]; -- %s", cid(wire->name), wire->width, log_id(wire)));
if (wire->attributes.count("\\init")) if (wire->attributes.count(ID::init))
assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at("\\init")))); assignments.push_back(stringf("init(%s) := %s;", lvalue(wire), rvalue(wire->attributes.at(ID::init))));
} }
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
// FIXME: $slice, $concat, $mem // FIXME: $slice, $concat, $mem
if (cell->type.in("$assert")) if (cell->type.in(ID($assert)))
{ {
SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_en = cell->getPort("\\EN"); SigSpec sig_en = cell->getPort(ID::EN);
invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a))); invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
continue; continue;
} }
if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx")) if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{ {
SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B); SigSpec sig_b = cell->getPort(ID::B);
@ -254,12 +254,12 @@ struct SmvWorker
break; break;
} }
bool signed_a = cell->getParam("\\A_SIGNED").as_bool(); bool signed_a = cell->getParam(ID::A_SIGNED).as_bool();
bool signed_b = cell->getParam("\\B_SIGNED").as_bool(); bool signed_b = cell->getParam(ID::B_SIGNED).as_bool();
string op = cell->type.in("$shl", "$sshl") ? "<<" : ">>"; string op = cell->type.in(ID($shl), ID($sshl)) ? "<<" : ">>";
string expr, expr_a; string expr, expr_a;
if (cell->type == "$sshr" && signed_a) if (cell->type == ID($sshr) && signed_a)
{ {
expr_a = rvalue_s(sig_a, width); expr_a = rvalue_s(sig_a, width);
expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a.c_str(), op.c_str(), rvalue(sig_b.extract(0, shift_b_width)), width_y); expr = stringf("resize(unsigned(%s %s %s), %d)", expr_a.c_str(), op.c_str(), rvalue(sig_b.extract(0, shift_b_width)), width_y);
@ -268,7 +268,7 @@ struct SmvWorker
rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width, rvalue(sig_b.extract(shift_b_width, GetSize(sig_b) - shift_b_width)), GetSize(sig_b) - shift_b_width,
rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str()); rvalue(sig_a[GetSize(sig_a)-1]), width_y, width_y, expr.c_str());
} }
else if (cell->type.in("$shift", "$shiftx") && signed_b) else if (cell->type.in(ID($shift), ID($shiftx)) && signed_b)
{ {
expr_a = rvalue_u(sig_a, width); expr_a = rvalue_u(sig_a, width);
@ -292,7 +292,7 @@ struct SmvWorker
} }
else else
{ {
if (cell->type.in("$shift", "$shiftx") || !signed_a) if (cell->type.in(ID($shift), ID($shiftx)) || !signed_a)
expr_a = rvalue_u(sig_a, width); expr_a = rvalue_u(sig_a, width);
else else
expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width); expr_a = stringf("resize(unsigned(%s), %d)", rvalue_s(sig_a, width_ay), width);
@ -308,16 +308,16 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$not", "$pos", "$neg")) if (cell->type.in(ID($not), ID($pos), ID($neg)))
{ {
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
string expr_a, op; string expr_a, op;
if (cell->type == "$not") op = "!"; if (cell->type == ID($not)) op = "!";
if (cell->type == "$pos") op = ""; if (cell->type == ID($pos)) op = "";
if (cell->type == "$neg") op = "-"; if (cell->type == ID($neg)) op = "-";
if (cell->getParam("\\A_SIGNED").as_bool()) if (cell->getParam(ID::A_SIGNED).as_bool())
{ {
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_s(cell->getPort(ID::A), width))); op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
@ -331,20 +331,20 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor")) if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
{ {
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
string expr_a, expr_b, op; string expr_a, expr_b, op;
if (cell->type == "$add") op = "+"; if (cell->type == ID($add)) op = "+";
if (cell->type == "$sub") op = "-"; if (cell->type == ID($sub)) op = "-";
if (cell->type == "$mul") op = "*"; if (cell->type == ID($mul)) op = "*";
if (cell->type == "$and") op = "&"; if (cell->type == ID($and)) op = "&";
if (cell->type == "$or") op = "|"; if (cell->type == ID($or)) op = "|";
if (cell->type == "$xor") op = "xor"; if (cell->type == ID($xor)) op = "xor";
if (cell->type == "$xnor") op = "xnor"; if (cell->type == ID($xnor)) op = "xnor";
if (cell->getParam("\\A_SIGNED").as_bool()) if (cell->getParam(ID::A_SIGNED).as_bool())
{ {
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width))); rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width)));
@ -358,17 +358,17 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$div", "$mod")) if (cell->type.in(ID($div), ID($mod)))
{ {
int width_y = GetSize(cell->getPort(ID::Y)); int width_y = GetSize(cell->getPort(ID::Y));
int width = max(width_y, GetSize(cell->getPort(ID::A))); int width = max(width_y, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(ID::B))); width = max(width, GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op; string expr_a, expr_b, op;
if (cell->type == "$div") op = "/"; if (cell->type == ID($div)) op = "/";
if (cell->type == "$mod") op = "mod"; if (cell->type == ID($mod)) op = "mod";
if (cell->getParam("\\A_SIGNED").as_bool()) if (cell->getParam(ID::A_SIGNED).as_bool())
{ {
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y)); rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y));
@ -382,21 +382,21 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$eq", "$ne", "$eqx", "$nex", "$lt", "$le", "$ge", "$gt")) if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
{ {
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B))); int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
string expr_a, expr_b, op; string expr_a, expr_b, op;
if (cell->type == "$eq") op = "="; if (cell->type == ID($eq)) op = "=";
if (cell->type == "$ne") op = "!="; if (cell->type == ID($ne)) op = "!=";
if (cell->type == "$eqx") op = "="; if (cell->type == ID($eqx)) op = "=";
if (cell->type == "$nex") op = "!="; if (cell->type == ID($nex)) op = "!=";
if (cell->type == "$lt") op = "<"; if (cell->type == ID($lt)) op = "<";
if (cell->type == "$le") op = "<="; if (cell->type == ID($le)) op = "<=";
if (cell->type == "$ge") op = ">="; if (cell->type == ID($ge)) op = ">=";
if (cell->type == "$gt") op = ">"; if (cell->type == ID($gt)) op = ">";
if (cell->getParam("\\A_SIGNED").as_bool()) if (cell->getParam(ID::A_SIGNED).as_bool())
{ {
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width); expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width); expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width);
@ -413,7 +413,7 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool")) if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
{ {
int width_a = GetSize(cell->getPort(ID::A)); int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y)); int width_y = GetSize(cell->getPort(ID::Y));
@ -421,15 +421,15 @@ struct SmvWorker
const char *expr_y = lvalue(cell->getPort(ID::Y)); const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr; string expr;
if (cell->type == "$reduce_and") expr = stringf("%s = !0ub%d_0", expr_a, width_a); if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
if (cell->type == "$reduce_or") expr = stringf("%s != 0ub%d_0", expr_a, width_a); if (cell->type == ID($reduce_or)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
if (cell->type == "$reduce_bool") expr = stringf("%s != 0ub%d_0", expr_a, width_a); if (cell->type == ID($reduce_bool)) expr = stringf("%s != 0ub%d_0", expr_a, width_a);
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
continue; continue;
} }
if (cell->type.in("$reduce_xor", "$reduce_xnor")) if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
{ {
int width_y = GetSize(cell->getPort(ID::Y)); int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_y = lvalue(cell->getPort(ID::Y)); const char *expr_y = lvalue(cell->getPort(ID::Y));
@ -441,14 +441,14 @@ struct SmvWorker
expr += rvalue(bit); expr += rvalue(bit);
} }
if (cell->type == "$reduce_xnor") if (cell->type == ID($reduce_xnor))
expr = "!(" + expr + ")"; expr = "!(" + expr + ")";
definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y)); definitions.push_back(stringf("%s := resize(%s, %d);", expr_y, expr.c_str(), width_y));
continue; continue;
} }
if (cell->type.in("$logic_and", "$logic_or")) if (cell->type.in(ID($logic_and), ID($logic_or)))
{ {
int width_a = GetSize(cell->getPort(ID::A)); int width_a = GetSize(cell->getPort(ID::A));
int width_b = GetSize(cell->getPort(ID::B)); int width_b = GetSize(cell->getPort(ID::B));
@ -459,14 +459,14 @@ struct SmvWorker
const char *expr_y = lvalue(cell->getPort(ID::Y)); const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr; string expr;
if (cell->type == "$logic_and") expr = expr_a + " & " + expr_b; if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
if (cell->type == "$logic_or") expr = expr_a + " | " + expr_b; if (cell->type == ID($logic_or)) expr = expr_a + " | " + expr_b;
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y)); definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr.c_str(), width_y));
continue; continue;
} }
if (cell->type.in("$logic_not")) if (cell->type.in(ID($logic_not)))
{ {
int width_a = GetSize(cell->getPort(ID::A)); int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y)); int width_y = GetSize(cell->getPort(ID::Y));
@ -478,7 +478,7 @@ struct SmvWorker
continue; continue;
} }
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_a = cell->getPort(ID::A);
@ -494,34 +494,34 @@ struct SmvWorker
continue; continue;
} }
if (cell->type == "$dff") if (cell->type == ID($dff))
{ {
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort("\\Q")), GetSize(cell->getPort("\\Q")), log_signal(cell->getPort("\\Q")))); vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort("\\Q")), rvalue(cell->getPort("\\D")))); assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D))));
continue; continue;
} }
if (cell->type.in("$_BUF_", "$_NOT_")) if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{ {
string op = cell->type == "$_NOT_" ? "!" : ""; string op = cell->type == ID($_NOT_) ? "!" : "";
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A)))); definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op.c_str(), rvalue(cell->getPort(ID::A))));
continue; continue;
} }
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{ {
string op; string op;
if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_")) op = "&"; if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_))) op = "&";
if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_")) op = "|"; if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_))) op = "|";
if (cell->type.in("$_XOR_")) op = "xor"; if (cell->type.in(ID($_XOR_))) op = "xor";
if (cell->type.in("$_XNOR_")) op = "xnor"; if (cell->type.in(ID($_XNOR_))) op = "xnor";
if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else else
if (cell->type.in("$_NAND_", "$_NOR_")) if (cell->type.in(ID($_NAND_), ID($_NOR_)))
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B)))); rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
else else
@ -530,45 +530,45 @@ struct SmvWorker
continue; continue;
} }
if (cell->type == "$_MUX_") if (cell->type == ID($_MUX_))
{ {
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue; continue;
} }
if (cell->type == "$_NMUX_") if (cell->type == ID($_NMUX_))
{ {
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A)))); rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
continue; continue;
} }
if (cell->type == "$_AOI3_") if (cell->type == ID($_AOI3_))
{ {
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")))); rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
continue; continue;
} }
if (cell->type == "$_OAI3_") if (cell->type == ID($_OAI3_))
{ {
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")))); rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
continue; continue;
} }
if (cell->type == "$_AOI4_") if (cell->type == ID($_AOI4_))
{ {
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
continue; continue;
} }
if (cell->type == "$_OAI4_") if (cell->type == ID($_OAI4_))
{ {
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)), definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort("\\C")), rvalue(cell->getPort("\\D")))); rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
continue; continue;
} }

424
backends/verilog/verilog_backend.cc
View file

@ -378,7 +378,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
if (attr2comment) if (attr2comment)
as_comment = true; as_comment = true;
for (auto it = attributes.begin(); it != attributes.end(); ++it) { for (auto it = attributes.begin(); it != attributes.end(); ++it) {
if (it->first == "\\init" && regattr) continue; if (it->first == ID::init && regattr) continue;
f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
f << stringf(" = "); f << stringf(" = ");
if (modattr && (it->second == State::S0 || it->second == Const(0))) if (modattr && (it->second == State::S0 || it->second == Const(0)))
@ -423,9 +423,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str()); f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (reg_wires.count(wire->name)) { if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str()); f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
f << stringf(" = "); f << stringf(" = ");
dump_const(f, wire->attributes.at("\\init")); dump_const(f, wire->attributes.at(ID::init));
} }
f << stringf(";\n"); f << stringf(";\n");
} else if (!wire->port_input && !wire->port_output) } else if (!wire->port_input && !wire->port_output)
@ -451,9 +451,9 @@ void dump_cell_expr_port(std::ostream &f, RTLIL::Cell *cell, std::string port, b
std::string cellname(RTLIL::Cell *cell) std::string cellname(RTLIL::Cell *cell)
{ {
if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort(ID::Q))
{ {
RTLIL::SigSpec sig = cell->getPort("\\Q"); RTLIL::SigSpec sig = cell->getPort(ID::Q);
if (GetSize(sig) != 1 || sig.is_fully_const()) if (GetSize(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name; goto no_special_reg_name;
@ -509,7 +509,7 @@ void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell
bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{ {
if (cell->type == "$_NOT_") { if (cell->type == ID($_NOT_)) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
@ -520,32 +520,32 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type.in("$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) { if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_")) if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
f << stringf("~("); f << stringf("~(");
dump_cell_expr_port(f, cell, "A", false); dump_cell_expr_port(f, cell, "A", false);
f << stringf(" "); f << stringf(" ");
if (cell->type.in("$_AND_", "$_NAND_", "$_ANDNOT_")) if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_ANDNOT_)))
f << stringf("&"); f << stringf("&");
if (cell->type.in("$_OR_", "$_NOR_", "$_ORNOT_")) if (cell->type.in(ID($_OR_), ID($_NOR_), ID($_ORNOT_)))
f << stringf("|"); f << stringf("|");
if (cell->type.in("$_XOR_", "$_XNOR_")) if (cell->type.in(ID($_XOR_), ID($_XNOR_)))
f << stringf("^"); f << stringf("^");
dump_attributes(f, "", cell->attributes, ' '); dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" "); f << stringf(" ");
if (cell->type.in("$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
f << stringf("~("); f << stringf("~(");
dump_cell_expr_port(f, cell, "B", false); dump_cell_expr_port(f, cell, "B", false);
if (cell->type.in("$_NAND_", "$_NOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_")) if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
f << stringf(")"); f << stringf(")");
f << stringf(";\n"); f << stringf(";\n");
return true; return true;
} }
if (cell->type == "$_MUX_") { if (cell->type == ID($_MUX_)) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
@ -559,7 +559,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$_NMUX_") { if (cell->type == ID($_NMUX_)) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = !("); f << stringf(" = !(");
@ -573,14 +573,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type.in("$_AOI3_", "$_OAI3_")) { if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~(("); f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false); dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == "$_AOI3_" ? " & " : " | "); f << stringf(cell->type == ID($_AOI3_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false); dump_cell_expr_port(f, cell, "B", false);
f << stringf(cell->type == "$_AOI3_" ? ") |" : ") &"); f << stringf(cell->type == ID($_AOI3_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, ' '); dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" "); f << stringf(" ");
dump_cell_expr_port(f, cell, "C", false); dump_cell_expr_port(f, cell, "C", false);
@ -588,18 +588,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type.in("$_AOI4_", "$_OAI4_")) { if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = ~(("); f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false); dump_cell_expr_port(f, cell, "A", false);
f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "B", false); dump_cell_expr_port(f, cell, "B", false);
f << stringf(cell->type == "$_AOI4_" ? ") |" : ") &"); f << stringf(cell->type == ID($_AOI4_) ? ") |" : ") &");
dump_attributes(f, "", cell->attributes, ' '); dump_attributes(f, "", cell->attributes, ' ');
f << stringf(" ("); f << stringf(" (");
dump_cell_expr_port(f, cell, "C", false); dump_cell_expr_port(f, cell, "C", false);
f << stringf(cell->type == "$_AOI4_" ? " & " : " | "); f << stringf(cell->type == ID($_AOI4_) ? " & " : " | ");
dump_cell_expr_port(f, cell, "D", false); dump_cell_expr_port(f, cell, "D", false);
f << stringf("));\n"); f << stringf("));\n");
return true; return true;
@ -608,26 +608,26 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.begins_with("$_DFF_")) if (cell->type.begins_with("$_DFF_"))
{ {
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str()); f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
dump_reg_init(f, cell->getPort("\\Q")); dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n"; f << ";\n";
} }
dump_attributes(f, indent, cell->attributes); dump_attributes(f, indent, cell->attributes);
f << stringf("%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg"); f << stringf("%s" "always @(%sedge ", indent.c_str(), cell->type[6] == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\C")); dump_sigspec(f, cell->getPort(ID::C));
if (cell->type[7] != '_') { if (cell->type[7] != '_') {
f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg"); f << stringf(" or %sedge ", cell->type[7] == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\R")); dump_sigspec(f, cell->getPort(ID::R));
} }
f << stringf(")\n"); f << stringf(")\n");
if (cell->type[7] != '_') { if (cell->type[7] != '_') {
f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!"); f << stringf("%s" " if (%s", indent.c_str(), cell->type[7] == 'P' ? "" : "!");
dump_sigspec(f, cell->getPort("\\R")); dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n"); f << stringf(")\n");
f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]); f << stringf("%s" " %s <= %c;\n", indent.c_str(), reg_name.c_str(), cell->type[8]);
f << stringf("%s" " else\n", indent.c_str()); f << stringf("%s" " else\n", indent.c_str());
@ -639,7 +639,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Q")); dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str()); f << stringf(" = %s;\n", reg_name.c_str());
} }
@ -651,25 +651,25 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10]; char pol_c = cell->type[8], pol_s = cell->type[9], pol_r = cell->type[10];
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str()); f << stringf("%s" "reg %s", indent.c_str(), reg_name.c_str());
dump_reg_init(f, cell->getPort("\\Q")); dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n"; f << ";\n";
} }
dump_attributes(f, indent, cell->attributes); dump_attributes(f, indent, cell->attributes);
f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg"); f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_c == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\C")); dump_sigspec(f, cell->getPort(ID::C));
f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg"); f << stringf(" or %sedge ", pol_s == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort(ID::S)); dump_sigspec(f, cell->getPort(ID::S));
f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg"); f << stringf(" or %sedge ", pol_r == 'P' ? "pos" : "neg");
dump_sigspec(f, cell->getPort("\\R")); dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n"); f << stringf(")\n");
f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!"); f << stringf("%s" " if (%s", indent.c_str(), pol_r == 'P' ? "" : "!");
dump_sigspec(f, cell->getPort("\\R")); dump_sigspec(f, cell->getPort(ID::R));
f << stringf(")\n"); f << stringf(")\n");
f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str()); f << stringf("%s" " %s <= 0;\n", indent.c_str(), reg_name.c_str());
@ -685,7 +685,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Q")); dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str()); f << stringf(" = %s;\n", reg_name.c_str());
} }
@ -697,55 +697,55 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
#define HANDLE_BINOP(_type, _operator) \ #define HANDLE_BINOP(_type, _operator) \
if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; } if (cell->type ==_type) { dump_cell_expr_binop(f, indent, cell, _operator); return true; }
HANDLE_UNIOP("$not", "~") HANDLE_UNIOP(ID($not), "~")
HANDLE_UNIOP("$pos", "+") HANDLE_UNIOP(ID($pos), "+")
HANDLE_UNIOP("$neg", "-") HANDLE_UNIOP(ID($neg), "-")
HANDLE_BINOP("$and", "&") HANDLE_BINOP(ID($and), "&")
HANDLE_BINOP("$or", "|") HANDLE_BINOP(ID($or), "|")
HANDLE_BINOP("$xor", "^") HANDLE_BINOP(ID($xor), "^")
HANDLE_BINOP("$xnor", "~^") HANDLE_BINOP(ID($xnor), "~^")
HANDLE_UNIOP("$reduce_and", "&") HANDLE_UNIOP(ID($reduce_and), "&")
HANDLE_UNIOP("$reduce_or", "|") HANDLE_UNIOP(ID($reduce_or), "|")
HANDLE_UNIOP("$reduce_xor", "^") HANDLE_UNIOP(ID($reduce_xor), "^")
HANDLE_UNIOP("$reduce_xnor", "~^") HANDLE_UNIOP(ID($reduce_xnor), "~^")
HANDLE_UNIOP("$reduce_bool", "|") HANDLE_UNIOP(ID($reduce_bool), "|")
HANDLE_BINOP("$shl", "<<") HANDLE_BINOP(ID($shl), "<<")
HANDLE_BINOP("$shr", ">>") HANDLE_BINOP(ID($shr), ">>")
HANDLE_BINOP("$sshl", "<<<") HANDLE_BINOP(ID($sshl), "<<<")
HANDLE_BINOP("$sshr", ">>>") HANDLE_BINOP(ID($sshr), ">>>")
HANDLE_BINOP("$lt", "<") HANDLE_BINOP(ID($lt), "<")
HANDLE_BINOP("$le", "<=") HANDLE_BINOP(ID($le), "<=")
HANDLE_BINOP("$eq", "==") HANDLE_BINOP(ID($eq), "==")
HANDLE_BINOP("$ne", "!=") HANDLE_BINOP(ID($ne), "!=")
HANDLE_BINOP("$eqx", "===") HANDLE_BINOP(ID($eqx), "===")
HANDLE_BINOP("$nex", "!==") HANDLE_BINOP(ID($nex), "!==")
HANDLE_BINOP("$ge", ">=") HANDLE_BINOP(ID($ge), ">=")
HANDLE_BINOP("$gt", ">") HANDLE_BINOP(ID($gt), ">")
HANDLE_BINOP("$add", "+") HANDLE_BINOP(ID($add), "+")
HANDLE_BINOP("$sub", "-") HANDLE_BINOP(ID($sub), "-")
HANDLE_BINOP("$mul", "*") HANDLE_BINOP(ID($mul), "*")
HANDLE_BINOP("$div", "/") HANDLE_BINOP(ID($div), "/")
HANDLE_BINOP("$mod", "%") HANDLE_BINOP(ID($mod), "%")
HANDLE_BINOP("$pow", "**") HANDLE_BINOP(ID($pow), "**")
HANDLE_UNIOP("$logic_not", "!") HANDLE_UNIOP(ID($logic_not), "!")
HANDLE_BINOP("$logic_and", "&&") HANDLE_BINOP(ID($logic_and), "&&")
HANDLE_BINOP("$logic_or", "||") HANDLE_BINOP(ID($logic_or), "||")
#undef HANDLE_UNIOP #undef HANDLE_UNIOP
#undef HANDLE_BINOP #undef HANDLE_BINOP
if (cell->type == "$shift") if (cell->type == ID($shift))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
if (cell->getParam("\\B_SIGNED").as_bool()) if (cell->getParam(ID::B_SIGNED).as_bool())
{ {
f << stringf("$signed("); f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B)); dump_sigspec(f, cell->getPort(ID::B));
@ -769,7 +769,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$shiftx") if (cell->type == ID($shiftx))
{ {
std::string temp_id = next_auto_id(); std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str()); f << stringf("%s" "wire [%d:0] %s = ", indent.c_str(), GetSize(cell->getPort(ID::A))-1, temp_id.c_str());
@ -779,17 +779,17 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = %s[", temp_id.c_str()); f << stringf(" = %s[", temp_id.c_str());
if (cell->getParam("\\B_SIGNED").as_bool()) if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf("$signed("); f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B)); dump_sigspec(f, cell->getPort(ID::B));
if (cell->getParam("\\B_SIGNED").as_bool()) if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf(")"); f << stringf(")");
f << stringf(" +: %d", cell->getParam("\\Y_WIDTH").as_int()); f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int());
f << stringf("];\n"); f << stringf("];\n");
return true; return true;
} }
if (cell->type == "$mux") if (cell->type == ID($mux))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
@ -804,9 +804,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$pmux") if (cell->type == ID($pmux))
{ {
int width = cell->parameters["\\WIDTH"].as_int(); int width = cell->parameters[ID::WIDTH].as_int();
int s_width = cell->getPort(ID::S).size(); int s_width = cell->getPort(ID::S).size();
std::string func_name = cellname(cell); std::string func_name = cellname(cell);
@ -850,29 +850,29 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$tribuf") if (cell->type == ID($tribuf))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
dump_sigspec(f, cell->getPort("\\EN")); dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(" ? "); f << stringf(" ? ");
dump_sigspec(f, cell->getPort(ID::A)); dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" : %d'bz;\n", cell->parameters.at("\\WIDTH").as_int()); f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int());
return true; return true;
} }
if (cell->type == "$slice") if (cell->type == ID($slice))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::A)); dump_sigspec(f, cell->getPort(ID::A));
f << stringf(" >> %d;\n", cell->parameters.at("\\OFFSET").as_int()); f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int());
return true; return true;
} }
if (cell->type == "$concat") if (cell->type == ID($concat))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
@ -884,12 +884,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$lut") if (cell->type == ID($lut))
{ {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort(ID::Y)); dump_sigspec(f, cell->getPort(ID::Y));
f << stringf(" = "); f << stringf(" = ");
dump_const(f, cell->parameters.at("\\LUT")); dump_const(f, cell->parameters.at(ID::LUT));
f << stringf(" >> "); f << stringf(" >> ");
dump_attributes(f, "", cell->attributes, ' '); dump_attributes(f, "", cell->attributes, ' ');
dump_sigspec(f, cell->getPort(ID::A)); dump_sigspec(f, cell->getPort(ID::A));
@ -897,18 +897,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$dffsr") if (cell->type == ID($dffsr))
{ {
SigSpec sig_clk = cell->getPort("\\CLK"); SigSpec sig_clk = cell->getPort(ID::CLK);
SigSpec sig_set = cell->getPort("\\SET"); SigSpec sig_set = cell->getPort(ID::SET);
SigSpec sig_clr = cell->getPort("\\CLR"); SigSpec sig_clr = cell->getPort(ID::CLR);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
int width = cell->parameters["\\WIDTH"].as_int(); int width = cell->parameters[ID::WIDTH].as_int();
bool pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); bool pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
bool pol_set = cell->parameters["\\SET_POLARITY"].as_bool(); bool pol_set = cell->parameters[ID::SET_POLARITY].as_bool();
bool pol_clr = cell->parameters["\\CLR_POLARITY"].as_bool(); bool pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool();
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(sig_q, reg_name); bool out_is_reg_wire = is_reg_wire(sig_q, reg_name);
@ -950,43 +950,43 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type.in("$dff", "$adff", "$dffe")) if (cell->type.in(ID($dff), ID($adff), ID($dffe)))
{ {
RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst; RTLIL::SigSpec sig_clk, sig_arst, sig_en, val_arst;
bool pol_clk, pol_arst = false, pol_en = false; bool pol_clk, pol_arst = false, pol_en = false;
sig_clk = cell->getPort("\\CLK"); sig_clk = cell->getPort(ID::CLK);
pol_clk = cell->parameters["\\CLK_POLARITY"].as_bool(); pol_clk = cell->parameters[ID::CLK_POLARITY].as_bool();
if (cell->type == "$adff") { if (cell->type == ID($adff)) {
sig_arst = cell->getPort("\\ARST"); sig_arst = cell->getPort(ID::ARST);
pol_arst = cell->parameters["\\ARST_POLARITY"].as_bool(); pol_arst = cell->parameters[ID::ARST_POLARITY].as_bool();
val_arst = RTLIL::SigSpec(cell->parameters["\\ARST_VALUE"]); val_arst = RTLIL::SigSpec(cell->parameters[ID::ARST_VALUE]);
} }
if (cell->type == "$dffe") { if (cell->type == ID($dffe)) {
sig_en = cell->getPort("\\EN"); sig_en = cell->getPort(ID::EN);
pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
} }
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
dump_reg_init(f, cell->getPort("\\Q")); dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n"; f << ";\n";
} }
f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg"); f << stringf("%s" "always @(%sedge ", indent.c_str(), pol_clk ? "pos" : "neg");
dump_sigspec(f, sig_clk); dump_sigspec(f, sig_clk);
if (cell->type == "$adff") { if (cell->type == ID($adff)) {
f << stringf(" or %sedge ", pol_arst ? "pos" : "neg"); f << stringf(" or %sedge ", pol_arst ? "pos" : "neg");
dump_sigspec(f, sig_arst); dump_sigspec(f, sig_arst);
} }
f << stringf(")\n"); f << stringf(")\n");
if (cell->type == "$adff") { if (cell->type == ID($adff)) {
f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!"); f << stringf("%s" " if (%s", indent.c_str(), pol_arst ? "" : "!");
dump_sigspec(f, sig_arst); dump_sigspec(f, sig_arst);
f << stringf(")\n"); f << stringf(")\n");
@ -996,7 +996,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" " else\n", indent.c_str()); f << stringf("%s" " else\n", indent.c_str());
} }
if (cell->type == "$dffe") { if (cell->type == ID($dffe)) {
f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!"); f << stringf("%s" " if (%s", indent.c_str(), pol_en ? "" : "!");
dump_sigspec(f, sig_en); dump_sigspec(f, sig_en);
f << stringf(")\n"); f << stringf(")\n");
@ -1008,27 +1008,27 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Q")); dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str()); f << stringf(" = %s;\n", reg_name.c_str());
} }
return true; return true;
} }
if (cell->type == "$dlatch") if (cell->type == ID($dlatch))
{ {
RTLIL::SigSpec sig_en; RTLIL::SigSpec sig_en;
bool pol_en = false; bool pol_en = false;
sig_en = cell->getPort("\\EN"); sig_en = cell->getPort(ID::EN);
pol_en = cell->parameters["\\EN_POLARITY"].as_bool(); pol_en = cell->parameters[ID::EN_POLARITY].as_bool();
std::string reg_name = cellname(cell); std::string reg_name = cellname(cell);
bool out_is_reg_wire = is_reg_wire(cell->getPort("\\Q"), reg_name); bool out_is_reg_wire = is_reg_wire(cell->getPort(ID::Q), reg_name);
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters["\\WIDTH"].as_int()-1, reg_name.c_str()); f << stringf("%s" "reg [%d:0] %s", indent.c_str(), cell->parameters[ID::WIDTH].as_int()-1, reg_name.c_str());
dump_reg_init(f, cell->getPort("\\Q")); dump_reg_init(f, cell->getPort(ID::Q));
f << ";\n"; f << ";\n";
} }
@ -1044,22 +1044,22 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (!out_is_reg_wire) { if (!out_is_reg_wire) {
f << stringf("%s" "assign ", indent.c_str()); f << stringf("%s" "assign ", indent.c_str());
dump_sigspec(f, cell->getPort("\\Q")); dump_sigspec(f, cell->getPort(ID::Q));
f << stringf(" = %s;\n", reg_name.c_str()); f << stringf(" = %s;\n", reg_name.c_str());
} }
return true; return true;
} }
if (cell->type == "$mem") if (cell->type == ID($mem))
{ {
RTLIL::IdString memid = cell->parameters["\\MEMID"].decode_string(); RTLIL::IdString memid = cell->parameters[ID::MEMID].decode_string();
std::string mem_id = id(cell->parameters["\\MEMID"].decode_string()); std::string mem_id = id(cell->parameters[ID::MEMID].decode_string());
int abits = cell->parameters["\\ABITS"].as_int(); int abits = cell->parameters[ID::ABITS].as_int();
int size = cell->parameters["\\SIZE"].as_int(); int size = cell->parameters[ID::SIZE].as_int();
int offset = cell->parameters["\\OFFSET"].as_int(); int offset = cell->parameters[ID::OFFSET].as_int();
int width = cell->parameters["\\WIDTH"].as_int(); int width = cell->parameters[ID::WIDTH].as_int();
bool use_init = !(RTLIL::SigSpec(cell->parameters["\\INIT"]).is_fully_undef()); bool use_init = !(RTLIL::SigSpec(cell->parameters[ID::INIT]).is_fully_undef());
// for memory block make something like: // for memory block make something like:
// reg [7:0] memid [3:0]; // reg [7:0] memid [3:0];
@ -1099,7 +1099,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{ {
for (int i=0; i<size; i++) for (int i=0; i<size; i++)
{ {
RTLIL::Const element = cell->parameters["\\INIT"].extract(i*width, width); RTLIL::Const element = cell->parameters[ID::INIT].extract(i*width, width);
for (int j=0; j<element.size(); j++) for (int j=0; j<element.size(); j++)
{ {
switch (element[element.size()-j-1]) switch (element[element.size()-j-1])
@ -1123,7 +1123,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
for (int i=0; i<size; i++) for (int i=0; i<size; i++)
{ {
f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i); f << stringf("%s" " %s[%d] = ", indent.c_str(), mem_id.c_str(), i);
dump_const(f, cell->parameters["\\INIT"].extract(i*width, width)); dump_const(f, cell->parameters[ID::INIT].extract(i*width, width));
f << stringf(";\n"); f << stringf(";\n");
} }
f << stringf("%s" "end\n", indent.c_str()); f << stringf("%s" "end\n", indent.c_str());
@ -1137,19 +1137,19 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// create a list of reg declarations // create a list of reg declarations
std::vector<std::string> lof_reg_declarations; std::vector<std::string> lof_reg_declarations;
int nread_ports = cell->parameters["\\RD_PORTS"].as_int(); int nread_ports = cell->parameters[ID::RD_PORTS].as_int();
RTLIL::SigSpec sig_rd_clk, sig_rd_en, sig_rd_data, sig_rd_addr; RTLIL::SigSpec sig_rd_clk, sig_rd_en, sig_rd_data, sig_rd_addr;
bool use_rd_clk, rd_clk_posedge, rd_transparent; bool use_rd_clk, rd_clk_posedge, rd_transparent;
// read ports // read ports
for (int i=0; i < nread_ports; i++) for (int i=0; i < nread_ports; i++)
{ {
sig_rd_clk = cell->getPort("\\RD_CLK").extract(i); sig_rd_clk = cell->getPort(ID::RD_CLK).extract(i);
sig_rd_en = cell->getPort("\\RD_EN").extract(i); sig_rd_en = cell->getPort(ID::RD_EN).extract(i);
sig_rd_data = cell->getPort("\\RD_DATA").extract(i*width, width); sig_rd_data = cell->getPort(ID::RD_DATA).extract(i*width, width);
sig_rd_addr = cell->getPort("\\RD_ADDR").extract(i*abits, abits); sig_rd_addr = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
use_rd_clk = cell->parameters["\\RD_CLK_ENABLE"].extract(i).as_bool(); use_rd_clk = cell->parameters[ID::RD_CLK_ENABLE].extract(i).as_bool();
rd_clk_posedge = cell->parameters["\\RD_CLK_POLARITY"].extract(i).as_bool(); rd_clk_posedge = cell->parameters[ID::RD_CLK_POLARITY].extract(i).as_bool();
rd_transparent = cell->parameters["\\RD_TRANSPARENT"].extract(i).as_bool(); rd_transparent = cell->parameters[ID::RD_TRANSPARENT].extract(i).as_bool();
if (use_rd_clk) if (use_rd_clk)
{ {
{ {
@ -1221,18 +1221,18 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
} }
} }
int nwrite_ports = cell->parameters["\\WR_PORTS"].as_int(); int nwrite_ports = cell->parameters[ID::WR_PORTS].as_int();
RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en; RTLIL::SigSpec sig_wr_clk, sig_wr_data, sig_wr_addr, sig_wr_en;
bool wr_clk_posedge; bool wr_clk_posedge;
// write ports // write ports
for (int i=0; i < nwrite_ports; i++) for (int i=0; i < nwrite_ports; i++)
{ {
sig_wr_clk = cell->getPort("\\WR_CLK").extract(i); sig_wr_clk = cell->getPort(ID::WR_CLK).extract(i);
sig_wr_data = cell->getPort("\\WR_DATA").extract(i*width, width); sig_wr_data = cell->getPort(ID::WR_DATA).extract(i*width, width);
sig_wr_addr = cell->getPort("\\WR_ADDR").extract(i*abits, abits); sig_wr_addr = cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
sig_wr_en = cell->getPort("\\WR_EN").extract(i*width, width); sig_wr_en = cell->getPort(ID::WR_EN).extract(i*width, width);
wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool(); wr_clk_posedge = cell->parameters[ID::WR_CLK_POLARITY].extract(i).as_bool();
{ {
std::ostringstream os; std::ostringstream os;
dump_sigspec(os, sig_wr_clk); dump_sigspec(os, sig_wr_clk);
@ -1319,66 +1319,66 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type.in("$assert", "$assume", "$cover")) if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{ {
f << stringf("%s" "always @* if (", indent.c_str()); f << stringf("%s" "always @* if (", indent.c_str());
dump_sigspec(f, cell->getPort("\\EN")); dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(") %s(", cell->type.c_str()+1); f << stringf(") %s(", cell->type.c_str()+1);
dump_sigspec(f, cell->getPort(ID::A)); dump_sigspec(f, cell->getPort(ID::A));
f << stringf(");\n"); f << stringf(");\n");
return true; return true;
} }
if (cell->type.in("$specify2", "$specify3")) if (cell->type.in(ID($specify2), ID($specify3)))
{ {
f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str());
SigSpec en = cell->getPort("\\EN"); SigSpec en = cell->getPort(ID::EN);
if (en != State::S1) { if (en != State::S1) {
f << stringf("if ("); f << stringf("if (");
dump_sigspec(f, cell->getPort("\\EN")); dump_sigspec(f, cell->getPort(ID::EN));
f << stringf(") "); f << stringf(") ");
} }
f << "("; f << "(";
if (cell->type == "$specify3" && cell->getParam("\\EDGE_EN").as_bool()) if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
f << (cell->getParam("\\EDGE_POL").as_bool() ? "posedge ": "negedge "); f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort("\\SRC")); dump_sigspec(f, cell->getPort(ID::SRC));
f << " "; f << " ";
if (cell->getParam("\\SRC_DST_PEN").as_bool()) if (cell->getParam(ID::SRC_DST_PEN).as_bool())
f << (cell->getParam("\\SRC_DST_POL").as_bool() ? "+": "-"); f << (cell->getParam(ID::SRC_DST_POL).as_bool() ? "+": "-");
f << (cell->getParam("\\FULL").as_bool() ? "*> ": "=> "); f << (cell->getParam(ID::FULL).as_bool() ? "*> ": "=> ");
if (cell->type == "$specify3") { if (cell->type == ID($specify3)) {
f << "("; f << "(";
dump_sigspec(f, cell->getPort("\\DST")); dump_sigspec(f, cell->getPort(ID::DST));
f << " "; f << " ";
if (cell->getParam("\\DAT_DST_PEN").as_bool()) if (cell->getParam(ID::DAT_DST_PEN).as_bool())
f << (cell->getParam("\\DAT_DST_POL").as_bool() ? "+": "-"); f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-");
f << ": "; f << ": ";
dump_sigspec(f, cell->getPort("\\DAT")); dump_sigspec(f, cell->getPort(ID::DAT));
f << ")"; f << ")";
} else { } else {
dump_sigspec(f, cell->getPort("\\DST")); dump_sigspec(f, cell->getPort(ID::DST));
} }
bool bak_decimal = decimal; bool bak_decimal = decimal;
decimal = 1; decimal = 1;
f << ") = ("; f << ") = (";
dump_const(f, cell->getParam("\\T_RISE_MIN")); dump_const(f, cell->getParam(ID::T_RISE_MIN));
f << ":"; f << ":";
dump_const(f, cell->getParam("\\T_RISE_TYP")); dump_const(f, cell->getParam(ID::T_RISE_TYP));
f << ":"; f << ":";
dump_const(f, cell->getParam("\\T_RISE_MAX")); dump_const(f, cell->getParam(ID::T_RISE_MAX));
f << ", "; f << ", ";
dump_const(f, cell->getParam("\\T_FALL_MIN")); dump_const(f, cell->getParam(ID::T_FALL_MIN));
f << ":"; f << ":";
dump_const(f, cell->getParam("\\T_FALL_TYP")); dump_const(f, cell->getParam(ID::T_FALL_TYP));
f << ":"; f << ":";
dump_const(f, cell->getParam("\\T_FALL_MAX")); dump_const(f, cell->getParam(ID::T_FALL_MAX));
f << ");\n"; f << ");\n";
decimal = bak_decimal; decimal = bak_decimal;
@ -1387,49 +1387,49 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true; return true;
} }
if (cell->type == "$specrule") if (cell->type == ID($specrule))
{ {
f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str()); f << stringf("%s" "specify\n%s ", indent.c_str(), indent.c_str());
string spec_type = cell->getParam("\\TYPE").decode_string(); IdString spec_type = cell->getParam(ID::TYPE).decode_string();
f << stringf("%s(", spec_type.c_str()); f << stringf("%s(", spec_type.c_str());
if (cell->getParam("\\SRC_PEN").as_bool()) if (cell->getParam(ID::SRC_PEN).as_bool())
f << (cell->getParam("\\SRC_POL").as_bool() ? "posedge ": "negedge "); f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort("\\SRC")); dump_sigspec(f, cell->getPort(ID::SRC));
if (cell->getPort("\\SRC_EN") != State::S1) { if (cell->getPort(ID::SRC_EN) != State::S1) {
f << " &&& "; f << " &&& ";
dump_sigspec(f, cell->getPort("\\SRC_EN")); dump_sigspec(f, cell->getPort(ID::SRC_EN));
} }
f << ", "; f << ", ";
if (cell->getParam("\\DST_PEN").as_bool()) if (cell->getParam(ID::DST_PEN).as_bool())
f << (cell->getParam("\\DST_POL").as_bool() ? "posedge ": "negedge "); f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort("\\DST")); dump_sigspec(f, cell->getPort(ID::DST));
if (cell->getPort("\\DST_EN") != State::S1) { if (cell->getPort(ID::DST_EN) != State::S1) {
f << " &&& "; f << " &&& ";
dump_sigspec(f, cell->getPort("\\DST_EN")); dump_sigspec(f, cell->getPort(ID::DST_EN));
} }
bool bak_decimal = decimal; bool bak_decimal = decimal;
decimal = 1; decimal = 1;
f << ", "; f << ", ";
dump_const(f, cell->getParam("\\T_LIMIT_MIN")); dump_const(f, cell->getParam(ID::T_LIMIT_MIN));
f << ": "; f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT_TYP")); dump_const(f, cell->getParam(ID::T_LIMIT_TYP));
f << ": "; f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT_MAX")); dump_const(f, cell->getParam(ID::T_LIMIT_MAX));
if (spec_type == "$setuphold" || spec_type == "$recrem" || spec_type == "$fullskew") { if (spec_type.in(ID($setuphold), ID($recrem), ID($fullskew))) {
f << ", "; f << ", ";
dump_const(f, cell->getParam("\\T_LIMIT2_MIN")); dump_const(f, cell->getParam(ID::T_LIMIT2_MIN));
f << ": "; f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT2_TYP")); dump_const(f, cell->getParam(ID::T_LIMIT2_TYP));
f << ": "; f << ": ";
dump_const(f, cell->getParam("\\T_LIMIT2_MAX")); dump_const(f, cell->getParam(ID::T_LIMIT2_MAX));
} }
f << ");\n"; f << ");\n";
@ -1513,9 +1513,9 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
} }
} }
if (siminit && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { if (siminit && reg_ct.count(cell->type) && cell->hasPort(ID::Q)) {
std::stringstream ss; std::stringstream ss;
dump_reg_init(ss, cell->getPort("\\Q")); dump_reg_init(ss, cell->getPort(ID::Q));
if (!ss.str().empty()) { if (!ss.str().empty()) {
f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str()); f << stringf("%sinitial %s.Q", indent.c_str(), cell_name.c_str());
f << ss.str(); f << ss.str();
@ -1698,9 +1698,9 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
active_initdata.clear(); active_initdata.clear();
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
SigSpec sig = active_sigmap(wire); SigSpec sig = active_sigmap(wire);
Const val = wire->attributes.at("\\init"); Const val = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++) for (int i = 0; i < GetSize(sig) && i < GetSize(val); i++)
if (val[i] == State::S0 || val[i] == State::S1) if (val[i] == State::S0 || val[i] == State::S1)
active_initdata[sig[i]] = val[i]; active_initdata[sig[i]] = val[i];
@ -1721,10 +1721,10 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
std::set<std::pair<RTLIL::Wire*,int>> reg_bits; std::set<std::pair<RTLIL::Wire*,int>> reg_bits;
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (!reg_ct.count(cell->type) || !cell->hasPort("\\Q")) if (!reg_ct.count(cell->type) || !cell->hasPort(ID::Q))
continue; continue;
RTLIL::SigSpec sig = cell->getPort("\\Q"); RTLIL::SigSpec sig = cell->getPort(ID::Q);
if (sig.is_chunk()) { if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk(); RTLIL::SigChunk chunk = sig.as_chunk();
@ -1889,31 +1889,31 @@ struct VerilogBackend : public Backend {
reg_wires.clear(); reg_wires.clear();
reg_ct.clear(); reg_ct.clear();
reg_ct.insert("$dff"); reg_ct.insert(ID($dff));
reg_ct.insert("$adff"); reg_ct.insert(ID($adff));
reg_ct.insert("$dffe"); reg_ct.insert(ID($dffe));
reg_ct.insert("$dlatch"); reg_ct.insert(ID($dlatch));
reg_ct.insert("$_DFF_N_"); reg_ct.insert(ID($_DFF_N_));
reg_ct.insert("$_DFF_P_"); reg_ct.insert(ID($_DFF_P_));
reg_ct.insert("$_DFF_NN0_"); reg_ct.insert(ID($_DFF_NN0_));
reg_ct.insert("$_DFF_NN1_"); reg_ct.insert(ID($_DFF_NN1_));
reg_ct.insert("$_DFF_NP0_"); reg_ct.insert(ID($_DFF_NP0_));
reg_ct.insert("$_DFF_NP1_"); reg_ct.insert(ID($_DFF_NP1_));
reg_ct.insert("$_DFF_PN0_"); reg_ct.insert(ID($_DFF_PN0_));
reg_ct.insert("$_DFF_PN1_"); reg_ct.insert(ID($_DFF_PN1_));
reg_ct.insert("$_DFF_PP0_"); reg_ct.insert(ID($_DFF_PP0_));
reg_ct.insert("$_DFF_PP1_"); reg_ct.insert(ID($_DFF_PP1_));
reg_ct.insert("$_DFFSR_NNN_"); reg_ct.insert(ID($_DFFSR_NNN_));
reg_ct.insert("$_DFFSR_NNP_"); reg_ct.insert(ID($_DFFSR_NNP_));
reg_ct.insert("$_DFFSR_NPN_"); reg_ct.insert(ID($_DFFSR_NPN_));
reg_ct.insert("$_DFFSR_NPP_"); reg_ct.insert(ID($_DFFSR_NPP_));
reg_ct.insert("$_DFFSR_PNN_"); reg_ct.insert(ID($_DFFSR_PNN_));
reg_ct.insert("$_DFFSR_PNP_"); reg_ct.insert(ID($_DFFSR_PNP_));
reg_ct.insert("$_DFFSR_PPN_"); reg_ct.insert(ID($_DFFSR_PPN_));
reg_ct.insert("$_DFFSR_PPP_"); reg_ct.insert(ID($_DFFSR_PPP_));
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {

46
frontends/aiger/aigerparse.cc
View file

@ -125,7 +125,7 @@ struct ConstEvalAig
if (!inputs.count(sig_a)) if (!inputs.count(sig_a))
compute_deps(sig_a, inputs); compute_deps(sig_a, inputs);
if (cell->type == "$_AND_") { if (cell->type == ID($_AND_)) {
RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_b = cell->getPort(ID::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and // that may occur does so here, and
@ -135,7 +135,7 @@ struct ConstEvalAig
if (!inputs.count(sig_b)) if (!inputs.count(sig_b))
compute_deps(sig_b, inputs); compute_deps(sig_b, inputs);
} }
else if (cell->type == "$_NOT_") { else if (cell->type == ID($_NOT_)) {
} }
else log_abort(); else log_abort();
} }
@ -151,11 +151,11 @@ struct ConstEvalAig
return false; return false;
RTLIL::State eval_ret = RTLIL::Sx; RTLIL::State eval_ret = RTLIL::Sx;
if (cell->type == "$_NOT_") { if (cell->type == ID($_NOT_)) {
if (sig_a == State::S0) eval_ret = State::S1; if (sig_a == State::S0) eval_ret = State::S1;
else if (sig_a == State::S1) eval_ret = State::S0; else if (sig_a == State::S1) eval_ret = State::S0;
} }
else if (cell->type == "$_AND_") { else if (cell->type == ID($_AND_)) {
if (sig_a == State::S0) { if (sig_a == State::S0) {
eval_ret = State::S0; eval_ret = State::S0;
goto eval_end; goto eval_end;
@ -478,9 +478,9 @@ void AigerReader::parse_xaiger()
log_assert(boxUniqueId > 0); log_assert(boxUniqueId > 0);
uint32_t oldBoxNum = parse_xaiger_literal(f); uint32_t oldBoxNum = parse_xaiger_literal(f);
RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId)); RTLIL::Cell* cell = module->addCell(stringf("$box%u", oldBoxNum), stringf("$__boxid%u", boxUniqueId));
cell->setPort("\\i", SigSpec(State::S0, boxInputs)); cell->setPort(ID(i), SigSpec(State::S0, boxInputs));
cell->setPort("\\o", SigSpec(State::S0, boxOutputs)); cell->setPort(ID(o), SigSpec(State::S0, boxOutputs));
cell->attributes["\\abc9_box_seq"] = oldBoxNum; cell->attributes[ID::abc9_box_seq] = oldBoxNum;
boxes.emplace_back(cell); boxes.emplace_back(cell);
} }
} }
@ -548,18 +548,18 @@ void AigerReader::parse_aiger_ascii()
log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_error("Line %u cannot be interpreted as a latch!\n", line_count);
if (l3 == 0) if (l3 == 0)
q_wire->attributes["\\init"] = State::S0; q_wire->attributes[ID::init] = State::S0;
else if (l3 == 1) else if (l3 == 1)
q_wire->attributes["\\init"] = State::S1; q_wire->attributes[ID::init] = State::S1;
else if (l3 == l1) { else if (l3 == l1) {
//q_wire->attributes["\\init"] = RTLIL::Sx; //q_wire->attributes[ID::init] = RTLIL::Sx;
} }
else else
log_error("Line %u has invalid reset literal for latch!\n", line_count); log_error("Line %u has invalid reset literal for latch!\n", line_count);
} }
else { else {
// AIGER latches are assumed to be initialized to zero // AIGER latches are assumed to be initialized to zero
q_wire->attributes["\\init"] = State::S0; q_wire->attributes[ID::init] = State::S0;
} }
latches.push_back(q_wire); latches.push_back(q_wire);
} }
@ -673,18 +673,18 @@ void AigerReader::parse_aiger_binary()
log_error("Line %u cannot be interpreted as a latch!\n", line_count); log_error("Line %u cannot be interpreted as a latch!\n", line_count);
if (l3 == 0) if (l3 == 0)
q_wire->attributes["\\init"] = State::S0; q_wire->attributes[ID::init] = State::S0;
else if (l3 == 1) else if (l3 == 1)
q_wire->attributes["\\init"] = State::S1; q_wire->attributes[ID::init] = State::S1;
else if (l3 == l1) { else if (l3 == l1) {
//q_wire->attributes["\\init"] = RTLIL::Sx; //q_wire->attributes[ID::init] = RTLIL::Sx;
} }
else else
log_error("Line %u has invalid reset literal for latch!\n", line_count); log_error("Line %u has invalid reset literal for latch!\n", line_count);
} }
else { else {
// AIGER latches are assumed to be initialized to zero // AIGER latches are assumed to be initialized to zero
q_wire->attributes["\\init"] = State::S0; q_wire->attributes[ID::init] = State::S0;
} }
latches.push_back(q_wire); latches.push_back(q_wire);
} }
@ -747,7 +747,7 @@ void AigerReader::post_process()
{ {
unsigned ci_count = 0, co_count = 0; unsigned ci_count = 0, co_count = 0;
for (auto cell : boxes) { for (auto cell : boxes) {
for (auto &bit : cell->connections_.at("\\i")) { for (auto &bit : cell->connections_.at(ID(i))) {
log_assert(bit == State::S0); log_assert(bit == State::S0);
log_assert(co_count < outputs.size()); log_assert(co_count < outputs.size());
bit = outputs[co_count++]; bit = outputs[co_count++];
@ -755,7 +755,7 @@ void AigerReader::post_process()
log_assert(bit.wire->port_output); log_assert(bit.wire->port_output);
bit.wire->port_output = false; bit.wire->port_output = false;
} }
for (auto &bit : cell->connections_.at("\\o")) { for (auto &bit : cell->connections_.at(ID(o))) {
log_assert(bit == State::S0); log_assert(bit == State::S0);
log_assert((piNum + ci_count) < inputs.size()); log_assert((piNum + ci_count) < inputs.size());
bit = inputs[piNum + ci_count++]; bit = inputs[piNum + ci_count++];
@ -776,10 +776,10 @@ void AigerReader::post_process()
log_assert(q->port_input); log_assert(q->port_input);
q->port_input = false; q->port_input = false;
auto ff = module->addCell(NEW_ID, "$__ABC9_FF_"); auto ff = module->addCell(NEW_ID, ID($__ABC9_FF_));
ff->setPort("\\D", d); ff->setPort(ID::D, d);
ff->setPort("\\Q", q); ff->setPort(ID::Q, q);
ff->attributes["\\abc9_mergeability"] = mergeability[i]; ff->attributes[ID::abc9_mergeability] = mergeability[i];
} }
dict<RTLIL::IdString, int> wideports_cache; dict<RTLIL::IdString, int> wideports_cache;
@ -866,7 +866,7 @@ void AigerReader::post_process()
int init; int init;
mf >> init; mf >> init;
if (init < 2) if (init < 2)
wire->attributes["\\init"] = init; wire->attributes[ID::init] = init;
} }
else if (type == "box") { else if (type == "box") {
RTLIL::Cell* cell = module->cell(stringf("$box%d", variable)); RTLIL::Cell* cell = module->cell(stringf("$box%d", variable));
@ -929,7 +929,7 @@ void AigerReader::post_process()
design->add(module); design->add(module);
for (auto cell : module->cells().to_vector()) { for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue; if (cell->type != ID($lut)) continue;
auto y_port = cell->getPort(ID::Y).as_bit(); auto y_port = cell->getPort(ID::Y).as_bit();
if (y_port.wire->width == 1) if (y_port.wire->width == 1)
module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str())); module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));

68
frontends/ast/ast.cc
View file

@ -954,7 +954,7 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
current_module->name = ast->str; current_module->name = ast->str;
current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line, current_module->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", ast->filename.c_str(), ast->location.first_line,
ast->location.first_column, ast->location.last_line, ast->location.last_column); ast->location.first_column, ast->location.last_line, ast->location.last_column);
current_module->set_bool_attribute("\\cells_not_processed"); current_module->set_bool_attribute(ID::cells_not_processed);
current_ast_mod = ast; current_ast_mod = ast;
AstNode *ast_before_simplify; AstNode *ast_before_simplify;
@ -1007,61 +1007,61 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
log("--- END OF AST DUMP ---\n"); log("--- END OF AST DUMP ---\n");
} }
if (flag_nowb && ast->attributes.count("\\whitebox")) { if (flag_nowb && ast->attributes.count(ID::whitebox)) {
delete ast->attributes.at("\\whitebox"); delete ast->attributes.at(ID::whitebox);
ast->attributes.erase("\\whitebox"); ast->attributes.erase(ID::whitebox);
} }
if (ast->attributes.count("\\lib_whitebox")) { if (ast->attributes.count(ID::lib_whitebox)) {
if (!flag_lib || flag_nowb) { if (!flag_lib || flag_nowb) {
delete ast->attributes.at("\\lib_whitebox"); delete ast->attributes.at(ID::lib_whitebox);
ast->attributes.erase("\\lib_whitebox"); ast->attributes.erase(ID::lib_whitebox);
} else { } else {
if (ast->attributes.count("\\whitebox")) { if (ast->attributes.count(ID::whitebox)) {
delete ast->attributes.at("\\whitebox"); delete ast->attributes.at(ID::whitebox);
ast->attributes.erase("\\whitebox"); ast->attributes.erase(ID::whitebox);
} }
AstNode *n = ast->attributes.at("\\lib_whitebox"); AstNode *n = ast->attributes.at(ID::lib_whitebox);
ast->attributes["\\whitebox"] = n; ast->attributes[ID::whitebox] = n;
ast->attributes.erase("\\lib_whitebox"); ast->attributes.erase(ID::lib_whitebox);
} }
} }
if (!blackbox_module && ast->attributes.count("\\blackbox")) { if (!blackbox_module && ast->attributes.count(ID::blackbox)) {
AstNode *n = ast->attributes.at("\\blackbox"); AstNode *n = ast->attributes.at(ID::blackbox);
if (n->type != AST_CONSTANT) if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n"); log_file_error(ast->filename, ast->location.first_line, "Got blackbox attribute with non-constant value!\n");
blackbox_module = n->asBool(); blackbox_module = n->asBool();
} }
if (blackbox_module && ast->attributes.count("\\whitebox")) { if (blackbox_module && ast->attributes.count(ID::whitebox)) {
AstNode *n = ast->attributes.at("\\whitebox"); AstNode *n = ast->attributes.at(ID::whitebox);
if (n->type != AST_CONSTANT) if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n"); log_file_error(ast->filename, ast->location.first_line, "Got whitebox attribute with non-constant value!\n");
blackbox_module = !n->asBool(); blackbox_module = !n->asBool();
} }
if (ast->attributes.count("\\noblackbox")) { if (ast->attributes.count(ID::noblackbox)) {
if (blackbox_module) { if (blackbox_module) {
AstNode *n = ast->attributes.at("\\noblackbox"); AstNode *n = ast->attributes.at(ID::noblackbox);
if (n->type != AST_CONSTANT) if (n->type != AST_CONSTANT)
log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n"); log_file_error(ast->filename, ast->location.first_line, "Got noblackbox attribute with non-constant value!\n");
blackbox_module = !n->asBool(); blackbox_module = !n->asBool();
} }
delete ast->attributes.at("\\noblackbox"); delete ast->attributes.at(ID::noblackbox);
ast->attributes.erase("\\noblackbox"); ast->attributes.erase(ID::noblackbox);
} }
if (blackbox_module) if (blackbox_module)
{ {
if (ast->attributes.count("\\whitebox")) { if (ast->attributes.count(ID::whitebox)) {
delete ast->attributes.at("\\whitebox"); delete ast->attributes.at(ID::whitebox);
ast->attributes.erase("\\whitebox"); ast->attributes.erase(ID::whitebox);
} }
if (ast->attributes.count("\\lib_whitebox")) { if (ast->attributes.count(ID::lib_whitebox)) {
delete ast->attributes.at("\\lib_whitebox"); delete ast->attributes.at(ID::lib_whitebox);
ast->attributes.erase("\\lib_whitebox"); ast->attributes.erase(ID::lib_whitebox);
} }
std::vector<AstNode*> new_children; std::vector<AstNode*> new_children;
@ -1082,8 +1082,8 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
ast->children.swap(new_children); ast->children.swap(new_children);
if (ast->attributes.count("\\blackbox") == 0) { if (ast->attributes.count(ID::blackbox) == 0) {
ast->attributes["\\blackbox"] = AstNode::mkconst_int(1, false); ast->attributes[ID::blackbox] = AstNode::mkconst_int(1, false);
} }
} }
@ -1212,7 +1212,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
continue; continue;
} else { } else {
log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n", log("Replacing existing%s module `%s' at %s:%d.%d-%d.%d.\n",
existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->location.first_line, (*it)->location.first_column, (*it)->location.last_line, (*it)->location.last_column);
design->remove(existing_mod); design->remove(existing_mod);
} }
@ -1385,7 +1385,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
std::string original_name = this->name.str(); std::string original_name = this->name.str();
std::string changed_name = original_name + "_before_replacing_local_interfaces"; std::string changed_name = original_name + "_before_replacing_local_interfaces";
design->rename(this, changed_name); design->rename(this, changed_name);
this->set_bool_attribute("\\to_delete"); this->set_bool_attribute(ID::to_delete);
// Check if the module was the top module. If it was, we need to remove the top attribute and put it on the // Check if the module was the top module. If it was, we need to remove the top attribute and put it on the
// new module. // new module.
@ -1403,7 +1403,7 @@ void AstModule::reprocess_module(RTLIL::Design *design, const dict<RTLIL::IdStri
mod->set_bool_attribute(ID::top); mod->set_bool_attribute(ID::top);
// Set the attribute "interfaces_replaced_in_module" so that it does not happen again. // Set the attribute "interfaces_replaced_in_module" so that it does not happen again.
mod->set_bool_attribute("\\interfaces_replaced_in_module"); mod->set_bool_attribute(ID::interfaces_replaced_in_module);
} }
// create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces // create a new parametric module (when needed) and return the name of the generated module - WITH support for interfaces
@ -1482,7 +1482,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
// If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module': // If any interfaces were replaced, set the attribute 'interfaces_replaced_in_module':
if (interfaces.size() > 0) { if (interfaces.size() > 0) {
mod->set_bool_attribute("\\interfaces_replaced_in_module"); mod->set_bool_attribute(ID::interfaces_replaced_in_module);
} }
} else { } else {
@ -1496,7 +1496,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdStr
// create a new parametric module (when needed) and return the name of the generated module - without support for interfaces // create a new parametric module (when needed) and return the name of the generated module - without support for interfaces
RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/) RTLIL::IdString AstModule::derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool /*mayfail*/)
{ {
bool quiet = lib || attributes.count(ID(blackbox)) || attributes.count(ID(whitebox)); bool quiet = lib || attributes.count(ID::blackbox) || attributes.count(ID::whitebox);
AstNode *new_ast = NULL; AstNode *new_ast = NULL;
std::string modname = derive_common(design, parameters, &new_ast, quiet); std::string modname = derive_common(design, parameters, &new_ast, quiet);

256
frontends/ast/genrtlil.cc
View file

@ -41,12 +41,10 @@ using namespace AST;
using namespace AST_INTERNAL; using namespace AST_INTERNAL;
// helper function for creating RTLIL code for unary operations // helper function for creating RTLIL code for unary operations
static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true) static RTLIL::SigSpec uniop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &arg, bool gen_attributes = true)
{ {
std::stringstream sstr; IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); RTLIL::Cell *cell = current_module->addCell(name, type);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
@ -59,11 +57,11 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(arg.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(arg.size());
cell->setPort(ID::A, arg); cell->setPort(ID::A, arg);
cell->parameters["\\Y_WIDTH"] = result_width; cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
return wire; return wire;
} }
@ -76,10 +74,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
return; return;
} }
std::stringstream sstr; IdString name = stringf("$extend$%s:%d$%d", that->filename.c_str(), that->location.first_line, autoidx++);
sstr << "$extend" << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); RTLIL::Cell *cell = current_module->addCell(name, ID($pos));
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$pos");
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
@ -92,22 +88,20 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
cell->parameters["\\A_SIGNED"] = RTLIL::Const(is_signed); cell->parameters[ID::A_SIGNED] = RTLIL::Const(is_signed);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
cell->setPort(ID::A, sig); cell->setPort(ID::A, sig);
cell->parameters["\\Y_WIDTH"] = width; cell->parameters[ID::Y_WIDTH] = width;
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
sig = wire; sig = wire;
} }
// helper function for creating RTLIL code for binary operations // helper function for creating RTLIL code for binary operations
static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right) static RTLIL::SigSpec binop2rtlil(AstNode *that, IdString type, int result_width, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{ {
std::stringstream sstr; IdString name = stringf("%s$%s:%d$%d", type.c_str(), that->filename.c_str(), that->location.first_line, autoidx++);
sstr << type << "$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); RTLIL::Cell *cell = current_module->addCell(name, type);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
@ -119,16 +113,16 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
cell->parameters["\\A_SIGNED"] = RTLIL::Const(that->children[0]->is_signed); cell->parameters[ID::A_SIGNED] = RTLIL::Const(that->children[0]->is_signed);
cell->parameters["\\B_SIGNED"] = RTLIL::Const(that->children[1]->is_signed); cell->parameters[ID::B_SIGNED] = RTLIL::Const(that->children[1]->is_signed);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(left.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(left.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(right.size()); cell->parameters[ID::B_WIDTH] = RTLIL::Const(right.size());
cell->setPort(ID::A, left); cell->setPort(ID::A, left);
cell->setPort(ID::B, right); cell->setPort(ID::B, right);
cell->parameters["\\Y_WIDTH"] = result_width; cell->parameters[ID::Y_WIDTH] = result_width;
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
return wire; return wire;
} }
@ -141,7 +135,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
std::stringstream sstr; std::stringstream sstr;
sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++); sstr << "$ternary$" << that->filename << ":" << that->location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux"); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($mux));
cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line); cell->attributes[ID::src] = stringf("%s:%d", that->filename.c_str(), that->location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size()); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
@ -153,7 +147,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
cell->parameters["\\WIDTH"] = RTLIL::Const(left.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(left.size());
cell->setPort(ID::A, right); cell->setPort(ID::A, right);
cell->setPort(ID::B, left); cell->setPort(ID::B, left);
@ -267,7 +261,7 @@ struct AST_INTERNAL::ProcessGenerator
} }
// create initial assignments for the temporary signals // create initial assignments for the temporary signals
if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) { if ((flag_nolatches || always->get_bool_attribute(ID::nolatches) || current_module->get_bool_attribute(ID::nolatches)) && !found_clocked_sync) {
subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from))); subst_rvalue_map = subst_lvalue_from.to_sigbit_dict(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else { } else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from); addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
@ -420,7 +414,7 @@ struct AST_INTERNAL::ProcessGenerator
for (auto &lvalue_c : lvalue.chunks()) { for (auto &lvalue_c : lvalue.chunks()) {
RTLIL::SigSpec lhs = lvalue_c; RTLIL::SigSpec lhs = lvalue_c;
RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width); RTLIL::SigSpec rhs = rvalue.extract(offset, lvalue_c.width);
if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute("\\nosync")) if (inSyncRule && lvalue_c.wire && lvalue_c.wire->get_bool_attribute(ID::nosync))
rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size()); rhs = RTLIL::SigSpec(RTLIL::State::Sx, rhs.size());
remove_unwanted_lvalue_bits(lhs, rhs); remove_unwanted_lvalue_bits(lhs, rhs);
actions.push_back(RTLIL::SigSig(lhs, rhs)); actions.push_back(RTLIL::SigSig(lhs, rhs));
@ -842,7 +836,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this // Clifford's Device (http://www.clifford.at/cfun/cliffdev/). In this
// cases this variable is used to hold the type of the cell that should // cases this variable is used to hold the type of the cell that should
// be instantiated for this type of AST node. // be instantiated for this type of AST node.
std::string type_name; IdString type_name;
current_filename = filename; current_filename = filename;
@ -883,9 +877,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
for(size_t i=0; i<children.size();i++) { for(size_t i=0; i<children.size();i++) {
if(children[i]->type == AST_INTERFACEPORTTYPE) { if(children[i]->type == AST_INTERFACEPORTTYPE) {
std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str); std::pair<std::string,std::string> res = AST::split_modport_from_type(children[i]->str);
wire->attributes["\\interface_type"] = res.first; wire->attributes[ID::interface_type] = res.first;
if (res.second != "") if (res.second != "")
wire->attributes["\\interface_modport"] = res.second; wire->attributes[ID::interface_modport] = res.second;
break; break;
} }
} }
@ -911,7 +905,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
current_module->connect(wire, val); current_module->connect(wire, val);
wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); wire->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
wire->attributes[type == AST_PARAMETER ? "\\parameter" : "\\localparam"] = 1; wire->attributes[type == AST_PARAMETER ? ID::parameter : ID::localparam] = 1;
for (auto &attr : attributes) { for (auto &attr : attributes) {
if (attr.second->type != AST_CONSTANT) if (attr.second->type != AST_CONSTANT)
@ -1052,16 +1046,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// This makes it possible for the hierarchy pass to see what are interface connections and then replace them // This makes it possible for the hierarchy pass to see what are interface connections and then replace them
// with the individual signals: // with the individual signals:
if (is_interface) { if (is_interface) {
RTLIL::Wire *dummy_wire; IdString dummy_wire_name = stringf("$dummywireforinterface%s", str.c_str());
std::string dummy_wire_name = "$dummywireforinterface" + str; RTLIL::Wire *dummy_wire = current_module->wire(dummy_wire_name);
if (current_module->wires_.count(dummy_wire_name)) if (!dummy_wire) {
dummy_wire = current_module->wires_[dummy_wire_name];
else {
dummy_wire = current_module->addWire(dummy_wire_name); dummy_wire = current_module->addWire(dummy_wire_name);
dummy_wire->set_bool_attribute(ID::is_interface); dummy_wire->set_bool_attribute(ID::is_interface);
} }
RTLIL::SigSpec tmp = RTLIL::SigSpec(dummy_wire); return dummy_wire;
return tmp;
} }
wire = current_module->wires_[str]; wire = current_module->wires_[str];
@ -1097,7 +1088,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
if (GetSize(shift_val) >= 32) if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true; fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val); RTLIL::SigSpec sig = binop2rtlil(fake_ast, ID($shiftx), width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast; delete left_at_zero_ast;
delete right_at_zero_ast; delete right_at_zero_ast;
delete fake_ast; delete fake_ast;
@ -1181,9 +1172,9 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for unary operations: $not, $pos, $neg // generate cells for unary operations: $not, $pos, $neg
if (0) { case AST_BIT_NOT: type_name = "$not"; } if (0) { case AST_BIT_NOT: type_name = ID($not); }
if (0) { case AST_POS: type_name = "$pos"; } if (0) { case AST_POS: type_name = ID($pos); }
if (0) { case AST_NEG: type_name = "$neg"; } if (0) { case AST_NEG: type_name = ID($neg); }
{ {
RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec arg = children[0]->genRTLIL(width_hint, sign_hint);
is_signed = children[0]->is_signed; is_signed = children[0]->is_signed;
@ -1196,10 +1187,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for binary operations: $and, $or, $xor, $xnor // generate cells for binary operations: $and, $or, $xor, $xnor
if (0) { case AST_BIT_AND: type_name = "$and"; } if (0) { case AST_BIT_AND: type_name = ID($and); }
if (0) { case AST_BIT_OR: type_name = "$or"; } if (0) { case AST_BIT_OR: type_name = ID($or); }
if (0) { case AST_BIT_XOR: type_name = "$xor"; } if (0) { case AST_BIT_XOR: type_name = ID($xor); }
if (0) { case AST_BIT_XNOR: type_name = "$xnor"; } if (0) { case AST_BIT_XNOR: type_name = ID($xnor); }
{ {
if (width_hint < 0) if (width_hint < 0)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
@ -1213,10 +1204,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor // generate cells for unary operations: $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor
if (0) { case AST_REDUCE_AND: type_name = "$reduce_and"; } if (0) { case AST_REDUCE_AND: type_name = ID($reduce_and); }
if (0) { case AST_REDUCE_OR: type_name = "$reduce_or"; } if (0) { case AST_REDUCE_OR: type_name = ID($reduce_or); }
if (0) { case AST_REDUCE_XOR: type_name = "$reduce_xor"; } if (0) { case AST_REDUCE_XOR: type_name = ID($reduce_xor); }
if (0) { case AST_REDUCE_XNOR: type_name = "$reduce_xnor"; } if (0) { case AST_REDUCE_XNOR: type_name = ID($reduce_xnor); }
{ {
RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg); RTLIL::SigSpec sig = uniop2rtlil(this, type_name, max(width_hint, 1), arg);
@ -1225,7 +1216,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// generate cells for unary operations: $reduce_bool // generate cells for unary operations: $reduce_bool
// (this is actually just an $reduce_or, but for clarity a different cell type is used) // (this is actually just an $reduce_or, but for clarity a different cell type is used)
if (0) { case AST_REDUCE_BOOL: type_name = "$reduce_bool"; } if (0) { case AST_REDUCE_BOOL: type_name = ID($reduce_bool); }
{ {
RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec arg = children[0]->genRTLIL();
RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg; RTLIL::SigSpec sig = arg.size() > 1 ? uniop2rtlil(this, type_name, max(width_hint, 1), arg) : arg;
@ -1233,10 +1224,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for binary operations: $shl, $shr, $sshl, $sshr // generate cells for binary operations: $shl, $shr, $sshl, $sshr
if (0) { case AST_SHIFT_LEFT: type_name = "$shl"; } if (0) { case AST_SHIFT_LEFT: type_name = ID($shl); }
if (0) { case AST_SHIFT_RIGHT: type_name = "$shr"; } if (0) { case AST_SHIFT_RIGHT: type_name = ID($shr); }
if (0) { case AST_SHIFT_SLEFT: type_name = "$sshl"; } if (0) { case AST_SHIFT_SLEFT: type_name = ID($sshl); }
if (0) { case AST_SHIFT_SRIGHT: type_name = "$sshr"; } if (0) { case AST_SHIFT_SRIGHT: type_name = ID($sshr); }
{ {
if (width_hint < 0) if (width_hint < 0)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
@ -1260,19 +1251,19 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = width_hint > 0 ? width_hint : left.size(); int width = width_hint > 0 ? width_hint : left.size();
is_signed = children[0]->is_signed; is_signed = children[0]->is_signed;
if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed) if (!flag_noopt && left.is_fully_const() && left.as_int() == 2 && !right_signed)
return binop2rtlil(this, "$shl", width, RTLIL::SigSpec(1, left.size()), right); return binop2rtlil(this, ID($shl), width, RTLIL::SigSpec(1, left.size()), right);
return binop2rtlil(this, "$pow", width, left, right); return binop2rtlil(this, ID($pow), width, left, right);
} }
// generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt // generate cells for binary operations: $lt, $le, $eq, $ne, $ge, $gt
if (0) { case AST_LT: type_name = "$lt"; } if (0) { case AST_LT: type_name = ID($lt); }
if (0) { case AST_LE: type_name = "$le"; } if (0) { case AST_LE: type_name = ID($le); }
if (0) { case AST_EQ: type_name = "$eq"; } if (0) { case AST_EQ: type_name = ID($eq); }
if (0) { case AST_NE: type_name = "$ne"; } if (0) { case AST_NE: type_name = ID($ne); }
if (0) { case AST_EQX: type_name = "$eqx"; } if (0) { case AST_EQX: type_name = ID($eqx); }
if (0) { case AST_NEX: type_name = "$nex"; } if (0) { case AST_NEX: type_name = ID($nex); }
if (0) { case AST_GE: type_name = "$ge"; } if (0) { case AST_GE: type_name = ID($ge); }
if (0) { case AST_GT: type_name = "$gt"; } if (0) { case AST_GT: type_name = ID($gt); }
{ {
int width = max(width_hint, 1); int width = max(width_hint, 1);
width_hint = -1, sign_hint = true; width_hint = -1, sign_hint = true;
@ -1285,11 +1276,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for binary operations: $add, $sub, $mul, $div, $mod // generate cells for binary operations: $add, $sub, $mul, $div, $mod
if (0) { case AST_ADD: type_name = "$add"; } if (0) { case AST_ADD: type_name = ID($add); }
if (0) { case AST_SUB: type_name = "$sub"; } if (0) { case AST_SUB: type_name = ID($sub); }
if (0) { case AST_MUL: type_name = "$mul"; } if (0) { case AST_MUL: type_name = ID($mul); }
if (0) { case AST_DIV: type_name = "$div"; } if (0) { case AST_DIV: type_name = ID($div); }
if (0) { case AST_MOD: type_name = "$mod"; } if (0) { case AST_MOD: type_name = ID($mod); }
{ {
if (width_hint < 0) if (width_hint < 0)
detectSignWidth(width_hint, sign_hint); detectSignWidth(width_hint, sign_hint);
@ -1315,8 +1306,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
// generate cells for binary operations: $logic_and, $logic_or // generate cells for binary operations: $logic_and, $logic_or
if (0) { case AST_LOGIC_AND: type_name = "$logic_and"; } if (0) { case AST_LOGIC_AND: type_name = ID($logic_and); }
if (0) { case AST_LOGIC_OR: type_name = "$logic_or"; } if (0) { case AST_LOGIC_OR: type_name = ID($logic_or); }
{ {
RTLIL::SigSpec left = children[0]->genRTLIL(); RTLIL::SigSpec left = children[0]->genRTLIL();
RTLIL::SigSpec right = children[1]->genRTLIL(); RTLIL::SigSpec right = children[1]->genRTLIL();
@ -1327,7 +1318,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_LOGIC_NOT: case AST_LOGIC_NOT:
{ {
RTLIL::SigSpec arg = children[0]->genRTLIL(); RTLIL::SigSpec arg = children[0]->genRTLIL();
return uniop2rtlil(this, "$logic_not", max(width_hint, 1), arg); return uniop2rtlil(this, ID($logic_not), max(width_hint, 1), arg);
} }
// generate multiplexer for ternary operator (aka ?:-operator) // generate multiplexer for ternary operator (aka ?:-operator)
@ -1353,7 +1344,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint); RTLIL::SigSpec val2 = children[2]->genRTLIL(width_hint, sign_hint);
if (cond.size() > 1) if (cond.size() > 1)
cond = uniop2rtlil(this, "$reduce_bool", 1, cond, false); cond = uniop2rtlil(this, ID($reduce_bool), 1, cond, false);
int width = max(val1.size(), val2.size()); int width = max(val1.size(), val2.size());
is_signed = children[1]->is_signed && children[2]->is_signed; is_signed = children[1]->is_signed && children[2]->is_signed;
@ -1374,7 +1365,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr; std::stringstream sstr;
sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); sstr << "$memrd$" << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd"); RTLIL::Cell *cell = current_module->addCell(sstr.str(), ID($memrd));
cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line); cell->attributes[ID::src] = stringf("%s:%d", filename.c_str(), location.first_line);
RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width); RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
@ -1386,18 +1377,18 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::SigSpec addr_sig = children[0]->genRTLIL(); RTLIL::SigSpec addr_sig = children[0]->genRTLIL();
cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort("\\EN", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort(ID::EN, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort("\\ADDR", addr_sig); cell->setPort(ID::ADDR, addr_sig);
cell->setPort("\\DATA", RTLIL::SigSpec(wire)); cell->setPort(ID::DATA, RTLIL::SigSpec(wire));
cell->parameters["\\MEMID"] = RTLIL::Const(str); cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
cell->parameters["\\WIDTH"] = RTLIL::Const(wire->width); cell->parameters[ID::WIDTH] = RTLIL::Const(wire->width);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
if (!sign_hint) if (!sign_hint)
is_signed = false; is_signed = false;
@ -1412,7 +1403,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
std::stringstream sstr; std::stringstream sstr;
sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++); sstr << (type == AST_MEMWR ? "$memwr$" : "$meminit$") << str << "$" << filename << ":" << location.first_line << "$" << (autoidx++);
RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? "$memwr" : "$meminit"); RTLIL::Cell *cell = current_module->addCell(sstr.str(), type == AST_MEMWR ? ID($memwr) : ID($meminit));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
int mem_width, mem_size, addr_bits; int mem_width, mem_size, addr_bits;
@ -1423,26 +1414,26 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
if (children[2]->type != AST_CONSTANT) if (children[2]->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n"); log_file_error(filename, location.first_line, "Memory init with non-constant word count!\n");
num_words = int(children[2]->asInt(false)); num_words = int(children[2]->asInt(false));
cell->parameters["\\WORDS"] = RTLIL::Const(num_words); cell->parameters[ID::WORDS] = RTLIL::Const(num_words);
} }
SigSpec addr_sig = children[0]->genRTLIL(); SigSpec addr_sig = children[0]->genRTLIL();
cell->setPort("\\ADDR", addr_sig); cell->setPort(ID::ADDR, addr_sig);
cell->setPort("\\DATA", children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words)); cell->setPort(ID::DATA, children[1]->genWidthRTLIL(current_module->memories[str]->width * num_words));
cell->parameters["\\MEMID"] = RTLIL::Const(str); cell->parameters[ID::MEMID] = RTLIL::Const(str);
cell->parameters["\\ABITS"] = RTLIL::Const(GetSize(addr_sig)); cell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr_sig));
cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width); cell->parameters[ID::WIDTH] = RTLIL::Const(current_module->memories[str]->width);
if (type == AST_MEMWR) { if (type == AST_MEMWR) {
cell->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::Sx, 1)); cell->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::Sx, 1));
cell->setPort("\\EN", children[2]->genRTLIL()); cell->setPort(ID::EN, children[2]->genRTLIL());
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(0); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(0);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(0); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(0);
} }
cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
} }
break; break;
@ -1453,12 +1444,12 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
case AST_FAIR: case AST_FAIR:
case AST_COVER: case AST_COVER:
{ {
const char *celltype = nullptr; IdString celltype;
if (type == AST_ASSERT) celltype = "$assert"; if (type == AST_ASSERT) celltype = ID($assert);
if (type == AST_ASSUME) celltype = "$assume"; if (type == AST_ASSUME) celltype = ID($assume);
if (type == AST_LIVE) celltype = "$live"; if (type == AST_LIVE) celltype = ID($live);
if (type == AST_FAIR) celltype = "$fair"; if (type == AST_FAIR) celltype = ID($fair);
if (type == AST_COVER) celltype = "$cover"; if (type == AST_COVER) celltype = ID($cover);
log_assert(children.size() == 2); log_assert(children.size() == 2);
@ -1471,13 +1462,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
en = current_module->ReduceBool(NEW_ID, en); en = current_module->ReduceBool(NEW_ID, en);
IdString cellname; IdString cellname;
if (str.empty()) { if (str.empty())
std::stringstream sstr; cellname = stringf("%s$%s:%d$%d", celltype.c_str(), filename.c_str(), location.first_line, autoidx++);
sstr << celltype << "$" << filename << ":" << location.first_line << "$" << (autoidx++); else
cellname = sstr.str();
} else {
cellname = str; cellname = str;
}
RTLIL::Cell *cell = current_module->addCell(cellname, celltype); RTLIL::Cell *cell = current_module->addCell(cellname, celltype);
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
@ -1489,7 +1477,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
} }
cell->setPort(ID::A, check); cell->setPort(ID::A, check);
cell->setPort("\\EN", en); cell->setPort(ID::EN, en);
} }
break; break;
@ -1527,7 +1515,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Cell *cell = current_module->addCell(str, ""); RTLIL::Cell *cell = current_module->addCell(str, "");
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
// Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass // Set attribute 'module_not_derived' which will be cleared again after the hierarchy pass
cell->set_bool_attribute("\\module_not_derived"); cell->set_bool_attribute(ID::module_not_derived);
for (auto it = children.begin(); it != children.end(); it++) { for (auto it = children.begin(); it != children.end(); it++) {
AstNode *child = *it; AstNode *child = *it;
@ -1575,29 +1563,29 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); log_file_error(filename, location.first_line, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst(); cell->attributes[attr.first] = attr.second->asAttrConst();
} }
if (cell->type == "$specify2") { if (cell->type == ID($specify2)) {
int src_width = GetSize(cell->getPort("\\SRC")); int src_width = GetSize(cell->getPort(ID::SRC));
int dst_width = GetSize(cell->getPort("\\DST")); int dst_width = GetSize(cell->getPort(ID::DST));
bool full = cell->getParam("\\FULL").as_bool(); bool full = cell->getParam(ID::FULL).as_bool();
if (!full && src_width != dst_width) if (!full && src_width != dst_width)
log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n"); log_file_error(filename, location.first_line, "Parallel specify SRC width does not match DST width.\n");
cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam("\\DST_WIDTH", Const(dst_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width));
} }
else if (cell->type == "$specify3") { else if (cell->type == ID($specify3)) {
int dat_width = GetSize(cell->getPort("\\DAT")); int dat_width = GetSize(cell->getPort(ID::DAT));
int dst_width = GetSize(cell->getPort("\\DST")); int dst_width = GetSize(cell->getPort(ID::DST));
if (dat_width != dst_width) if (dat_width != dst_width)
log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n"); log_file_error(filename, location.first_line, "Specify DAT width does not match DST width.\n");
int src_width = GetSize(cell->getPort("\\SRC")); int src_width = GetSize(cell->getPort(ID::SRC));
cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam("\\DST_WIDTH", Const(dst_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width));
} }
else if (cell->type == "$specrule") { else if (cell->type == ID($specrule)) {
int src_width = GetSize(cell->getPort("\\SRC")); int src_width = GetSize(cell->getPort(ID::SRC));
int dst_width = GetSize(cell->getPort("\\DST")); int dst_width = GetSize(cell->getPort(ID::DST));
cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam(ID::SRC_WIDTH, Const(src_width));
cell->setParam("\\DST_WIDTH", Const(dst_width)); cell->setParam(ID::DST_WIDTH, Const(dst_width));
} }
} }
break; break;
@ -1669,13 +1657,13 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
Cell *cell = current_module->addCell(myid, str.substr(1)); Cell *cell = current_module->addCell(myid, str.substr(1));
cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column); cell->attributes[ID::src] = stringf("%s:%d.%d-%d.%d", filename.c_str(), location.first_line, location.first_column, location.last_line, location.last_column);
cell->parameters["\\WIDTH"] = width; cell->parameters[ID::WIDTH] = width;
if (attributes.count("\\reg")) { if (attributes.count(ID::reg)) {
auto &attr = attributes.at("\\reg"); auto &attr = attributes.at(ID::reg);
if (attr->type != AST_CONSTANT) if (attr->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n"); log_file_error(filename, location.first_line, "Attribute `reg' with non-constant value!\n");
cell->attributes["\\reg"] = attr->asAttrConst(); cell->attributes[ID::reg] = attr->asAttrConst();
} }
Wire *wire = current_module->addWire(myid + "_wire", width); Wire *wire = current_module->addWire(myid + "_wire", width);

28
frontends/ast/simplify.cc
View file

@ -172,7 +172,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
deep_recursion_warning = true; deep_recursion_warning = true;
while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { } while (simplify(const_fold, at_zero, in_lvalue, 1, width_hint, sign_hint, in_param)) { }
if (!flag_nomem2reg && !get_bool_attribute("\\nomem2reg")) if (!flag_nomem2reg && !get_bool_attribute(ID::nomem2reg))
{ {
dict<AstNode*, pool<std::string>> mem2reg_places; dict<AstNode*, pool<std::string>> mem2reg_places;
dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags; dict<AstNode*, uint32_t> mem2reg_candidates, dummy_proc_flags;
@ -187,10 +187,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
bool this_nomeminit = flag_nomeminit; bool this_nomeminit = flag_nomeminit;
log_assert((memflags & ~0x00ffff00) == 0); log_assert((memflags & ~0x00ffff00) == 0);
if (mem->get_bool_attribute("\\nomem2reg")) if (mem->get_bool_attribute(ID::nomem2reg))
continue; continue;
if (mem->get_bool_attribute("\\nomeminit") || get_bool_attribute("\\nomeminit")) if (mem->get_bool_attribute(ID::nomeminit) || get_bool_attribute(ID::nomeminit))
this_nomeminit = true; this_nomeminit = true;
if (memflags & AstNode::MEM2REG_FL_FORCED) if (memflags & AstNode::MEM2REG_FL_FORCED)
@ -248,7 +248,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
reg->is_reg = true; reg->is_reg = true;
reg->is_signed = node->is_signed; reg->is_signed = node->is_signed;
for (auto &it : node->attributes) for (auto &it : node->attributes)
if (it.first != ID(mem2reg)) if (it.first != ID::mem2reg)
reg->attributes.emplace(it.first, it.second->clone()); reg->attributes.emplace(it.first, it.second->clone());
reg->filename = node->filename; reg->filename = node->filename;
reg->location = node->location; reg->location = node->location;
@ -345,9 +345,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) {
for (auto c : node->children[0]->children) { for (auto c : node->children[0]->children) {
if (!c->is_simple_const_expr()) { if (!c->is_simple_const_expr()) {
if (attributes.count("\\dynports")) if (attributes.count(ID::dynports))
delete attributes.at("\\dynports"); delete attributes.at(ID::dynports);
attributes["\\dynports"] = AstNode::mkconst_int(1, true); attributes[ID::dynports] = AstNode::mkconst_int(1, true);
} }
} }
} }
@ -1219,7 +1219,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true))); AstNode *wire = new AstNode(AST_WIRE, new AstNode(AST_RANGE, mkconst_int(data_range_left, true), mkconst_int(data_range_right, true)));
wire->str = wire_id; wire->str = wire_id;
if (current_block) if (current_block)
wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
current_ast_mod->children.push_back(wire); current_ast_mod->children.push_back(wire);
while (wire->simplify(true, false, false, 1, -1, false, false)) { } while (wire->simplify(true, false, false, 1, -1, false, false)) { }
@ -1856,7 +1856,7 @@ skip_dynamic_range_lvalue_expansion:;
wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++); wire_tmp->str = stringf("$splitcmplxassign$%s:%d$%d", filename.c_str(), location.first_line, autoidx++);
current_ast_mod->children.push_back(wire_tmp); current_ast_mod->children.push_back(wire_tmp);
current_scope[wire_tmp->str] = wire_tmp; current_scope[wire_tmp->str] = wire_tmp;
wire_tmp->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_tmp->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { } while (wire_tmp->simplify(true, false, false, 1, -1, false, false)) { }
wire_tmp->is_logic = true; wire_tmp->is_logic = true;
@ -2676,7 +2676,7 @@ skip_dynamic_range_lvalue_expansion:;
wire->is_input = false; wire->is_input = false;
wire->is_output = false; wire->is_output = false;
wire->is_reg = true; wire->is_reg = true;
wire->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
if (child->type == AST_ENUM_ITEM) if (child->type == AST_ENUM_ITEM)
wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"]; wire->attributes["\\enum_base_type"] = child->attributes["\\enum_base_type"];
@ -3530,7 +3530,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
wire_addr->str = id_addr; wire_addr->str = id_addr;
wire_addr->is_reg = true; wire_addr->is_reg = true;
wire_addr->was_checked = true; wire_addr->was_checked = true;
wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr); mod->children.push_back(wire_addr);
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
@ -3539,7 +3539,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
wire_data->is_reg = true; wire_data->is_reg = true;
wire_data->was_checked = true; wire_data->was_checked = true;
wire_data->is_signed = mem_signed; wire_data->is_signed = mem_signed;
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data); mod->children.push_back(wire_data);
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }
@ -3610,7 +3610,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
wire_addr->is_reg = true; wire_addr->is_reg = true;
wire_addr->was_checked = true; wire_addr->was_checked = true;
if (block) if (block)
wire_addr->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_addr->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_addr); mod->children.push_back(wire_addr);
while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { } while (wire_addr->simplify(true, false, false, 1, -1, false, false)) { }
@ -3620,7 +3620,7 @@ bool AstNode::mem2reg_as_needed_pass2(pool<AstNode*> &mem2reg_set, AstNode *mod,
wire_data->was_checked = true; wire_data->was_checked = true;
wire_data->is_signed = mem_signed; wire_data->is_signed = mem_signed;
if (block) if (block)
wire_data->attributes["\\nosync"] = AstNode::mkconst_int(1, false); wire_data->attributes[ID::nosync] = AstNode::mkconst_int(1, false);
mod->children.push_back(wire_data); mod->children.push_back(wire_data);
while (wire_data->simplify(true, false, false, 1, -1, false, false)) { } while (wire_data->simplify(true, false, false, 1, -1, false, false)) { }

50
frontends/blif/blifparse.cc
View file

@ -176,7 +176,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (!strcmp(cmd, ".blackbox")) if (!strcmp(cmd, ".blackbox"))
{ {
module->attributes["\\blackbox"] = RTLIL::Const(1); module->attributes[ID::blackbox] = RTLIL::Const(1);
continue; continue;
} }
@ -215,7 +215,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
vector<Cell*> remove_cells; vector<Cell*> remove_cells;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) { if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A)); module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
remove_cells.push_back(cell); remove_cells.push_back(cell);
} }
@ -223,9 +223,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (auto cell : remove_cells) for (auto cell : remove_cells)
module->remove(cell); module->remove(cell);
Wire *true_wire = module->wire("$true"); Wire *true_wire = module->wire(ID($true));
Wire *false_wire = module->wire("$false"); Wire *false_wire = module->wire(ID($false));
Wire *undef_wire = module->wire("$undef"); Wire *undef_wire = module->wire(ID($undef));
if (true_wire != nullptr) if (true_wire != nullptr)
module->rename(true_wire, stringf("$true$%d", ++blif_maxnum)); module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
@ -337,7 +337,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
} }
if (init != nullptr && (init[0] == '0' || init[0] == '1')) if (init != nullptr && (init[0] == '0' || init[0] == '1'))
blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1); blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
if (clock == nullptr) if (clock == nullptr)
goto no_latch_clock; goto no_latch_clock;
@ -356,8 +356,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q)); cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
} else { } else {
cell = module->addCell(NEW_ID, dff_name); cell = module->addCell(NEW_ID, dff_name);
cell->setPort("\\D", blif_wire(d)); cell->setPort(ID::D, blif_wire(d));
cell->setPort("\\Q", blif_wire(q)); cell->setPort(ID::Q, blif_wire(q));
} }
} }
@ -476,7 +476,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
finished_parsing_constval: finished_parsing_constval:
if (state == RTLIL::State::Sa) if (state == RTLIL::State::Sa)
state = RTLIL::State::S0; state = RTLIL::State::S0;
if (output_sig.as_wire()->name == "$undef") if (output_sig.as_wire()->name == ID($undef))
state = RTLIL::State::Sx; state = RTLIL::State::Sx;
module->connect(RTLIL::SigSig(output_sig, state)); module->connect(RTLIL::SigSig(output_sig, state));
goto continue_without_read; goto continue_without_read;
@ -484,10 +484,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sop_mode) if (sop_mode)
{ {
sopcell = module->addCell(NEW_ID, "$sop"); sopcell = module->addCell(NEW_ID, ID($sop));
sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters["\\DEPTH"] = 0; sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters["\\TABLE"] = RTLIL::Const(); sopcell->parameters[ID::TABLE] = RTLIL::Const();
sopcell->setPort(ID::A, input_sig); sopcell->setPort(ID::A, input_sig);
sopcell->setPort(ID::Y, output_sig); sopcell->setPort(ID::Y, output_sig);
sopmode = -1; sopmode = -1;
@ -495,12 +495,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
} }
else else
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size()); cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig); cell->setPort(ID::A, input_sig);
cell->setPort(ID::Y, output_sig); cell->setPort(ID::Y, output_sig);
lutptr = &cell->parameters.at("\\LUT"); lutptr = &cell->parameters.at(ID::LUT);
lut_default_state = RTLIL::State::Sx; lut_default_state = RTLIL::State::Sx;
lastcell = cell; lastcell = cell;
} }
@ -523,22 +523,22 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sopcell) if (sopcell)
{ {
log_assert(sopcell->parameters["\\WIDTH"].as_int() == input_len); log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
sopcell->parameters["\\DEPTH"] = sopcell->parameters["\\DEPTH"].as_int() + 1; sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
for (int i = 0; i < input_len; i++) for (int i = 0; i < input_len; i++)
switch (input[i]) { switch (input[i]) {
case '0': case '0':
sopcell->parameters["\\TABLE"].bits.push_back(State::S1); sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
sopcell->parameters["\\TABLE"].bits.push_back(State::S0); sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break; break;
case '1': case '1':
sopcell->parameters["\\TABLE"].bits.push_back(State::S0); sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters["\\TABLE"].bits.push_back(State::S1); sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
break; break;
default: default:
sopcell->parameters["\\TABLE"].bits.push_back(State::S0); sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters["\\TABLE"].bits.push_back(State::S0); sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break; break;
} }

60
frontends/liberty/liberty.cc
View file

@ -55,7 +55,7 @@ static RTLIL::SigSpec parse_func_identifier(RTLIL::Module *module, const char *&
static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A) static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, A); cell->setPort(ID::A, A);
cell->setPort(ID::Y, module->addWire(NEW_ID)); cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y); return cell->getPort(ID::Y);
@ -63,7 +63,7 @@ static RTLIL::SigSpec create_inv_cell(RTLIL::Module *module, RTLIL::SigSpec A)
static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_XOR_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_XOR_));
cell->setPort(ID::A, A); cell->setPort(ID::A, A);
cell->setPort(ID::B, B); cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID)); cell->setPort(ID::Y, module->addWire(NEW_ID));
@ -72,7 +72,7 @@ static RTLIL::SigSpec create_xor_cell(RTLIL::Module *module, RTLIL::SigSpec A, R
static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_AND_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_AND_));
cell->setPort(ID::A, A); cell->setPort(ID::A, A);
cell->setPort(ID::B, B); cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID)); cell->setPort(ID::Y, module->addWire(NEW_ID));
@ -81,7 +81,7 @@ static RTLIL::SigSpec create_and_cell(RTLIL::Module *module, RTLIL::SigSpec A, R
static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B) static RTLIL::SigSpec create_or_cell(RTLIL::Module *module, RTLIL::SigSpec A, RTLIL::SigSpec B)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_OR_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_OR_));
cell->setPort(ID::A, A); cell->setPort(ID::A, A);
cell->setPort(ID::B, B); cell->setPort(ID::B, B);
cell->setPort(ID::Y, module->addWire(NEW_ID)); cell->setPort(ID::Y, module->addWire(NEW_ID));
@ -241,17 +241,17 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
rerun_invert_rollback = false; rerun_invert_rollback = false;
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clk_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
clk_sig = it.second->getPort(ID::A); clk_sig = it.second->getPort(ID::A);
clk_polarity = !clk_polarity; clk_polarity = !clk_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
} }
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A); clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity; clear_polarity = !clear_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
} }
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A); preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity; preset_polarity = !preset_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
@ -259,14 +259,14 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
} }
} }
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig); cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig); cell->setPort(ID::Y, iqn_sig);
cell = module->addCell(NEW_ID, ""); cell = module->addCell(NEW_ID, "");
cell->setPort("\\D", data_sig); cell->setPort(ID::D, data_sig);
cell->setPort("\\Q", iq_sig); cell->setPort(ID::Q, iq_sig);
cell->setPort("\\C", clk_sig); cell->setPort(ID::C, clk_sig);
if (clear_sig.size() == 0 && preset_sig.size() == 0) { if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N'); cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@ -274,18 +274,18 @@ static void create_ff(RTLIL::Module *module, LibertyAst *node)
if (clear_sig.size() == 1 && preset_sig.size() == 0) { if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort("\\R", clear_sig); cell->setPort(ID::R, clear_sig);
} }
if (clear_sig.size() == 0 && preset_sig.size() == 1) { if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N'); cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
cell->setPort("\\R", preset_sig); cell->setPort(ID::R, preset_sig);
} }
if (clear_sig.size() == 1 && preset_sig.size() == 1) { if (clear_sig.size() == 1 && preset_sig.size() == 1) {
cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N'); cell->type = stringf("$_DFFSR_%c%c%c_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort(ID::S, preset_sig); cell->setPort(ID::S, preset_sig);
cell->setPort("\\R", clear_sig); cell->setPort(ID::R, clear_sig);
} }
log_assert(!cell->type.empty()); log_assert(!cell->type.empty());
@ -324,17 +324,17 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
rerun_invert_rollback = false; rerun_invert_rollback = false;
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == enable_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
enable_sig = it.second->getPort(ID::A); enable_sig = it.second->getPort(ID::A);
enable_polarity = !enable_polarity; enable_polarity = !enable_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
} }
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == clear_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A); clear_sig = it.second->getPort(ID::A);
clear_polarity = !clear_polarity; clear_polarity = !clear_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
} }
if (it.second->type == "$_NOT_" && it.second->getPort(ID::Y) == preset_sig) { if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A); preset_sig = it.second->getPort(ID::A);
preset_polarity = !preset_polarity; preset_polarity = !preset_polarity;
rerun_invert_rollback = true; rerun_invert_rollback = true;
@ -342,7 +342,7 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
} }
} }
RTLIL::Cell *cell = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig); cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig); cell->setPort(ID::Y, iqn_sig);
@ -353,7 +353,7 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (clear_polarity == true || clear_polarity != enable_polarity) if (clear_polarity == true || clear_polarity != enable_polarity)
{ {
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig); inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID)); inv->setPort(ID::Y, module->addWire(NEW_ID));
@ -363,12 +363,12 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
clear_enable = inv->getPort(ID::Y); clear_enable = inv->getPort(ID::Y);
} }
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_AND_"); RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig); data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative); data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_"); RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig); enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable); enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
@ -381,7 +381,7 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
if (preset_polarity == false || preset_polarity != enable_polarity) if (preset_polarity == false || preset_polarity != enable_polarity)
{ {
RTLIL::Cell *inv = module->addCell(NEW_ID, "$_NOT_"); RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig); inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID)); inv->setPort(ID::Y, module->addWire(NEW_ID));
@ -391,21 +391,21 @@ static bool create_latch(RTLIL::Module *module, LibertyAst *node, bool flag_igno
preset_enable = inv->getPort(ID::Y); preset_enable = inv->getPort(ID::Y);
} }
RTLIL::Cell *data_gate = module->addCell(NEW_ID, "$_OR_"); RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig); data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive); data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? "$_OR_" : "$_AND_"); RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig); enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable); enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID)); enable_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
} }
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N')); cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort("\\D", data_sig); cell->setPort(ID::D, data_sig);
cell->setPort("\\Q", iq_sig); cell->setPort(ID::Q, iq_sig);
cell->setPort("\\E", enable_sig); cell->setPort(ID::E, enable_sig);
return true; return true;
} }
@ -550,13 +550,13 @@ struct LibertyFrontend : public Frontend {
if (design->has(cell_name)) { if (design->has(cell_name)) {
Module *existing_mod = design->module(cell_name); Module *existing_mod = design->module(cell_name);
if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute("\\blackbox")) { if (!flag_nooverwrite && !flag_overwrite && !existing_mod->get_bool_attribute(ID::blackbox)) {
log_error("Re-definition of cell/module %s!\n", log_id(cell_name)); log_error("Re-definition of cell/module %s!\n", log_id(cell_name));
} else if (flag_nooverwrite) { } else if (flag_nooverwrite) {
log("Ignoring re-definition of module %s.\n", log_id(cell_name)); log("Ignoring re-definition of module %s.\n", log_id(cell_name));
continue; continue;
} else { } else {
log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute("\\blackbox") ? " blackbox" : "", log_id(cell_name)); log("Replacing existing%s module %s.\n", existing_mod->get_bool_attribute(ID::blackbox) ? " blackbox" : "", log_id(cell_name));
design->remove(existing_mod); design->remove(existing_mod);
} }
} }
@ -570,7 +570,7 @@ struct LibertyFrontend : public Frontend {
module->name = cell_name; module->name = cell_name;
if (flag_lib) if (flag_lib)
module->set_bool_attribute("\\blackbox"); module->set_bool_attribute(ID::blackbox);
for (auto &attr : attributes) for (auto &attr : attributes)
module->attributes[attr] = 1; module->attributes[attr] = 1;

96
frontends/verific/verific.cc
View file

@ -738,7 +738,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi
SigSpec dbits; SigSpec dbits;
for (auto cell : candidates) { for (auto cell : candidates) {
SigBit bit = sigmap(cell->getPort("\\D")); SigBit bit = sigmap(cell->getPort(ID::D));
dbits_db[bit].insert(cell); dbits_db[bit].insert(cell);
dbits.append(bit); dbits.append(bit);
} }
@ -764,7 +764,7 @@ void VerificImporter::merge_past_ffs_clock(pool<RTLIL::Cell*> &candidates, SigBi
if (verific_verbose) if (verific_verbose)
log(" replacing old ff %s on bit %d.\n", log_id(old_ff), i); log(" replacing old ff %s on bit %d.\n", log_id(old_ff), i);
SigBit old_q = old_ff->getPort("\\Q"); SigBit old_q = old_ff->getPort(ID::Q);
SigBit new_q = sig_q[i]; SigBit new_q = sig_q[i];
sigmap.add(old_q, new_q); sigmap.add(old_q, new_q);
@ -783,8 +783,8 @@ void VerificImporter::merge_past_ffs(pool<RTLIL::Cell*> &candidates)
for (auto cell : candidates) for (auto cell : candidates)
{ {
SigBit clock = cell->getPort("\\CLK"); SigBit clock = cell->getPort(ID::CLK);
bool clock_pol = cell->getParam("\\CLK_POLARITY").as_bool(); bool clock_pol = cell->getParam(ID::CLK_POLARITY).as_bool();
database[make_pair(clock, int(clock_pol))].insert(cell); database[make_pair(clock, int(clock_pol))].insert(cell);
} }
@ -822,7 +822,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (is_blackbox(nl)) { if (is_blackbox(nl)) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
module->set_bool_attribute("\\blackbox"); module->set_bool_attribute(ID::blackbox);
} else { } else {
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
@ -952,17 +952,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
ascii_initdata++; ascii_initdata++;
} }
if (initval_valid) { if (initval_valid) {
RTLIL::Cell *cell = module->addCell(new_verific_id(net), "$meminit"); RTLIL::Cell *cell = module->addCell(new_verific_id(net), ID($meminit));
cell->parameters["\\WORDS"] = 1; cell->parameters[ID::WORDS] = 1;
if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound()) if (net->GetOrigTypeRange()->LeftRangeBound() < net->GetOrigTypeRange()->RightRangeBound())
cell->setPort("\\ADDR", word_idx); cell->setPort(ID::ADDR, word_idx);
else else
cell->setPort("\\ADDR", memory->size - word_idx - 1); cell->setPort(ID::ADDR, memory->size - word_idx - 1);
cell->setPort("\\DATA", initval); cell->setPort(ID::DATA, initval);
cell->parameters["\\MEMID"] = RTLIL::Const(memory->name.str()); cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
cell->parameters["\\ABITS"] = 32; cell->parameters[ID::ABITS] = 32;
cell->parameters["\\WIDTH"] = memory->width; cell->parameters[ID::WIDTH] = memory->width;
cell->parameters["\\PRIORITY"] = RTLIL::Const(autoidx-1); cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
} }
} }
} }
@ -1079,7 +1079,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} }
if (initval_valid) if (initval_valid)
wire->attributes["\\init"] = initval; wire->attributes[ID::init] = initval;
} }
else else
{ {
@ -1133,8 +1133,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
SigBit bit = net_map_at(it.first); SigBit bit = net_map_at(it.first);
log_assert(bit.wire); log_assert(bit.wire);
if (bit.wire->attributes.count("\\init")) if (bit.wire->attributes.count(ID::init))
initval = bit.wire->attributes.at("\\init"); initval = bit.wire->attributes.at(ID::init);
while (GetSize(initval) < GetSize(bit.wire)) while (GetSize(initval) < GetSize(bit.wire))
initval.bits.push_back(State::Sx); initval.bits.push_back(State::Sx);
@ -1144,7 +1144,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
if (it.second == '1') if (it.second == '1')
initval.bits.at(bit.offset) = State::S1; initval.bits.at(bit.offset) = State::S1;
bit.wire->attributes["\\init"] = initval; bit.wire->attributes[ID::init] = initval;
} }
for (auto net : anyconst_nets) for (auto net : anyconst_nets)
@ -1212,17 +1212,17 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width); RTLIL::SigSpec data = operatorOutput(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memrd"); RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memrd));
cell->parameters["\\MEMID"] = memory->name.str(); cell->parameters[ID::MEMID] = memory->name.str();
cell->parameters["\\CLK_ENABLE"] = false; cell->parameters[ID::CLK_ENABLE] = false;
cell->parameters["\\CLK_POLARITY"] = true; cell->parameters[ID::CLK_POLARITY] = true;
cell->parameters["\\TRANSPARENT"] = false; cell->parameters[ID::TRANSPARENT] = false;
cell->parameters["\\ABITS"] = GetSize(addr); cell->parameters[ID::ABITS] = GetSize(addr);
cell->parameters["\\WIDTH"] = GetSize(data); cell->parameters[ID::WIDTH] = GetSize(data);
cell->setPort("\\CLK", RTLIL::State::Sx); cell->setPort(ID::CLK, RTLIL::State::Sx);
cell->setPort("\\EN", RTLIL::State::Sx); cell->setPort(ID::EN, RTLIL::State::Sx);
cell->setPort("\\ADDR", addr); cell->setPort(ID::ADDR, addr);
cell->setPort("\\DATA", data); cell->setPort(ID::DATA, data);
} }
continue; continue;
} }
@ -1242,21 +1242,21 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width); RTLIL::SigSpec data = operatorInput2(inst).extract(i * memory->width, memory->width);
RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name : RTLIL::Cell *cell = module->addCell(numchunks == 1 ? inst_name :
RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), "$memwr"); RTLIL::IdString(stringf("%s_%d", inst_name.c_str(), i)), ID($memwr));
cell->parameters["\\MEMID"] = memory->name.str(); cell->parameters[ID::MEMID] = memory->name.str();
cell->parameters["\\CLK_ENABLE"] = false; cell->parameters[ID::CLK_ENABLE] = false;
cell->parameters["\\CLK_POLARITY"] = true; cell->parameters[ID::CLK_POLARITY] = true;
cell->parameters["\\PRIORITY"] = 0; cell->parameters[ID::PRIORITY] = 0;
cell->parameters["\\ABITS"] = GetSize(addr); cell->parameters[ID::ABITS] = GetSize(addr);
cell->parameters["\\WIDTH"] = GetSize(data); cell->parameters[ID::WIDTH] = GetSize(data);
cell->setPort("\\EN", RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data))); cell->setPort(ID::EN, RTLIL::SigSpec(net_map_at(inst->GetControl())).repeat(GetSize(data)));
cell->setPort("\\CLK", RTLIL::State::S0); cell->setPort(ID::CLK, RTLIL::State::S0);
cell->setPort("\\ADDR", addr); cell->setPort(ID::ADDR, addr);
cell->setPort("\\DATA", data); cell->setPort(ID::DATA, data);
if (inst->Type() == OPER_CLOCKED_WRITE_PORT) { if (inst->Type() == OPER_CLOCKED_WRITE_PORT) {
cell->parameters["\\CLK_ENABLE"] = true; cell->parameters[ID::CLK_ENABLE] = true;
cell->setPort("\\CLK", net_map_at(inst->GetClock())); cell->setPort(ID::CLK, net_map_at(inst->GetClock()));
} }
} }
continue; continue;
@ -1431,7 +1431,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Cell *cell = module->addCell(inst_name, inst_type); RTLIL::Cell *cell = module->addCell(inst_name, inst_type);
if (inst->IsPrimitive() && mode_keep) if (inst->IsPrimitive() && mode_keep)
cell->attributes["\\keep"] = 1; cell->attributes[ID::keep] = 1;
dict<IdString, vector<SigBit>> cell_port_conns; dict<IdString, vector<SigBit>> cell_port_conns;
@ -1514,10 +1514,10 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (!wire->attributes.count("\\init")) if (!wire->attributes.count(ID::init))
continue; continue;
Const &initval = wire->attributes.at("\\init"); Const &initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval); i++) for (int i = 0; i < GetSize(initval); i++)
{ {
if (initval[i] != State::S0 && initval[i] != State::S1) if (initval[i] != State::S0 && initval[i] != State::S1)
@ -1528,7 +1528,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
} }
if (initval.is_fully_undef()) if (initval.is_fully_undef())
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
} }
} }
} }
@ -1652,10 +1652,10 @@ Cell *VerificClocking::addDff(IdString name, SigSpec sig_d, SigSpec sig_q, Const
if (GetSize(init_value) != 0) { if (GetSize(init_value) != 0) {
log_assert(GetSize(sig_q) == GetSize(init_value)); log_assert(GetSize(sig_q) == GetSize(init_value));
if (sig_q.is_wire()) { if (sig_q.is_wire()) {
sig_q.as_wire()->attributes["\\init"] = init_value; sig_q.as_wire()->attributes[ID::init] = init_value;
} else { } else {
Wire *w = module->addWire(NEW_ID, GetSize(sig_q)); Wire *w = module->addWire(NEW_ID, GetSize(sig_q));
w->attributes["\\init"] = init_value; w->attributes[ID::init] = init_value;
module->connect(sig_q, w); module->connect(sig_q, w);
sig_q = w; sig_q = w;
} }

10
frontends/verilog/verilog_parser.y
View file

@ -1544,7 +1544,7 @@ wire_name_and_opt_assign:
fcall->str = "\\$allconst"; fcall->str = "\\$allconst";
if (attr_allseq) if (attr_allseq)
fcall->str = "\\$allseq"; fcall->str = "\\$allseq";
fcall->attributes["\\reg"] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str)); fcall->attributes[ID::reg] = AstNode::mkconst_str(RTLIL::unescape_id(wire->str));
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall)); ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, fcall));
} }
} | } |
@ -1839,7 +1839,7 @@ cell_port:
attr TOK_WILDCARD_CONNECT { attr TOK_WILDCARD_CONNECT {
if (!sv_mode) if (!sv_mode)
frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode.");
astbuf2->attributes[ID(wildcard_port_conns)] = AstNode::mkconst_int(1, false); astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false);
}; };
always_comb_or_latch: always_comb_or_latch:
@ -1863,7 +1863,7 @@ always_stmt:
AstNode *node = new AstNode(AST_ALWAYS); AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1); append_attr(node, $1);
if ($2) if ($2)
node->attributes[ID(always_ff)] = AstNode::mkconst_int(1, false); node->attributes[ID::always_ff] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
ast_stack.push_back(node); ast_stack.push_back(node);
} always_cond { } always_cond {
@ -1883,9 +1883,9 @@ always_stmt:
AstNode *node = new AstNode(AST_ALWAYS); AstNode *node = new AstNode(AST_ALWAYS);
append_attr(node, $1); append_attr(node, $1);
if ($2) if ($2)
node->attributes[ID(always_latch)] = AstNode::mkconst_int(1, false); node->attributes[ID::always_latch] = AstNode::mkconst_int(1, false);
else else
node->attributes[ID(always_comb)] = AstNode::mkconst_int(1, false); node->attributes[ID::always_comb] = AstNode::mkconst_int(1, false);
ast_stack.back()->children.push_back(node); ast_stack.back()->children.push_back(node);
ast_stack.push_back(node); ast_stack.push_back(node);
AstNode *block = new AstNode(AST_BLOCK); AstNode *block = new AstNode(AST_BLOCK);

30
kernel/cellaigs.cc
View file

@ -268,9 +268,9 @@ Aig::Aig(Cell *cell)
cell->parameters.sort(); cell->parameters.sort();
for (auto p : cell->parameters) for (auto p : cell->parameters)
{ {
if (p.first == ID(A_WIDTH) && mkname_a_signed) { if (p.first == ID::A_WIDTH && mkname_a_signed) {
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
} else if (p.first == ID(B_WIDTH) && mkname_b_signed) { } else if (p.first == ID::B_WIDTH && mkname_b_signed) {
name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U'); name = mkname_last + stringf(":%d%c", p.second.as_int(), mkname_is_signed ? 'S' : 'U');
} else { } else {
mkname_last = name; mkname_last = name;
@ -280,11 +280,11 @@ Aig::Aig(Cell *cell)
mkname_a_signed = false; mkname_a_signed = false;
mkname_b_signed = false; mkname_b_signed = false;
mkname_is_signed = false; mkname_is_signed = false;
if (p.first == ID(A_SIGNED)) { if (p.first == ID::A_SIGNED) {
mkname_a_signed = true; mkname_a_signed = true;
mkname_is_signed = p.second.as_bool(); mkname_is_signed = p.second.as_bool();
} }
if (p.first == ID(B_SIGNED)) { if (p.first == ID::B_SIGNED) {
mkname_b_signed = true; mkname_b_signed = true;
mkname_is_signed = p.second.as_bool(); mkname_is_signed = p.second.as_bool();
} }
@ -320,7 +320,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($mux), ID($_MUX_))) if (cell->type.in(ID($mux), ID($_MUX_)))
{ {
int S = mk.inport(ID(S)); int S = mk.inport(ID::S);
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) { for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
int A = mk.inport(ID::A, i); int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i); int B = mk.inport(ID::B, i);
@ -390,8 +390,8 @@ Aig::Aig(Cell *cell)
int width = GetSize(cell->getPort(ID::Y)); int width = GetSize(cell->getPort(ID::Y));
vector<int> A = mk.inport_vec(ID::A, width); vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width); vector<int> B = mk.inport_vec(ID::B, width);
int carry = mk.inport(ID(CI)); int carry = mk.inport(ID::CI);
int binv = mk.inport(ID(BI)); int binv = mk.inport(ID::BI);
for (auto &n : B) for (auto &n : B)
n = mk.xor_gate(n, binv); n = mk.xor_gate(n, binv);
vector<int> X(width), CO(width); vector<int> X(width), CO(width);
@ -399,8 +399,8 @@ Aig::Aig(Cell *cell)
for (int i = 0; i < width; i++) for (int i = 0; i < width; i++)
X[i] = mk.xor_gate(A[i], B[i]); X[i] = mk.xor_gate(A[i], B[i]);
mk.outport_vec(Y, ID::Y); mk.outport_vec(Y, ID::Y);
mk.outport_vec(X, ID(X)); mk.outport_vec(X, ID::X);
mk.outport_vec(CO, ID(CO)); mk.outport_vec(CO, ID::CO);
goto optimize; goto optimize;
} }
@ -422,7 +422,7 @@ Aig::Aig(Cell *cell)
{ {
int A = mk.inport(ID::A); int A = mk.inport(ID::A);
int B = mk.inport(ID::B); int B = mk.inport(ID::B);
int C = mk.inport(ID(C)); int C = mk.inport(ID::C);
int Y = mk.nor_gate(mk.and_gate(A, B), C); int Y = mk.nor_gate(mk.and_gate(A, B), C);
mk.outport(Y, ID::Y); mk.outport(Y, ID::Y);
goto optimize; goto optimize;
@ -432,7 +432,7 @@ Aig::Aig(Cell *cell)
{ {
int A = mk.inport(ID::A); int A = mk.inport(ID::A);
int B = mk.inport(ID::B); int B = mk.inport(ID::B);
int C = mk.inport(ID(C)); int C = mk.inport(ID::C);
int Y = mk.nand_gate(mk.or_gate(A, B), C); int Y = mk.nand_gate(mk.or_gate(A, B), C);
mk.outport(Y, ID::Y); mk.outport(Y, ID::Y);
goto optimize; goto optimize;
@ -442,8 +442,8 @@ Aig::Aig(Cell *cell)
{ {
int A = mk.inport(ID::A); int A = mk.inport(ID::A);
int B = mk.inport(ID::B); int B = mk.inport(ID::B);
int C = mk.inport(ID(C)); int C = mk.inport(ID::C);
int D = mk.inport(ID(D)); int D = mk.inport(ID::D);
int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D)); int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
mk.outport(Y, ID::Y); mk.outport(Y, ID::Y);
goto optimize; goto optimize;
@ -453,8 +453,8 @@ Aig::Aig(Cell *cell)
{ {
int A = mk.inport(ID::A); int A = mk.inport(ID::A);
int B = mk.inport(ID::B); int B = mk.inport(ID::B);
int C = mk.inport(ID(C)); int C = mk.inport(ID::C);
int D = mk.inport(ID(D)); int D = mk.inport(ID::D);
int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D)); int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
mk.outport(Y, ID::Y); mk.outport(Y, ID::Y);
goto optimize; goto optimize;

84
kernel/celledges.cc
View file

@ -24,29 +24,25 @@ PRIVATE_NAMESPACE_BEGIN
void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(A));
int y_width = GetSize(cell->getPort(Y));
for (int i = 0; i < y_width; i++) for (int i = 0; i < y_width; i++)
{ {
if (i < a_width) if (i < a_width)
db->add_edge(cell, A, i, Y, i, -1); db->add_edge(cell, ID::A, i, ID::Y, i, -1);
else if (is_signed && a_width > 0) else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i, -1); db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
} }
} }
void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(A)); int y_width = GetSize(cell->getPort(ID::Y));
int b_width = GetSize(cell->getPort(B));
int y_width = GetSize(cell->getPort(Y));
if (cell->type == ID($and) && !is_signed) { if (cell->type == ID($and) && !is_signed) {
if (a_width > b_width) if (a_width > b_width)
@ -58,41 +54,37 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
for (int i = 0; i < y_width; i++) for (int i = 0; i < y_width; i++)
{ {
if (i < a_width) if (i < a_width)
db->add_edge(cell, A, i, Y, i, -1); db->add_edge(cell, ID::A, i, ID::Y, i, -1);
else if (is_signed && a_width > 0) else if (is_signed && a_width > 0)
db->add_edge(cell, A, a_width-1, Y, i, -1); db->add_edge(cell, ID::A, a_width-1, ID::Y, i, -1);
if (i < b_width) if (i < b_width)
db->add_edge(cell, B, i, Y, i, -1); db->add_edge(cell, ID::B, i, ID::Y, i, -1);
else if (is_signed && b_width > 0) else if (is_signed && b_width > 0)
db->add_edge(cell, B, b_width-1, Y, i, -1); db->add_edge(cell, ID::B, b_width-1, ID::Y, i, -1);
} }
} }
void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, Y = ID::Y; bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(A));
int y_width = GetSize(cell->getPort(Y));
if (is_signed && a_width == 1) if (is_signed && a_width == 1)
y_width = std::min(y_width, 1); y_width = std::min(y_width, 1);
for (int i = 0; i < y_width; i++) for (int i = 0; i < y_width; i++)
for (int k = 0; k <= i && k < a_width; k++) for (int k = 0; k <= i && k < a_width; k++)
db->add_edge(cell, A, k, Y, i, -1); db->add_edge(cell, ID::A, k, ID::Y, i, -1);
} }
void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, B = ID::B, Y = ID::Y; bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(A)); int y_width = GetSize(cell->getPort(ID::Y));
int b_width = GetSize(cell->getPort(B));
int y_width = GetSize(cell->getPort(Y));
if (!is_signed && cell->type != ID($sub)) { if (!is_signed && cell->type != ID($sub)) {
int ab_width = std::max(a_width, b_width); int ab_width = std::max(a_width, b_width);
@ -104,55 +96,49 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
for (int k = 0; k <= i; k++) for (int k = 0; k <= i; k++)
{ {
if (k < a_width) if (k < a_width)
db->add_edge(cell, A, k, Y, i, -1); db->add_edge(cell, ID::A, k, ID::Y, i, -1);
if (k < b_width) if (k < b_width)
db->add_edge(cell, B, k, Y, i, -1); db->add_edge(cell, ID::B, k, ID::Y, i, -1);
} }
} }
} }
void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, Y = ID::Y; int a_width = GetSize(cell->getPort(ID::A));
int a_width = GetSize(cell->getPort(A));
for (int i = 0; i < a_width; i++) for (int i = 0; i < a_width; i++)
db->add_edge(cell, A, i, Y, 0, -1); db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
} }
void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, B = ID::B, Y = ID::Y; int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(A));
int b_width = GetSize(cell->getPort(B));
for (int i = 0; i < a_width; i++) for (int i = 0; i < a_width; i++)
db->add_edge(cell, A, i, Y, 0, -1); db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
for (int i = 0; i < b_width; i++) for (int i = 0; i < b_width; i++)
db->add_edge(cell, B, i, Y, 0, -1); db->add_edge(cell, ID::B, i, ID::Y, 0, -1);
} }
void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell) void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{ {
IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y; int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(A)); int s_width = GetSize(cell->getPort(ID::S));
int b_width = GetSize(cell->getPort(B));
int s_width = GetSize(cell->getPort(S));
for (int i = 0; i < a_width; i++) for (int i = 0; i < a_width; i++)
{ {
db->add_edge(cell, A, i, Y, i, -1); db->add_edge(cell, ID::A, i, ID::Y, i, -1);
for (int k = i; k < b_width; k += a_width) for (int k = i; k < b_width; k += a_width)
db->add_edge(cell, B, k, Y, i, -1); db->add_edge(cell, ID::B, k, ID::Y, i, -1);
for (int k = 0; k < s_width; k++) for (int k = 0; k < s_width; k++)
db->add_edge(cell, S, k, Y, i, -1); db->add_edge(cell, ID::S, k, ID::Y, i, -1);
} }
} }

175
kernel/celltypes.h
View file

@ -84,26 +84,22 @@ struct CellTypes
{ {
setup_internals_eval(); setup_internals_eval();
IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y; setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT);
IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST);
setup_type(ID($tribuf), {A, EN}, {Y}, true); setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
setup_type(ID($assert), {A, EN}, pool<RTLIL::IdString>(), true); setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
setup_type(ID($assume), {A, EN}, pool<RTLIL::IdString>(), true); setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
setup_type(ID($live), {A, EN}, pool<RTLIL::IdString>(), true); setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
setup_type(ID($fair), {A, EN}, pool<RTLIL::IdString>(), true); setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
setup_type(ID($cover), {A, EN}, pool<RTLIL::IdString>(), true); setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
setup_type(ID($initstate), pool<RTLIL::IdString>(), {Y}, true); setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
setup_type(ID($anyconst), pool<RTLIL::IdString>(), {Y}, true); setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
setup_type(ID($anyseq), pool<RTLIL::IdString>(), {Y}, true); setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
setup_type(ID($allconst), pool<RTLIL::IdString>(), {Y}, true); setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($allseq), pool<RTLIL::IdString>(), {Y}, true); setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
setup_type(ID($equiv), {A, B}, {Y}, true); setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
setup_type(ID($specify2), {EN, SRC, DST}, pool<RTLIL::IdString>(), true); setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
setup_type(ID($specify3), {EN, SRC, DST, DAT}, pool<RTLIL::IdString>(), true);
setup_type(ID($specrule), {EN_SRC, EN_DST, SRC, DST}, pool<RTLIL::IdString>(), true);
} }
void setup_internals_eval() void setup_internals_eval()
@ -121,134 +117,109 @@ struct CellTypes
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow),
ID($logic_and), ID($logic_or), ID($concat), ID($macc) ID($logic_and), ID($logic_or), ID($concat), ID($macc)
}; };
IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y;
IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X);
IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN);
for (auto type : unary_ops) for (auto type : unary_ops)
setup_type(type, {A}, {Y}, true); setup_type(type, {ID::A}, {ID::Y}, true);
for (auto type : binary_ops) for (auto type : binary_ops)
setup_type(type, {A, B}, {Y}, true); setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)})) for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
setup_type(type, {A, B, S}, {Y}, true); setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($lcu), {P, G, CI}, {CO}, true); setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
setup_type(ID($alu), {A, B, CI, BI}, {X, Y, CO}, true); setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
setup_type(ID($fa), {A, B, C}, {X, Y}, true); setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
} }
void setup_internals_ff() void setup_internals_ff()
{ {
IdString SET = ID(SET), CLR = ID(CLR), CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
IdString Q = ID(Q), D = ID(D); setup_type(ID($ff), {ID::D}, {ID::Q});
setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
setup_type(ID($sr), {SET, CLR}, {Q}); setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
setup_type(ID($ff), {D}, {Q}); setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($dff), {CLK, D}, {Q}); setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
setup_type(ID($dffe), {CLK, EN, D}, {Q}); setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
setup_type(ID($dffsr), {CLK, SET, CLR, D}, {Q}); setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($adff), {CLK, ARST, D}, {Q});
setup_type(ID($dlatch), {EN, D}, {Q});
setup_type(ID($dlatchsr), {EN, SET, CLR, D}, {Q});
} }
void setup_internals_mem() void setup_internals_mem()
{ {
setup_internals_ff(); setup_internals_ff();
IdString CLK = ID(CLK), ARST = ID(ARST), EN = ID(EN); setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
IdString ADDR = ID(ADDR), DATA = ID(DATA), RD_EN = ID(RD_EN); setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
IdString RD_CLK = ID(RD_CLK), RD_ADDR = ID(RD_ADDR), WR_CLK = ID(WR_CLK), WR_EN = ID(WR_EN); setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
IdString WR_ADDR = ID(WR_ADDR), WR_DATA = ID(WR_DATA), RD_DATA = ID(RD_DATA); setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
IdString CTRL_IN = ID(CTRL_IN), CTRL_OUT = ID(CTRL_OUT);
setup_type(ID($memrd), {CLK, EN, ADDR}, {DATA}); setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
setup_type(ID($memwr), {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
setup_type(ID($meminit), {ADDR, DATA}, pool<RTLIL::IdString>());
setup_type(ID($mem), {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
setup_type(ID($fsm), {CLK, ARST, CTRL_IN}, {CTRL_OUT});
} }
void setup_stdcells() void setup_stdcells()
{ {
setup_stdcells_eval(); setup_stdcells_eval();
IdString A = ID::A, E = ID(E), Y = ID::Y; setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
setup_type(ID($_TBUF_), {A, E}, {Y}, true);
} }
void setup_stdcells_eval() void setup_stdcells_eval()
{ {
IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D); setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H); setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L); setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P); setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V); setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
IdString Y = ID::Y; setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_BUF_), {A}, {Y}, true); setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NOT_), {A}, {Y}, true); setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_AND_), {A, B}, {Y}, true); setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NAND_), {A, B}, {Y}, true); setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_OR_), {A, B}, {Y}, true); setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_NOR_), {A, B}, {Y}, true); setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
setup_type(ID($_XOR_), {A, B}, {Y}, true); setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
setup_type(ID($_XNOR_), {A, B}, {Y}, true); setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
setup_type(ID($_ANDNOT_), {A, B}, {Y}, true); setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_ORNOT_), {A, B}, {Y}, true); setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_MUX_), {A, B, S}, {Y}, true); setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_NMUX_), {A, B, S}, {Y}, true); setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_MUX4_), {A, B, C, D, S, T}, {Y}, true);
setup_type(ID($_MUX8_), {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true);
setup_type(ID($_MUX16_), {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true);
setup_type(ID($_AOI3_), {A, B, C}, {Y}, true);
setup_type(ID($_OAI3_), {A, B, C}, {Y}, true);
setup_type(ID($_AOI4_), {A, B, C, D}, {Y}, true);
setup_type(ID($_OAI4_), {A, B, C, D}, {Y}, true);
} }
void setup_stdcells_mem() void setup_stdcells_mem()
{ {
IdString S = ID(S), R = ID(R), C = ID(C);
IdString D = ID(D), Q = ID(Q), E = ID(E);
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'}; std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
for (auto c1 : list_np) for (auto c1 : list_np)
for (auto c2 : list_np) for (auto c2 : list_np)
setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q}); setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
setup_type(ID($_FF_), {D}, {Q}); setup_type(ID($_FF_), {ID::D}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q}); setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
for (auto c2 : list_np) for (auto c2 : list_np)
setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q}); setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
for (auto c2 : list_np) for (auto c2 : list_np)
for (auto c3 : list_01) for (auto c3 : list_01)
setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q}); setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
for (auto c2 : list_np) for (auto c2 : list_np)
for (auto c3 : list_np) for (auto c3 : list_np)
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q}); setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q}); setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
for (auto c1 : list_np) for (auto c1 : list_np)
for (auto c2 : list_np) for (auto c2 : list_np)
for (auto c3 : list_np) for (auto c3 : list_np)
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q}); setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
} }
void clear() void clear()
@ -300,7 +271,7 @@ struct CellTypes
signed1 = false, signed2 = false; signed1 = false, signed2 = false;
} }
#define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len); #define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
HANDLE_CELL_TYPE(not) HANDLE_CELL_TYPE(not)
HANDLE_CELL_TYPE(and) HANDLE_CELL_TYPE(and)
HANDLE_CELL_TYPE(or) HANDLE_CELL_TYPE(or)
@ -371,8 +342,8 @@ struct CellTypes
{ {
if (cell->type == ID($slice)) { if (cell->type == ID($slice)) {
RTLIL::Const ret; RTLIL::Const ret;
int width = cell->parameters.at(ID(Y_WIDTH)).as_int(); int width = cell->parameters.at(ID::Y_WIDTH).as_int();
int offset = cell->parameters.at(ID(OFFSET)).as_int(); int offset = cell->parameters.at(ID::OFFSET).as_int();
ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width); ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
return ret; return ret;
} }
@ -385,9 +356,9 @@ struct CellTypes
if (cell->type == ID($lut)) if (cell->type == ID($lut))
{ {
int width = cell->parameters.at(ID(WIDTH)).as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::State> t = cell->parameters.at(ID(LUT)).bits; std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
while (GetSize(t) < (1 << width)) while (GetSize(t) < (1 << width))
t.push_back(State::S0); t.push_back(State::S0);
t.resize(1 << width); t.resize(1 << width);
@ -411,9 +382,9 @@ struct CellTypes
if (cell->type == ID($sop)) if (cell->type == ID($sop))
{ {
int width = cell->parameters.at(ID(WIDTH)).as_int(); int width = cell->parameters.at(ID::WIDTH).as_int();
int depth = cell->parameters.at(ID(DEPTH)).as_int(); int depth = cell->parameters.at(ID::DEPTH).as_int();
std::vector<RTLIL::State> t = cell->parameters.at(ID(TABLE)).bits; std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
while (GetSize(t) < width*depth*2) while (GetSize(t) < width*depth*2)
t.push_back(State::S0); t.push_back(State::S0);
@ -447,9 +418,9 @@ struct CellTypes
return default_ret; return default_ret;
} }
bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
int result_len = cell->parameters.count(ID(Y_WIDTH)) > 0 ? cell->parameters[ID(Y_WIDTH)].as_int() : -1; int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp); return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
} }

36
kernel/consteval.h
View file

@ -91,10 +91,10 @@ struct ConstEval
{ {
if (cell->type == ID($lcu)) if (cell->type == ID($lcu))
{ {
RTLIL::SigSpec sig_p = cell->getPort(ID(P)); RTLIL::SigSpec sig_p = cell->getPort(ID::P);
RTLIL::SigSpec sig_g = cell->getPort(ID(G)); RTLIL::SigSpec sig_g = cell->getPort(ID::G);
RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID(CO)))); RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
if (sig_co.is_fully_const()) if (sig_co.is_fully_const())
return true; return true;
@ -133,8 +133,8 @@ struct ConstEval
if (sig_y.is_fully_const()) if (sig_y.is_fully_const())
return true; return true;
if (cell->hasPort(ID(S))) { if (cell->hasPort(ID::S)) {
sig_s = cell->getPort(ID(S)); sig_s = cell->getPort(ID::S);
if (!eval(sig_s, undef, cell)) if (!eval(sig_s, undef, cell))
return false; return false;
} }
@ -200,8 +200,8 @@ struct ConstEval
} }
else if (cell->type == ID($fa)) else if (cell->type == ID($fa))
{ {
RTLIL::SigSpec sig_c = cell->getPort(ID(C)); RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_x = cell->getPort(ID(X)); RTLIL::SigSpec sig_x = cell->getPort(ID::X);
int width = GetSize(sig_c); int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell)) if (!eval(sig_a, undef, cell))
@ -229,11 +229,11 @@ struct ConstEval
} }
else if (cell->type == ID($alu)) else if (cell->type == ID($alu))
{ {
bool signed_a = cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool(); bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
bool signed_b = cell->parameters.count(ID(B_SIGNED)) > 0 && cell->parameters[ID(B_SIGNED)].as_bool(); bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
if (!eval(sig_a, undef, cell)) if (!eval(sig_a, undef, cell))
return false; return false;
@ -247,8 +247,8 @@ struct ConstEval
if (!eval(sig_bi, undef, cell)) if (!eval(sig_bi, undef, cell))
return false; return false;
RTLIL::SigSpec sig_x = cell->getPort(ID(X)); RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend_u0(GetSize(sig_y), signed_a); sig_a.extend_u0(GetSize(sig_y), signed_a);
@ -309,10 +309,10 @@ struct ConstEval
RTLIL::SigSpec sig_c, sig_d; RTLIL::SigSpec sig_c, sig_d;
if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) { if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
if (cell->hasPort(ID(C))) if (cell->hasPort(ID::C))
sig_c = cell->getPort(ID(C)); sig_c = cell->getPort(ID::C);
if (cell->hasPort(ID(D))) if (cell->hasPort(ID::D))
sig_d = cell->getPort(ID(D)); sig_d = cell->getPort(ID::D);
} }
if (sig_a.size() > 0 && !eval(sig_a, undef, cell)) if (sig_a.size() > 0 && !eval(sig_a, undef, cell))

200
kernel/constids.inc
View file

@ -1,27 +1,213 @@
X(A) X(A)
X(B) X(abc9_box)
X(S) X(abc9_box_id)
X(Y) X(abc9_box_seq)
X(keep) X(abc9_carry)
X(src) X(abc9_flop)
X(whitebox) X(abc9_holes)
X(blackbox) X(abc9_init)
X(abc9_lut)
X(abc9_mergeability)
X(abc9_scc)
X(abc9_scc_id)
X(abcgroup)
X(ABITS)
X(ADDR)
X(allconst) X(allconst)
X(allseq) X(allseq)
X(always_comb)
X(always_ff)
X(always_latch)
X(anyconst) X(anyconst)
X(anyseq) X(anyseq)
X(ARST)
X(ARST_POLARITY)
X(ARST_VALUE)
X(A_SIGNED)
X(A_WIDTH)
X(B)
X(BI)
X(blackbox)
X(B_SIGNED)
X(B_WIDTH)
X(C)
X(cells_not_processed)
X(CFG_ABITS)
X(CFG_DBITS)
X(CFG_INIT)
X(CI)
X(CLK)
X(clkbuf_driver)
X(clkbuf_inhibit)
X(clkbuf_inv)
X(clkbuf_sink)
X(CLK_ENABLE)
X(CLK_POLARITY)
X(CLR)
X(CLR_POLARITY)
X(CO)
X(CONFIG)
X(CONFIG_WIDTH)
X(CTRL_IN)
X(CTRL_IN_WIDTH)
X(CTRL_OUT)
X(CTRL_OUT_WIDTH)
X(D)
X(DAT)
X(DATA)
X(DAT_DST_PEN)
X(DAT_DST_POL)
X(defaultvalue) X(defaultvalue)
X(DELAY)
X(DEPTH)
X(DST)
X(DST_EN)
X(DST_PEN)
X(DST_POL)
X(DST_WIDTH)
X(dynports)
X(E)
X(EDGE_EN)
X(EDGE_POL)
X(EN)
X(EN_DST)
X(EN_POLARITY)
X(EN_SRC)
X(equiv_merged)
X(equiv_region)
X(extract_order)
X(F)
X(fsm_encoding) X(fsm_encoding)
X(fsm_export)
X(FULL)
X(full_case) X(full_case)
X(G)
X(gclk) X(gclk)
X(gentb_clock)
X(gentb_constant)
X(gentb_skip)
X(H)
X(hdlname)
X(hierconn)
X(I)
X(INIT)
X(init)
X(initial_top) X(initial_top)
X(interface_modport)
X(interfaces_replaced_in_module)
X(interface_type)
X(invertible_pin)
X(iopad_external_pin)
X(is_interface) X(is_interface)
X(J)
X(K)
X(keep)
X(keep_hierarchy)
X(L)
X(lib_whitebox)
X(localparam)
X(LUT)
X(lut_keep)
X(M)
X(maximize)
X(mem2reg) X(mem2reg)
X(MEMID)
X(minimize)
X(module_not_derived)
X(N)
X(NAME)
X(noblackbox) X(noblackbox)
X(nolatches) X(nolatches)
X(nomem2init)
X(nomem2reg) X(nomem2reg)
X(nomeminit)
X(nosync) X(nosync)
X(O)
X(OFFSET)
X(onehot)
X(P)
X(parallel_case) X(parallel_case)
X(parameter)
X(PRIORITY)
X(Q)
X(qwp_position)
X(R)
X(RD_ADDR)
X(RD_CLK)
X(RD_CLK_ENABLE)
X(RD_CLK_POLARITY)
X(RD_DATA)
X(RD_EN)
X(RD_PORTS)
X(RD_TRANSPARENT)
X(reg)
X(S)
X(SET)
X(SET_POLARITY)
X(SIZE)
X(SRC)
X(src)
X(SRC_DST_PEN)
X(SRC_DST_POL)
X(SRC_EN)
X(SRC_PEN)
X(SRC_POL)
X(SRC_WIDTH)
X(STATE_BITS)
X(STATE_NUM)
X(STATE_NUM_LOG2)
X(STATE_RST)
X(STATE_TABLE)
X(submod)
X(S_WIDTH)
X(T)
X(TABLE)
X(techmap_autopurge)
X(_TECHMAP_BITS_CONNMAP_)
X(_TECHMAP_CELLTYPE_)
X(techmap_celltype)
X(techmap_maccmap)
X(_TECHMAP_REPLACE_)
X(techmap_simplemap)
X(_techmap_special_)
X(techmap_wrap)
X(T_FALL_MAX)
X(T_FALL_MIN)
X(T_FALL_TYP)
X(T_LIMIT)
X(T_LIMIT2)
X(T_LIMIT2_MAX)
X(T_LIMIT2_MIN)
X(T_LIMIT2_TYP)
X(T_LIMIT_MAX)
X(T_LIMIT_MIN)
X(T_LIMIT_TYP)
X(to_delete)
X(top) X(top)
X(TRANS_NUM)
X(TRANSPARENT)
X(TRANS_TABLE)
X(T_RISE_MAX)
X(T_RISE_MIN)
X(T_RISE_TYP)
X(TYPE)
X(U)
X(unique)
X(unused_bits)
X(V)
X(wand) X(wand)
X(whitebox)
X(WIDTH)
X(wildcard_port_conns)
X(wor) X(wor)
X(WORDS)
X(WR_ADDR)
X(WR_CLK)
X(WR_CLK_ENABLE)
X(WR_CLK_POLARITY)
X(WR_DATA)
X(WR_EN)
X(WR_PORTS)
X(X)
X(Y)
X(Y_WIDTH)

12
kernel/macc.h
View file

@ -104,11 +104,11 @@ struct Macc
ports.clear(); ports.clear();
bit_ports = cell->getPort(ID::B); bit_ports = cell->getPort(ID::B);
std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits; std::vector<RTLIL::State> config_bits = cell->getParam(ID::CONFIG).bits;
int config_cursor = 0; int config_cursor = 0;
#ifndef NDEBUG #ifndef NDEBUG
int config_width = cell->getParam(ID(CONFIG_WIDTH)).as_int(); int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int();
log_assert(GetSize(config_bits) >= config_width); log_assert(GetSize(config_bits) >= config_width);
#endif #endif
@ -193,10 +193,10 @@ struct Macc
cell->setPort(ID::A, port_a); cell->setPort(ID::A, port_a);
cell->setPort(ID::B, bit_ports); cell->setPort(ID::B, bit_ports);
cell->setParam(ID(CONFIG), config_bits); cell->setParam(ID::CONFIG, config_bits);
cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits)); cell->setParam(ID::CONFIG_WIDTH, GetSize(config_bits));
cell->setParam(ID(A_WIDTH), GetSize(port_a)); cell->setParam(ID::A_WIDTH, GetSize(port_a));
cell->setParam(ID(B_WIDTH), GetSize(bit_ports)); cell->setParam(ID::B_WIDTH, GetSize(bit_ports));
} }
bool eval(RTLIL::Const &result) const bool eval(RTLIL::Const &result) const

802
kernel/rtlil.cc
View file

File diff suppressed because it is too large Load diff

112
kernel/satgen.h
View file

@ -224,8 +224,8 @@ struct SatGen
void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false) void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
{ {
bool is_signed = forced_signed; bool is_signed = forced_signed;
if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0) if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)
is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
while (vec_a.size() < vec_b.size() || vec_a.size() < y_width) while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_b.size() < vec_a.size() || vec_b.size() < y_width) while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
@ -241,7 +241,7 @@ struct SatGen
void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false) void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
{ {
bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool()); bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());
while (vec_a.size() < vec_y.size()) while (vec_a.size() < vec_y.size())
vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE); vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
while (vec_y.size() < vec_a.size()) while (vec_y.size() < vec_a.size())
@ -397,8 +397,8 @@ struct SatGen
int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0); int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0); int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0); int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0); int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int yy = model_undef ? ez->literal() : y; int yy = model_undef ? ez->literal() : y;
@ -411,8 +411,8 @@ struct SatGen
{ {
int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0); int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0); int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0); int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0); int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0); int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
if (aoi_mode) if (aoi_mode)
@ -479,7 +479,7 @@ struct SatGen
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -492,7 +492,7 @@ struct SatGen
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b)); std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
@ -508,7 +508,7 @@ struct SatGen
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep); std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -524,7 +524,7 @@ struct SatGen
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep); std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
int maybe_a = ez->CONST_TRUE; int maybe_a = ez->CONST_TRUE;
@ -684,7 +684,7 @@ struct SatGen
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{ {
bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool(); bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
@ -774,7 +774,7 @@ struct SatGen
int extend_bit = ez->CONST_FALSE; int extend_bit = ez->CONST_FALSE;
if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = a.back(); extend_bit = a.back();
while (y.size() < a.size()) while (y.size() < a.size())
@ -792,10 +792,10 @@ struct SatGen
shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr)) if (cell->type == ID($sshr))
shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type.in(ID($shift), ID($shiftx))) if (cell->type.in(ID($shift), ID($shiftx)))
shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
ez->assume(ez->vec_eq(shifted_a, yy)); ez->assume(ez->vec_eq(shifted_a, yy));
@ -807,7 +807,7 @@ struct SatGen
std::vector<int> undef_a_shifted; std::vector<int> undef_a_shifted;
extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE; extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool()) if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
extend_bit = undef_a.back(); extend_bit = undef_a.back();
while (undef_y.size() < undef_a.size()) while (undef_y.size() < undef_a.size())
@ -822,13 +822,13 @@ struct SatGen
undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE); undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($sshr)) if (cell->type == ID($sshr))
undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE); undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shift)) if (cell->type == ID($shift))
undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE); undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
if (cell->type == ID($shiftx)) if (cell->type == ID($shiftx))
undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE); undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b); int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b); std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
@ -945,7 +945,7 @@ struct SatGen
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> a_u, b_u; std::vector<int> a_u, b_u;
if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a); a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b); b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
} else { } else {
@ -971,12 +971,12 @@ struct SatGen
std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size()); std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
if (cell->type == ID($div)) { if (cell->type == ID($div)) {
if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u))); ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
else else
ez->assume(ez->vec_eq(y_tmp, y_u)); ez->assume(ez->vec_eq(y_tmp, y_u));
} else { } else {
if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf))); ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
else else
ez->assume(ez->vec_eq(y_tmp, chain_buf)); ez->assume(ez->vec_eq(y_tmp, chain_buf));
@ -987,7 +987,7 @@ struct SatGen
} else { } else {
std::vector<int> div_zero_result; std::vector<int> div_zero_result;
if (cell->type == ID($div)) { if (cell->type == ID($div)) {
if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) { if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
std::vector<int> all_ones(y.size(), ez->CONST_TRUE); std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
std::vector<int> only_first_one(y.size(), ez->CONST_FALSE); std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
only_first_one.at(0) = ez->CONST_TRUE; only_first_one.at(0) = ez->CONST_TRUE;
@ -999,7 +999,7 @@ struct SatGen
} else { } else {
int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size()); int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits); div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back()); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
else else
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE); div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
@ -1021,7 +1021,7 @@ struct SatGen
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> lut; std::vector<int> lut;
for (auto bit : cell->getParam(ID(LUT)).bits) for (auto bit : cell->getParam(ID::LUT).bits)
lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE); lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
while (GetSize(lut) < (1 << GetSize(a))) while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->CONST_FALSE); lut.push_back(ez->CONST_FALSE);
@ -1070,10 +1070,10 @@ struct SatGen
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0); int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int width = cell->getParam(ID(WIDTH)).as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int depth = cell->getParam(ID(DEPTH)).as_int(); int depth = cell->getParam(ID::DEPTH).as_int();
vector<State> table_raw = cell->getParam(ID(TABLE)).bits; vector<State> table_raw = cell->getParam(ID::TABLE).bits;
while (GetSize(table_raw) < 2*width*depth) while (GetSize(table_raw) < 2*width*depth)
table_raw.push_back(State::S0); table_raw.push_back(State::S0);
@ -1151,9 +1151,9 @@ struct SatGen
{ {
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep); std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y; std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x; std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
@ -1169,10 +1169,10 @@ struct SatGen
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep); std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c))); ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y)); ez->assume(ez->vec_eq(undef_x, undef_y));
@ -1185,10 +1185,10 @@ struct SatGen
if (cell->type == ID($lcu)) if (cell->type == ID($lcu))
{ {
std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep); std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep); std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co; std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
@ -1197,10 +1197,10 @@ struct SatGen
if (model_undef) if (model_undef)
{ {
std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep); std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep); std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
int undef_any_p = ez->expression(ezSAT::OpOr, undef_p); int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
int undef_any_g = ez->expression(ezSAT::OpOr, undef_g); int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
@ -1220,10 +1220,10 @@ struct SatGen
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep); std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep); std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep); std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep); std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(a, b, y, cell); extendSignalWidth(a, b, y, cell);
extendSignalWidth(a, b, x, cell); extendSignalWidth(a, b, x, cell);
@ -1250,12 +1250,12 @@ struct SatGen
{ {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep); std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep); std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep); std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep); std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep); std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep); std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep); std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell); extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell); extendSignalWidth(undef_a, undef_b, undef_x, cell);
@ -1285,7 +1285,7 @@ struct SatGen
{ {
RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y); RTLIL::SigSpec y = cell->getPort(ID::Y);
ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep)); ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
return true; return true;
} }
@ -1306,20 +1306,20 @@ struct SatGen
{ {
if (timestep == 1) if (timestep == 1)
{ {
initial_state.add((*sigmap)(cell->getPort(ID(Q)))); initial_state.add((*sigmap)(cell->getPort(ID::Q)));
} }
else else
{ {
std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1); std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep); std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q; std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq)); ez->assume(ez->vec_eq(d, qq));
if (model_undef) if (model_undef)
{ {
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1); std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep); std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q)); ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q); undefGating(q, qq, undef_q);
@ -1397,7 +1397,7 @@ struct SatGen
{ {
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
asserts_a[pf].append((*sigmap)(cell->getPort(ID::A))); asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true; return true;
} }
@ -1405,7 +1405,7 @@ struct SatGen
{ {
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep)); std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
assumes_a[pf].append((*sigmap)(cell->getPort(ID::A))); assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN)))); assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
return true; return true;
} }

26
kernel/timinginfo.h
View file

@ -82,20 +82,20 @@ struct TimingInfo
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) { if (cell->type == ID($specify2)) {
auto src = cell->getPort(ID(SRC)); auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID(DST)); auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks()) for (const auto &c : src.chunks())
if (!c.wire->port_input) if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks()) for (const auto &c : dst.chunks())
if (!c.wire->port_output) if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max); int max = std::max(rise_max,fall_max);
if (max < 0) if (max < 0)
log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell)); log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell));
if (cell->getParam(ID(FULL)).as_bool()) { if (cell->getParam(ID::FULL).as_bool()) {
for (const auto &s : src) for (const auto &s : src)
for (const auto &d : dst) { for (const auto &d : dst) {
auto r = t.comb.insert(BitBit(s,d)); auto r = t.comb.insert(BitBit(s,d));
@ -117,16 +117,16 @@ struct TimingInfo
} }
} }
else if (cell->type == ID($specify3)) { else if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID(SRC)); auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID(DST)); auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks()) for (const auto &c : src.chunks())
if (!c.wire->port_input) if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks()) for (const auto &c : dst.chunks())
if (!c.wire->port_output) if (!c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
int max = std::max(rise_max,fall_max); int max = std::max(rise_max,fall_max);
if (max < 0) if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
@ -140,18 +140,18 @@ struct TimingInfo
} }
} }
else if (cell->type == ID($specrule)) { else if (cell->type == ID($specrule)) {
auto type = cell->getParam(ID(TYPE)).decode_string(); auto type = cell->getParam(ID::TYPE).decode_string();
if (type != "$setup" && type != "$setuphold") if (type != "$setup" && type != "$setuphold")
continue; continue;
auto src = cell->getPort(ID(SRC)); auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID(DST)); auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks()) for (const auto &c : src.chunks())
if (!c.wire->port_input) if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks()) for (const auto &c : dst.chunks())
if (!c.wire->port_input) if (!c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst)); log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
int max = cell->getParam(ID(T_LIMIT_MAX)).as_int(); int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
if (max < 0) if (max < 0)
log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
if (max <= 0) { if (max <= 0) {

4
kernel/yosys.h
View file

@ -306,9 +306,9 @@ RTLIL::IdString new_id(std::string file, int line, std::string func);
#define NEW_ID \ #define NEW_ID \
YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__) YOSYS_NAMESPACE_PREFIX new_id(__FILE__, __LINE__, __FUNCTION__)
// Create a statically allocated IdString object, using for example ID(A) or ID($add). // Create a statically allocated IdString object, using for example ID::A or ID($add).
// //
// Recipe for Converting old code that is using conversion of strings like "\\A" and // Recipe for Converting old code that is using conversion of strings like ID::A and
// "$add" for creating IdStrings: Run below SED command on the .cc file and then use for // "$add" for creating IdStrings: Run below SED command on the .cc file and then use for
// example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary. // example "meld foo.cc foo.cc.orig" to manually compile errors, if necessary.
// //

8
passes/cmds/add.cc
View file

@ -42,9 +42,9 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
} }
else { else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype); RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID(A), wire); formal_cell->setPort(ID::A, wire);
if(enable_name == "") { if(enable_name == "") {
formal_cell->setPort(ID(EN), State::S1); formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str()); log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
} }
else { else {
@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
if(enable_wire == nullptr) if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str()); log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
formal_cell->setPort(ID(EN), enable_wire); formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str()); log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
} }
} }
@ -212,7 +212,7 @@ struct AddPass : public Pass {
log_assert(module != nullptr); log_assert(module != nullptr);
if (!design->selected_whole_module(module->name)) if (!design->selected_whole_module(module->name))
continue; continue;
if (module->get_bool_attribute("\\blackbox")) if (module->get_bool_attribute(ID::blackbox))
continue; continue;
selected_anything = true; selected_anything = true;

2
passes/cmds/blackbox.cc
View file

@ -73,7 +73,7 @@ struct BlackboxPass : public Pass {
module->remove(remove_wires); module->remove(remove_wires);
module->set_bool_attribute("\\blackbox"); module->set_bool_attribute(ID::blackbox);
} }
} }
} BlackboxPass; } BlackboxPass;

4
passes/cmds/bugpoint.cc
View file

@ -155,7 +155,7 @@ struct BugpointPass : public Pass {
for (auto wire : mod->wires()) for (auto wire : mod->wires())
{ {
if (!stage2 && wire->get_bool_attribute("$bugpoint")) if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
continue; continue;
if (wire->port_input || wire->port_output) if (wire->port_input || wire->port_output)
@ -220,7 +220,7 @@ struct BugpointPass : public Pass {
{ {
log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str()); log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size()); RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
wire->set_bool_attribute("$bugpoint"); wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first); wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first); wire->port_output = cell->output(it.first);
cell->unsetPort(it.first); cell->unsetPort(it.first);

88
passes/cmds/check.cc
View file

@ -99,47 +99,47 @@ struct CheckPass : public Pass {
log_header(design, "Executing CHECK pass (checking for obvious problems).\n"); log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
pool<IdString> fftypes; pool<IdString> fftypes;
fftypes.insert("$sr"); fftypes.insert(ID($sr));
fftypes.insert("$ff"); fftypes.insert(ID($ff));
fftypes.insert("$dff"); fftypes.insert(ID($dff));
fftypes.insert("$dffe"); fftypes.insert(ID($dffe));
fftypes.insert("$dffsr"); fftypes.insert(ID($dffsr));
fftypes.insert("$adff"); fftypes.insert(ID($adff));
fftypes.insert("$dlatch"); fftypes.insert(ID($dlatch));
fftypes.insert("$dlatchsr"); fftypes.insert(ID($dlatchsr));
fftypes.insert("$_DFFE_NN_"); fftypes.insert(ID($_DFFE_NN_));
fftypes.insert("$_DFFE_NP_"); fftypes.insert(ID($_DFFE_NP_));
fftypes.insert("$_DFFE_PN_"); fftypes.insert(ID($_DFFE_PN_));
fftypes.insert("$_DFFE_PP_"); fftypes.insert(ID($_DFFE_PP_));
fftypes.insert("$_DFFSR_NNN_"); fftypes.insert(ID($_DFFSR_NNN_));
fftypes.insert("$_DFFSR_NNP_"); fftypes.insert(ID($_DFFSR_NNP_));
fftypes.insert("$_DFFSR_NPN_"); fftypes.insert(ID($_DFFSR_NPN_));
fftypes.insert("$_DFFSR_NPP_"); fftypes.insert(ID($_DFFSR_NPP_));
fftypes.insert("$_DFFSR_PNN_"); fftypes.insert(ID($_DFFSR_PNN_));
fftypes.insert("$_DFFSR_PNP_"); fftypes.insert(ID($_DFFSR_PNP_));
fftypes.insert("$_DFFSR_PPN_"); fftypes.insert(ID($_DFFSR_PPN_));
fftypes.insert("$_DFFSR_PPP_"); fftypes.insert(ID($_DFFSR_PPP_));
fftypes.insert("$_DFF_NN0_"); fftypes.insert(ID($_DFF_NN0_));
fftypes.insert("$_DFF_NN1_"); fftypes.insert(ID($_DFF_NN1_));
fftypes.insert("$_DFF_NP0_"); fftypes.insert(ID($_DFF_NP0_));
fftypes.insert("$_DFF_NP1_"); fftypes.insert(ID($_DFF_NP1_));
fftypes.insert("$_DFF_N_"); fftypes.insert(ID($_DFF_N_));
fftypes.insert("$_DFF_PN0_"); fftypes.insert(ID($_DFF_PN0_));
fftypes.insert("$_DFF_PN1_"); fftypes.insert(ID($_DFF_PN1_));
fftypes.insert("$_DFF_PP0_"); fftypes.insert(ID($_DFF_PP0_));
fftypes.insert("$_DFF_PP1_"); fftypes.insert(ID($_DFF_PP1_));
fftypes.insert("$_DFF_P_"); fftypes.insert(ID($_DFF_P_));
fftypes.insert("$_DLATCHSR_NNN_"); fftypes.insert(ID($_DLATCHSR_NNN_));
fftypes.insert("$_DLATCHSR_NNP_"); fftypes.insert(ID($_DLATCHSR_NNP_));
fftypes.insert("$_DLATCHSR_NPN_"); fftypes.insert(ID($_DLATCHSR_NPN_));
fftypes.insert("$_DLATCHSR_NPP_"); fftypes.insert(ID($_DLATCHSR_NPP_));
fftypes.insert("$_DLATCHSR_PNN_"); fftypes.insert(ID($_DLATCHSR_PNN_));
fftypes.insert("$_DLATCHSR_PNP_"); fftypes.insert(ID($_DLATCHSR_PNP_));
fftypes.insert("$_DLATCHSR_PPN_"); fftypes.insert(ID($_DLATCHSR_PPN_));
fftypes.insert("$_DLATCHSR_PPP_"); fftypes.insert(ID($_DLATCHSR_PPP_));
fftypes.insert("$_DLATCH_N_"); fftypes.insert(ID($_DLATCH_N_));
fftypes.insert("$_DLATCH_P_"); fftypes.insert(ID($_DLATCH_P_));
fftypes.insert("$_FF_"); fftypes.insert(ID($_FF_));
for (auto module : design->selected_whole_modules_warn()) for (auto module : design->selected_whole_modules_warn())
{ {
@ -202,8 +202,8 @@ struct CheckPass : public Pass {
if (wire->port_input && !wire->port_output) if (wire->port_input && !wire->port_output)
for (auto bit : sigmap(wire)) for (auto bit : sigmap(wire))
if (bit.wire) wire_drivers_count[bit]++; if (bit.wire) wire_drivers_count[bit]++;
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sigmap(SigBit(wire, i))); init_bits.insert(sigmap(SigBit(wire, i)));
@ -245,7 +245,7 @@ struct CheckPass : public Pass {
if (fftypes.count(cell->type) == 0) if (fftypes.count(cell->type) == 0)
continue; continue;
for (auto bit : sigmap(cell->getPort("\\Q"))) for (auto bit : sigmap(cell->getPort(ID::Q)))
init_bits.erase(bit); init_bits.erase(bit);
} }

74
passes/cmds/chformal.cc
View file

@ -77,23 +77,23 @@ struct ChformalPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++) for (argidx = 1; argidx < args.size(); argidx++)
{ {
if (args[argidx] == "-assert") { if (args[argidx] == "-assert") {
constr_types.insert("$assert"); constr_types.insert(ID($assert));
continue; continue;
} }
if (args[argidx] == "-assume") { if (args[argidx] == "-assume") {
constr_types.insert("$assume"); constr_types.insert(ID($assume));
continue; continue;
} }
if (args[argidx] == "-live") { if (args[argidx] == "-live") {
constr_types.insert("$live"); constr_types.insert(ID($live));
continue; continue;
} }
if (args[argidx] == "-fair") { if (args[argidx] == "-fair") {
constr_types.insert("$fair"); constr_types.insert(ID($fair));
continue; continue;
} }
if (args[argidx] == "-cover") { if (args[argidx] == "-cover") {
constr_types.insert("$cover"); constr_types.insert(ID($cover));
continue; continue;
} }
if (mode == 0 && args[argidx] == "-remove") { if (mode == 0 && args[argidx] == "-remove") {
@ -139,11 +139,11 @@ struct ChformalPass : public Pass {
extra_args(args, argidx, design); extra_args(args, argidx, design);
if (constr_types.empty()) { if (constr_types.empty()) {
constr_types.insert("$assert"); constr_types.insert(ID($assert));
constr_types.insert("$assume"); constr_types.insert(ID($assume));
constr_types.insert("$live"); constr_types.insert(ID($live));
constr_types.insert("$fair"); constr_types.insert(ID($fair));
constr_types.insert("$cover"); constr_types.insert(ID($cover));
} }
if (mode == 0) if (mode == 0)
@ -171,11 +171,11 @@ struct ChformalPass : public Pass {
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count("\\init") == 0) if (wire->attributes.count(ID::init) == 0)
continue; continue;
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) { for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) {
if (initval[i] == State::S0) if (initval[i] == State::S0)
@ -187,17 +187,17 @@ struct ChformalPass : public Pass {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
{ {
if (cell->type == "$ff") { if (cell->type == ID($ff)) {
SigSpec D = sigmap(cell->getPort("\\D")); SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort("\\Q")); SigSpec Q = sigmap(cell->getPort(ID::Q));
for (int i = 0; i < GetSize(D); i++) for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false)); ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
} }
if (cell->type == "$dff") { if (cell->type == ID($dff)) {
SigSpec D = sigmap(cell->getPort("\\D")); SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort("\\Q")); SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec C = sigmap(cell->getPort("\\CLK")); SigSpec C = sigmap(cell->getPort(ID::CLK));
bool clockpol = cell->getParam("\\CLK_POLARITY").as_bool(); bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++) for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol)); ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
} }
@ -207,14 +207,14 @@ struct ChformalPass : public Pass {
while (true) while (true)
{ {
SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort("\\EN")); SigSpec EN = sigmap(cell->getPort(ID::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0) if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break; break;
if (!init_zero.count(EN)) { if (!init_zero.count(EN)) {
if (cell->type == "$cover") break; if (cell->type == ID($cover)) break;
if (cell->type.in("$assert", "$assume") && !init_one.count(A)) break; if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
} }
const auto &A_map = ffmap.at(A); const auto &A_map = ffmap.at(A);
@ -224,7 +224,7 @@ struct ChformalPass : public Pass {
break; break;
cell->setPort(ID::A, A_map.first); cell->setPort(ID::A, A_map.first);
cell->setPort("\\EN", EN_map.first); cell->setPort(ID::EN, EN_map.first);
} }
} }
else else
@ -234,17 +234,17 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++) for (int i = 0; i < mode_arg; i++)
{ {
SigSpec orig_a = cell->getPort(ID::A); SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort("\\EN"); SigSpec orig_en = cell->getPort(ID::EN);
Wire *new_a = module->addWire(NEW_ID); Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID); Wire *new_en = module->addWire(NEW_ID);
new_en->attributes["\\init"] = State::S0; new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a); module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en); module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a); cell->setPort(ID::A, new_a);
cell->setPort("\\EN", new_en); cell->setPort(ID::EN, new_en);
} }
} }
else else
@ -254,26 +254,26 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++) { for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID); Wire *w = module->addWire(NEW_ID);
w->attributes["\\init"] = State::S0; w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w); module->addFf(NEW_ID, en, w);
en = w; en = w;
} }
for (auto cell : constr_cells) for (auto cell : constr_cells)
cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN"))); cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
} }
else else
if (mode == 'c') if (mode == 'c')
{ {
for (auto cell : constr_cells) for (auto cell : constr_cells)
if (assert2assume && cell->type == "$assert") if (assert2assume && cell->type == ID($assert))
cell->type = "$assume"; cell->type = ID($assume);
else if (assume2assert && cell->type == "$assume") else if (assume2assert && cell->type == ID($assume))
cell->type = "$assert"; cell->type = ID($assert);
else if (live2fair && cell->type == "$live") else if (live2fair && cell->type == ID($live))
cell->type = "$fair"; cell->type = ID($fair);
else if (fair2live && cell->type == "$fair") else if (fair2live && cell->type == ID($fair))
cell->type = "$live"; cell->type = ID($live);
} }
} }
} }

4
passes/cmds/delete.cc
View file

@ -107,8 +107,8 @@ struct DeletePass : public Pass {
for (auto &it : module->cells_) { for (auto &it : module->cells_) {
if (design->selected(module, it.second)) if (design->selected(module, it.second))
delete_cells.insert(it.second); delete_cells.insert(it.second);
if (it.second->type.in("$memrd", "$memwr") && if (it.second->type.in(ID($memrd), ID($memwr)) &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0) delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0)
delete_cells.insert(it.second); delete_cells.insert(it.second);
} }

2
passes/cmds/qwp.cc
View file

@ -737,7 +737,7 @@ struct QwpWorker
for (auto &node : nodes) for (auto &node : nodes)
if (node.cell != nullptr) if (node.cell != nullptr)
node.cell->attributes["\\qwp_position"] = stringf("%f %f", node.pos, node.alt_pos); node.cell->attributes[ID::qwp_position] = stringf("%f %f", node.pos, node.alt_pos);
vector<double> edge_lengths; vector<double> edge_lengths;
vector<double> weighted_edge_lengths; vector<double> weighted_edge_lengths;

4
passes/cmds/setattr.cc
View file

@ -159,10 +159,10 @@ struct WbflipPass : public Pass {
if (!design->selected(module)) if (!design->selected(module))
continue; continue;
if (module->get_bool_attribute("\\blackbox")) if (module->get_bool_attribute(ID::blackbox))
continue; continue;
module->set_bool_attribute("\\whitebox", !module->get_bool_attribute("\\whitebox")); module->set_bool_attribute(ID::whitebox, !module->get_bool_attribute(ID::whitebox));
} }
} }
} WbflipPass; } WbflipPass;

20
passes/cmds/setundef.cc
View file

@ -360,10 +360,10 @@ struct SetundefPass : public Pass {
pool<Wire*> initwires; pool<Wire*> initwires;
pool<IdString> fftypes; pool<IdString> fftypes;
fftypes.insert("$dff"); fftypes.insert(ID($dff));
fftypes.insert("$dffe"); fftypes.insert(ID($dffe));
fftypes.insert("$dffsr"); fftypes.insert(ID($dffsr));
fftypes.insert("$adff"); fftypes.insert(ID($adff));
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'}; std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
@ -389,7 +389,7 @@ struct SetundefPass : public Pass {
if (!fftypes.count(cell->type)) if (!fftypes.count(cell->type))
continue; continue;
for (auto bit : sigmap(cell->getPort("\\Q"))) for (auto bit : sigmap(cell->getPort(ID::Q)))
ffbits.insert(bit); ffbits.insert(bit);
} }
@ -411,7 +411,7 @@ struct SetundefPass : public Pass {
for (auto wire : initwires) for (auto wire : initwires)
{ {
Const &initval = wire->attributes["\\init"]; Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx); initval.bits.resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) { for (int i = 0; i < GetSize(wire); i++) {
@ -423,7 +423,7 @@ struct SetundefPass : public Pass {
} }
if (initval.is_fully_undef()) if (initval.is_fully_undef())
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
} }
initwires.clear(); initwires.clear();
@ -439,14 +439,14 @@ struct SetundefPass : public Pass {
if (wire->name[0] == (wire_types ? '\\' : '$')) if (wire->name[0] == (wire_types ? '\\' : '$'))
continue; continue;
if (!wire->attributes.count("\\init")) if (!wire->attributes.count(ID::init))
continue; continue;
Const &initval = wire->attributes["\\init"]; Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx); initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) { if (initval.is_fully_undef()) {
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
continue; continue;
} }

14
passes/cmds/splice.cc
View file

@ -75,10 +75,10 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig; RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) { if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
cell->parameters["\\OFFSET"] = offset; cell->parameters[ID::OFFSET] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size(); cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size(); cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a); cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size())); cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y); new_sig = cell->getPort(ID::Y);
@ -132,9 +132,9 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front()); RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) { for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]); RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
cell->parameters["\\A_WIDTH"] = new_sig.size(); cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size(); cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig); cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2); cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size())); cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));

10
passes/cmds/splitnets.cc
View file

@ -63,14 +63,14 @@ struct SplitnetsWorker
if (wire->attributes.count(ID::src)) if (wire->attributes.count(ID::src))
new_wire->attributes[ID::src] = wire->attributes.at(ID::src); new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
if (wire->attributes.count("\\keep")) if (wire->attributes.count(ID::keep))
new_wire->attributes["\\keep"] = wire->attributes.at("\\keep"); new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
if (wire->attributes.count("\\init")) { if (wire->attributes.count(ID::init)) {
Const old_init = wire->attributes.at("\\init"), new_init; Const old_init = wire->attributes.at(ID::init), new_init;
for (int i = offset; i < offset+width; i++) for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx); new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_wire->attributes["\\init"] = new_init; new_wire->attributes[ID::init] = new_init;
} }
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector(); std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();

34
passes/cmds/stat.cc
View file

@ -109,22 +109,22 @@ struct statdata_t
if (width_mode) if (width_mode)
{ {
if (cell_type.in("$not", "$pos", "$neg", if (cell_type.in(ID($not), ID($pos), ID($neg),
"$logic_not", "$logic_and", "$logic_or", ID($logic_not), ID($logic_and), ID($logic_or),
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
"$lut", "$and", "$or", "$xor", "$xnor", ID($lut), ID($and), ID($or), ID($xor), ID($xnor),
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt", ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
"$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) { ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) {
int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0; int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0; int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0; int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y})); cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
} }
else if (cell_type.in("$mux", "$pmux")) else if (cell_type.in(ID($mux), ID($pmux)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y))); cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr")) else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q"))); cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Q)));
} }
if (!cell_area.empty()) { if (!cell_area.empty()) {
@ -172,12 +172,12 @@ struct statdata_t
if (tech == "xilinx") if (tech == "xilinx")
{ {
int lut6_cnt = num_cells_by_type["\\LUT6"]; int lut6_cnt = num_cells_by_type[ID(LUT6)];
int lut5_cnt = num_cells_by_type["\\LUT5"]; int lut5_cnt = num_cells_by_type[ID(LUT5)];
int lut4_cnt = num_cells_by_type["\\LUT4"]; int lut4_cnt = num_cells_by_type[ID(LUT4)];
int lut3_cnt = num_cells_by_type["\\LUT3"]; int lut3_cnt = num_cells_by_type[ID(LUT3)];
int lut2_cnt = num_cells_by_type["\\LUT2"]; int lut2_cnt = num_cells_by_type[ID(LUT2)];
int lut1_cnt = num_cells_by_type["\\LUT1"]; int lut1_cnt = num_cells_by_type[ID(LUT1)];
int lc_cnt = 0; int lc_cnt = 0;
lc_cnt += lut6_cnt; lc_cnt += lut6_cnt;
@ -235,7 +235,7 @@ struct statdata_t
if (gate_costs.count(ctype)) if (gate_costs.count(ctype))
tran_cnt += cnum * gate_costs.at(ctype); tran_cnt += cnum * gate_costs.at(ctype);
else if (ctype.in("$_DFF_P_", "$_DFF_N_")) else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
tran_cnt += cnum * 16; tran_cnt += cnum * 16;
else else
tran_cnt_exact = false; tran_cnt_exact = false;

4
passes/cmds/torder.cc
View file

@ -81,9 +81,9 @@ struct TorderPass : public Pass {
continue; continue;
if (!noautostop && yosys_celltypes.cell_known(cell->type)) { if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA")) if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
continue; continue;
if (cell->type == "$memrd" && conn.first == "\\DATA") if (cell->type == ID($memrd) && conn.first == ID::DATA)
continue; continue;
} }

2
passes/equiv/equiv_add.cc
View file

@ -152,7 +152,7 @@ struct EquivAddPass : public Pass {
for (int i = 0; i < GetSize(gold_signal); i++) { for (int i = 0; i < GetSize(gold_signal); i++) {
Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]); Cell *equiv_cell = module->addEquiv(NEW_ID, gold_signal[i], gate_signal[i], equiv_signal[i]);
equiv_cell->set_bool_attribute("\\keep"); equiv_cell->set_bool_attribute(ID::keep);
to_equiv_bits[gold_signal[i]] = equiv_signal[i]; to_equiv_bits[gold_signal[i]] = equiv_signal[i];
to_equiv_bits[gate_signal[i]] = equiv_signal[i]; to_equiv_bits[gate_signal[i]] = equiv_signal[i];
added_equiv_cells.insert(equiv_cell); added_equiv_cells.insert(equiv_cell);

4
passes/equiv/equiv_induct.cc
View file

@ -58,7 +58,7 @@ struct EquivInductWorker
log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type)); log_warning("No SAT model available for cell %s (%s).\n", log_id(cell), log_id(cell->type));
cell_warn_cache.insert(cell); cell_warn_cache.insert(cell);
} }
if (cell->type == "$equiv") { if (cell->type == ID($equiv)) {
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit(); SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit(); SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
if (bit_a != bit_b) { if (bit_a != bit_b) {
@ -219,7 +219,7 @@ struct EquivInductPass : public Pass {
pool<Cell*> unproven_equiv_cells; pool<Cell*> unproven_equiv_cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv") { if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B)) if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.insert(cell); unproven_equiv_cells.insert(cell);
} }

2
passes/equiv/equiv_make.cc
View file

@ -406,7 +406,7 @@ struct EquivMakeWorker
void init_bit2driven() void init_bit2driven()
{ {
for (auto cell : equiv_mod->cells()) { for (auto cell : equiv_mod->cells()) {
if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue; continue;
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
{ {

12
passes/equiv/equiv_mark.cc
View file

@ -48,7 +48,7 @@ struct EquivMarkWorker
{ {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "$equiv") if (cell->type == ID($equiv))
equiv_cells.insert(cell->name); equiv_cells.insert(cell->name);
for (auto &port : cell->connections()) for (auto &port : cell->connections())
@ -139,7 +139,7 @@ struct EquivMarkWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell_regions.count(cell->name) || cell->type != "$equiv") if (cell_regions.count(cell->name) || cell->type != ID($equiv))
continue; continue;
SigSpec sig_a = sigmap(cell->getPort(ID::A)); SigSpec sig_a = sigmap(cell->getPort(ID::A));
@ -176,10 +176,10 @@ struct EquivMarkWorker
{ {
if (cell_regions.count(cell->name)) { if (cell_regions.count(cell->name)) {
int r = final_region_map.at(cell_regions.at(cell->name)); int r = final_region_map.at(cell_regions.at(cell->name));
cell->attributes["\\equiv_region"] = Const(r); cell->attributes[ID::equiv_region] = Const(r);
region_cell_count[r]++; region_cell_count[r]++;
} else } else
cell->attributes.erase("\\equiv_region"); cell->attributes.erase(ID::equiv_region);
} }
for (auto wire : module->wires()) for (auto wire : module->wires())
@ -191,10 +191,10 @@ struct EquivMarkWorker
if (GetSize(regions) == 1) { if (GetSize(regions) == 1) {
int r = final_region_map.at(*regions.begin()); int r = final_region_map.at(*regions.begin());
wire->attributes["\\equiv_region"] = Const(r); wire->attributes[ID::equiv_region] = Const(r);
region_wire_count[r]++; region_wire_count[r]++;
} else } else
wire->attributes.erase("\\equiv_region"); wire->attributes.erase(ID::equiv_region);
} }
for (int i = 0; i < next_final_region; i++) for (int i = 0; i < next_final_region; i++)

12
passes/equiv/equiv_miter.cc
View file

@ -47,7 +47,7 @@ struct EquivMiterWorker
if (cone.count(c)) if (cone.count(c))
return; return;
if (c->type == "$equiv" && !seed_cells.count(c)) { if (c->type == ID($equiv) && !seed_cells.count(c)) {
leaves.insert(c); leaves.insert(c);
return; return;
} }
@ -57,7 +57,7 @@ struct EquivMiterWorker
for (auto &conn : c->connections()) { for (auto &conn : c->connections()) {
if (!ct.cell_input(c->type, conn.first)) if (!ct.cell_input(c->type, conn.first))
continue; continue;
if (c->type == "$equiv" && (conn.first == ID::A) != gold_mode) if (c->type == ID($equiv) && (conn.first == ID::A) != gold_mode)
continue; continue;
for (auto bit : sigmap(conn.second)) for (auto bit : sigmap(conn.second))
if (bit_to_driver.count(bit)) if (bit_to_driver.count(bit))
@ -81,7 +81,7 @@ struct EquivMiterWorker
// find seed cells // find seed cells
for (auto c : source_module->selected_cells()) for (auto c : source_module->selected_cells())
if (c->type == "$equiv") { if (c->type == ID($equiv)) {
log("Seed $equiv cell: %s\n", log_id(c)); log("Seed $equiv cell: %s\n", log_id(c));
seed_cells.insert(c); seed_cells.insert(c);
} }
@ -213,7 +213,7 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells; vector<Cell*> equiv_cells;
for (auto c : miter_module->cells()) for (auto c : miter_module->cells())
if (c->type == "$equiv" && c->getPort(ID::A) != c->getPort(ID::B)) if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
equiv_cells.push_back(c); equiv_cells.push_back(c);
for (auto c : equiv_cells) for (auto c : equiv_cells)
@ -224,7 +224,7 @@ struct EquivMiterWorker
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B)); miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
if (mode_cmp) { if (mode_cmp) {
string cmp_name = string("\\cmp") + log_signal(c->getPort(ID::Y)); string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
for (int i = 1; i < GetSize(cmp_name); i++) for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\') if (cmp_name[i] == '\\')
cmp_name[i] = '_'; cmp_name[i] = '_';
@ -242,7 +242,7 @@ struct EquivMiterWorker
} }
if (mode_trigger) { if (mode_trigger) {
auto w = miter_module->addWire("\\trigger"); auto w = miter_module->addWire(ID(trigger));
w->port_output = true; w->port_output = true;
miter_module->addReduceOr(NEW_ID, trigger_signals, w); miter_module->addReduceOr(NEW_ID, trigger_signals, w);
} }

4
passes/equiv/equiv_purge.cc
View file

@ -102,7 +102,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type != "$equiv") { if (cell->type != ID($equiv)) {
for (auto &port : cell->connections()) { for (auto &port : cell->connections()) {
if (cell->input(port.first)) if (cell->input(port.first))
for (auto bit : sigmap(port.second)) for (auto bit : sigmap(port.second))
@ -167,7 +167,7 @@ struct EquivPurgeWorker
rewrite_sigmap.add(chunk, make_input(chunk)); rewrite_sigmap.add(chunk, make_input(chunk));
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$equiv") if (cell->type == ID($equiv))
cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y)))); cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
module->fixup_ports(); module->fixup_ports();

2
passes/equiv/equiv_remove.cc
View file

@ -68,7 +68,7 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv" && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) { if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y))); log("Removing $equiv cell %s.%s (%s).\n", log_id(module), log_id(cell), log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A)); module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
module->remove(cell); module->remove(cell);

8
passes/equiv/equiv_simple.cc
View file

@ -60,8 +60,8 @@ struct EquivSimpleWorker
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first)) if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : sigmap(conn.second)) { for (auto bit : sigmap(conn.second)) {
if (cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) { if (cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_))) {
if (!conn.first.in("\\CLK", "\\C")) if (!conn.first.in(ID::CLK, ID::C))
next_seed.insert(bit); next_seed.insert(bit);
} else } else
find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit); find_input_cone(next_seed, cells_cone, bits_cone, cells_stop, bits_stop, input_bits, bit);
@ -344,7 +344,7 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0; int unproven_cells_counter = 0;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv" && cell->getPort(ID::A) != cell->getPort(ID::B)) { if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
auto bit = sigmap(cell->getPort(ID::Y).as_bit()); auto bit = sigmap(cell->getPort(ID::Y).as_bit());
auto bit_group = bit; auto bit_group = bit;
if (!nogroup && bit_group.wire) if (!nogroup && bit_group.wire)
@ -360,7 +360,7 @@ struct EquivSimplePass : public Pass {
unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module)); unproven_cells_counter, GetSize(unproven_equiv_cells), log_id(module));
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (!ct.cell_known(cell->type) && !cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_", "$ff", "$_FF_")) if (!ct.cell_known(cell->type) && !cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_), ID($ff), ID($_FF_)))
continue; continue;
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first)) if (yosys_celltypes.cell_output(cell->type, conn.first))

2
passes/equiv/equiv_status.cc
View file

@ -59,7 +59,7 @@ struct EquivStatusPass : public Pass {
int proven_equiv_cells = 0; int proven_equiv_cells = 0;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv") { if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B)) if (cell->getPort(ID::A) != cell->getPort(ID::B))
unproven_equiv_cells.push_back(cell); unproven_equiv_cells.push_back(cell);
else else

10
passes/equiv/equiv_struct.cc
View file

@ -110,9 +110,9 @@ struct EquivStructWorker
module->connect(sig_b, sig_a); module->connect(sig_b, sig_a);
} }
auto merged_attr = cell_b->get_strpool_attribute("\\equiv_merged"); auto merged_attr = cell_b->get_strpool_attribute(ID::equiv_merged);
merged_attr.insert(log_id(cell_b)); merged_attr.insert(log_id(cell_b));
cell_a->add_strpool_attribute("\\equiv_merged", merged_attr); cell_a->add_strpool_attribute(ID::equiv_merged, merged_attr);
module->remove(cell_b); module->remove(cell_b);
} }
@ -126,7 +126,7 @@ struct EquivStructWorker
pool<IdString> cells; pool<IdString> cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv") { if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
equiv_bits.add(sig_b, sig_a); equiv_bits.add(sig_b, sig_a);
@ -139,7 +139,7 @@ struct EquivStructWorker
} }
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$equiv") { if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit()); SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit()); SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit()); SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
@ -316,7 +316,7 @@ struct EquivStructPass : public Pass {
} }
void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE void execute(std::vector<std::string> args, Design *design) YS_OVERRIDE
{ {
pool<IdString> fwonly_cells({ "$equiv" }); pool<IdString> fwonly_cells({ ID($equiv) });
bool mode_icells = false; bool mode_icells = false;
bool mode_fwd = false; bool mode_fwd = false;
int max_iter = -1; int max_iter = -1;

46
passes/fsm/fsm_detect.cc
View file

@ -55,7 +55,7 @@ ret_false:
sig2driver.find(sig, cellport_list); sig2driver.find(sig, cellport_list);
for (auto &cellport : cellport_list) for (auto &cellport : cellport_list)
{ {
if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) { if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) {
goto ret_false; goto ret_false;
} }
@ -99,7 +99,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
RTLIL::Cell *cell = cellport.first; RTLIL::Cell *cell = cellport.first;
if (muxtree_cells.count(cell) > 0) if (muxtree_cells.count(cell) > 0)
continue; continue;
if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig) if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
continue; continue;
if (cellport.second != ID::A && cellport.second != ID::B) if (cellport.second != ID::A && cellport.second != ID::B)
return false; return false;
@ -122,7 +122,7 @@ static void detect_fsm(RTLIL::Wire *wire)
{ {
bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none"; bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none"; bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
bool has_init_attr = wire->attributes.count("\\init") > 0; bool has_init_attr = wire->attributes.count(ID::init) > 0;
bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire))); bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
bool looks_like_state_reg = false, looks_like_good_state_reg = false; bool looks_like_state_reg = false, looks_like_good_state_reg = false;
bool is_self_resetting = false; bool is_self_resetting = false;
@ -143,13 +143,13 @@ static void detect_fsm(RTLIL::Wire *wire)
for (auto &cellport : cellport_list) for (auto &cellport : cellport_list)
{ {
if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q") if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q)
continue; continue;
muxtree_cells.clear(); muxtree_cells.clear();
pool<Cell*> recursion_monitor; pool<Cell*> recursion_monitor;
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q")); RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D")); RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
dict<RTLIL::SigSpec, bool> mux_tree_cache; dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire)) if (sig_q != assign_map(wire))
@ -173,10 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire)
RTLIL::Cell *cell = cellport.first; RTLIL::Cell *cell = cellport.first;
bool set_output = false, clr_output = false; bool set_output = false, clr_output = false;
if (cell->type.in("$ne", "$reduce_or", "$reduce_bool")) if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
set_output = true; set_output = true;
if (cell->type.in("$eq", "$logic_not", "$reduce_and")) if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
clr_output = true; clr_output = true;
if (set_output || clr_output) { if (set_output || clr_output) {
@ -284,38 +284,34 @@ struct FsmDetectPass : public Pass {
ct.setup_stdcells(); ct.setup_stdcells();
ct.setup_stdcells_mem(); ct.setup_stdcells_mem();
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
{ {
if (!design->selected(mod_it.second)) module = mod;
continue;
module = mod_it.second;
assign_map.set(module); assign_map.set(module);
sig2driver.clear(); sig2driver.clear();
sig2user.clear(); sig2user.clear();
sig_at_port.clear(); sig_at_port.clear();
for (auto &cell_it : module->cells_) for (auto cell : module->cells())
for (auto &conn_it : cell_it.second->connections()) { for (auto &conn_it : cell->connections()) {
if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) { if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
RTLIL::SigSpec sig = conn_it.second; RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig); assign_map.apply(sig);
sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first)); sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
} }
if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) { if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
RTLIL::SigSpec sig = conn_it.second; RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig); assign_map.apply(sig);
sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first)); sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
} }
} }
for (auto &wire_it : module->wires_) for (auto wire : module->wires())
if (wire_it.second->port_id != 0) if (wire->port_id != 0)
sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second))); sig_at_port.add(assign_map(wire));
for (auto &wire_it : module->wires_) for (auto wire : module->selected_wires())
if (design->selected(module, wire_it.second)) detect_fsm(wire);
detect_fsm(wire_it.second);
} }
assign_map.clear(); assign_map.clear();

38
passes/fsm/fsm_expand.cc
View file

@ -47,10 +47,10 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell) bool is_cell_merge_candidate(RTLIL::Cell *cell)
{ {
if (full_mode || cell->type == "$_MUX_") if (full_mode || cell->type == ID($_MUX_))
return true; return true;
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
if (cell->getPort(ID::A).size() < 2) if (cell->getPort(ID::A).size() < 2)
return true; return true;
@ -81,8 +81,8 @@ struct FsmExpand
new_signals.sort_and_unify(); new_signals.sort_and_unify();
new_signals.remove_const(); new_signals.remove_const();
new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN"))); new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT"))); new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
if (new_signals.size() > 3) if (new_signals.size() > 3)
return false; return false;
@ -94,10 +94,10 @@ struct FsmExpand
{ {
std::vector<RTLIL::Cell*> cell_list; std::vector<RTLIL::Cell*> cell_list;
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN")))) for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
cell_list.push_back(c); cell_list.push_back(c);
for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT")))) for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
cell_list.push_back(c); cell_list.push_back(c);
current_set.clear(); current_set.clear();
@ -123,14 +123,14 @@ struct FsmExpand
if (already_optimized) if (already_optimized)
return; return;
int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int(); int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
if (trans_num > limit_transitions) if (trans_num > limit_transitions)
{ {
log(" grown transition table to %d entries -> optimize.\n", trans_num); log(" grown transition table to %d entries -> optimize.\n", trans_num);
FsmData::optimize_fsm(fsm_cell, module); FsmData::optimize_fsm(fsm_cell, module);
already_optimized = true; already_optimized = true;
trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int(); trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
log(" transition table size after optimizaton: %d\n", trans_num); log(" transition table size after optimizaton: %d\n", trans_num);
limit_transitions = 16 * trans_num; limit_transitions = 16 * trans_num;
} }
@ -178,14 +178,14 @@ struct FsmExpand
fsm_data.copy_from_cell(fsm_cell); fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size(); fsm_data.num_inputs += input_sig.size();
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN"); RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
new_ctrl_in.append(input_sig); new_ctrl_in.append(input_sig);
fsm_cell->setPort("\\CTRL_IN", new_ctrl_in); fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size(); fsm_data.num_outputs += output_sig.size();
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
new_ctrl_out.append(output_sig); new_ctrl_out.append(output_sig);
fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out); fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10) if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n", log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
@ -246,7 +246,7 @@ struct FsmExpand
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str()); log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
already_optimized = false; already_optimized = false;
limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int(); limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
for (create_current_set(); current_set.size() > 0; create_current_set()) { for (create_current_set(); current_set.size() > 0; create_current_set()) {
for (auto c : current_set) for (auto c : current_set)
@ -295,15 +295,13 @@ struct FsmExpandPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) { for (auto mod : design->selected_modules()) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells; std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells_) for (auto cell : mod->selected_cells())
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) if (cell->type == ID($fsm))
fsm_cells.push_back(cell_it.second); fsm_cells.push_back(cell);
for (auto c : fsm_cells) { for (auto c : fsm_cells) {
FsmExpand fsm_expand(c, design, mod_it.second, full_mode); FsmExpand fsm_expand(c, design, mod, full_mode);
fsm_expand.execute(); fsm_expand.execute();
} }
} }

19
passes/fsm/fsm_export.cc
View file

@ -57,7 +57,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
std::string kiss_name; std::string kiss_name;
size_t i; size_t i;
attr_it = cell->attributes.find("\\fsm_export"); attr_it = cell->attributes.find(ID::fsm_export);
if (!filename.empty()) { if (!filename.empty()) {
kiss_name.assign(filename); kiss_name.assign(filename);
} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") { } else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
@ -173,16 +173,15 @@ struct FsmExportPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
if (design->selected(mod_it.second)) for (auto cell : mod->selected_cells())
for (auto &cell_it : mod_it.second->cells_) if (cell->type == ID($fsm)) {
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { attr_it = cell->attributes.find(ID::fsm_export);
attr_it = cell_it.second->attributes.find("\\fsm_export"); if (!flag_noauto || (attr_it != cell->attributes.end())) {
if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) { write_kiss2(mod, cell, filename, flag_origenc);
write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc); filename.clear();
filename.clear();
}
} }
}
} }
} FsmExportPass; } FsmExportPass;

52
passes/fsm/fsm_extract.cc
View file

@ -70,7 +70,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
for (auto &cellport : cellport_list) for (auto &cellport : cellport_list)
{ {
RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) { if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str()); log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
return false; return false;
} }
@ -272,17 +272,17 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2driver.find(dff_out, cellport_list); sig2driver.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) { for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::Cell *cell = module->cells_.at(cellport.first);
if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q") if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue; continue;
log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str()); log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q")); RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D")); RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
clk = cell->getPort("\\CLK"); clk = cell->getPort(ID::CLK);
clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (cell->type == "$adff") { if (cell->type == ID($adff)) {
arst = cell->getPort("\\ARST"); arst = cell->getPort(ID::ARST);
arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool(); arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
reset_state = cell->parameters["\\ARST_VALUE"]; reset_state = cell->parameters[ID::ARST_VALUE];
} }
sig_q.replace(dff_out, sig_d, &dff_in); sig_q.replace(dff_out, sig_d, &dff_in);
break; break;
@ -368,14 +368,14 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell // create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm"); RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm));
fsm_cell->setPort("\\CLK", clk); fsm_cell->setPort(ID::CLK, clk);
fsm_cell->setPort("\\ARST", arst); fsm_cell->setPort(ID::ARST, arst);
fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0; fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0; fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
fsm_cell->setPort("\\CTRL_IN", ctrl_in); fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
fsm_cell->setPort("\\CTRL_OUT", ctrl_out); fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str()); fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes; fsm_cell->attributes = wire->attributes;
fsm_data.copy_to_cell(fsm_cell); fsm_data.copy_to_cell(fsm_cell);
@ -424,12 +424,9 @@ struct FsmExtractPass : public Pass {
CellTypes ct(design); CellTypes ct(design);
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
{ {
if (!design->selected(mod_it.second)) module = mod;
continue;
module = mod_it.second;
assign_map.set(module); assign_map.set(module);
sig2driver.clear(); sig2driver.clear();
@ -449,7 +446,7 @@ struct FsmExtractPass : public Pass {
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first)); sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
} }
} }
if (cell->type == "$pmux") { if (cell->type == ID($pmux)) {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S)); RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
for (auto &bit1 : sel_sig) for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig) for (auto &bit2 : sel_sig)
@ -459,10 +456,9 @@ struct FsmExtractPass : public Pass {
} }
std::vector<RTLIL::Wire*> wire_list; std::vector<RTLIL::Wire*> wire_list;
for (auto &wire_it : module->wires_) for (auto wire : module->selected_wires())
if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none") if (wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes[ID::fsm_encoding].decode_string() != "none")
if (design->selected(module, wire_it.second)) wire_list.push_back(wire);
wire_list.push_back(wire_it.second);
for (auto wire : wire_list) for (auto wire : wire_list)
extract_fsm(wire); extract_fsm(wire);
} }

19
passes/fsm/fsm_info.cc
View file

@ -46,16 +46,15 @@ struct FsmInfoPass : public Pass {
log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n"); log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
if (design->selected(mod_it.second)) for (auto cell : mod->selected_cells())
for (auto &cell_it : mod_it.second->cells_) if (cell->type == ID($fsm)) {
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) { log("\n");
log("\n"); log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str()); FsmData fsm_data;
FsmData fsm_data; fsm_data.copy_from_cell(cell);
fsm_data.copy_from_cell(cell_it.second); fsm_data.log_info(cell);
fsm_data.log_info(cell_it.second); }
}
} }
} FsmInfoPass; } FsmInfoPass;

102
passes/fsm/fsm_map.cc
View file

@ -74,15 +74,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *eq_wire = module->addWire(NEW_ID); RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(eq_wire)); and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, eq_sig_a); eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b); eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire)); eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size()); eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size()); eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(eq_sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} }
std::set<int> complete_in_state_cache = it.second; std::set<int> complete_in_state_cache = it.second;
@ -102,12 +102,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *or_wire = module->addWire(NEW_ID); RTLIL::Wire *or_wire = module->addWire(NEW_ID);
and_sig.append(RTLIL::SigSpec(or_wire)); and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, or_sig); or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire)); or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size()); or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} }
} }
@ -118,15 +118,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
RTLIL::Wire *and_wire = module->addWire(NEW_ID); RTLIL::Wire *and_wire = module->addWire(NEW_ID);
cases_vector.append(RTLIL::SigSpec(and_wire)); cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and"); RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
and_cell->setPort(ID::A, and_sig.extract(0, 1)); and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1)); and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire)); and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1); and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1); and_cell->parameters[ID::B_WIDTH] = RTLIL::Const(1);
and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); and_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
break; break;
} }
case 1: case 1:
@ -141,12 +141,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
} }
if (cases_vector.size() > 1) { if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or"); RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, cases_vector); or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output); or_cell->setPort(ID::Y, output);
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size()); or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} else if (cases_vector.size() == 1) { } else if (cases_vector.size() == 1) {
module->connect(RTLIL::SigSig(output, cases_vector)); module->connect(RTLIL::SigSig(output, cases_vector));
} else { } else {
@ -161,31 +161,31 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
FsmData fsm_data; FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell); fsm_data.copy_from_cell(fsm_cell);
RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN"); RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT"); RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
// create state register // create state register
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits); RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits); RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, ""); RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
if (fsm_cell->getPort("\\ARST").is_fully_const()) { if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
state_dff->type = "$dff"; state_dff->type = ID($dff);
} else { } else {
state_dff->type = "$adff"; state_dff->type = ID($adff);
state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"]; state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state]; state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits) for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
if (bit != RTLIL::State::S1) if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0; bit = RTLIL::State::S0;
state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST")); state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
} }
state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits); state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"]; state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK")); state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire)); state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire)); state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
// decode state register // decode state register
@ -212,20 +212,20 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{ {
encoding_is_onehot = false; encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq"); RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, sig_a); eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b); eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i)); eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size()); eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size()); eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(sig_b.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
} }
} }
if (encoding_is_onehot) if (encoding_is_onehot)
state_wire->set_bool_attribute("\\onehot"); state_wire->set_bool_attribute(ID::onehot);
// generate next_state signal // generate next_state signal
@ -285,13 +285,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
} }
} }
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux"); RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
mux_cell->setPort(ID::A, sig_a); mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b); mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s); mux_cell->setPort(ID::S, sig_s);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire)); mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size()); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size()); mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
} }
} }
@ -336,15 +336,13 @@ struct FsmMapPass : public Pass {
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n"); log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) { for (auto mod : design->selected_modules()) {
if (!design->selected(mod_it.second))
continue;
std::vector<RTLIL::Cell*> fsm_cells; std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells_) for (auto cell : mod->selected_cells())
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) if (cell->type == ID($fsm))
fsm_cells.push_back(cell_it.second); fsm_cells.push_back(cell);
for (auto cell : fsm_cells) for (auto cell : fsm_cells)
map_fsm(cell, mod_it.second); map_fsm(cell, mod);
} }
} }
} FsmMapPass; } FsmMapPass;

34
passes/fsm/fsm_opt.cc
View file

@ -81,10 +81,10 @@ struct FsmOpt
{ {
RTLIL::SigBit bit = sig.as_bit(); RTLIL::SigBit bit = sig.as_bit();
if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0) if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0)
return false; return false;
char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str()); char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str());
for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) { for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
if (tok[0] && bit.offset == atoi(tok)) { if (tok[0] && bit.offset == atoi(tok)) {
free(str); free(str);
@ -98,7 +98,7 @@ struct FsmOpt
void opt_const_and_unused_inputs() void opt_const_and_unused_inputs()
{ {
RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN"); RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
std::vector<bool> ctrl_in_used(ctrl_in.size()); std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table; std::vector<FsmData::transition_t> new_transition_table;
@ -119,15 +119,15 @@ struct FsmOpt
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) { for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
if (!ctrl_in_used[i]) { if (!ctrl_in_used[i]) {
log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1))); log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
for (auto &tr : new_transition_table) { for (auto &tr : new_transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_in); RTLIL::SigSpec tmp(tr.ctrl_in);
tmp.remove(i, 1); tmp.remove(i, 1);
tr.ctrl_in = tmp.as_const(); tr.ctrl_in = tmp.as_const();
} }
RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN"); RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
new_ctrl_in.remove(i, 1); new_ctrl_in.remove(i, 1);
cell->setPort("\\CTRL_IN", new_ctrl_in); cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_inputs--; fsm_data.num_inputs--;
} }
} }
@ -139,12 +139,12 @@ struct FsmOpt
void opt_unused_outputs() void opt_unused_outputs()
{ {
for (int i = 0; i < fsm_data.num_outputs; i++) { for (int i = 0; i < fsm_data.num_outputs; i++) {
RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1); RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
if (signal_is_unused(sig)) { if (signal_is_unused(sig)) {
log(" Removing unused output signal %s.\n", log_signal(sig)); log(" Removing unused output signal %s.\n", log_signal(sig));
RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT"); RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
new_ctrl_out.remove(i, 1); new_ctrl_out.remove(i, 1);
cell->setPort("\\CTRL_OUT", new_ctrl_out); cell->setPort(ID::CTRL_OUT, new_ctrl_out);
for (auto &tr : fsm_data.transition_table) { for (auto &tr : fsm_data.transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_out); RTLIL::SigSpec tmp(tr.ctrl_out);
tmp.remove(i, 1); tmp.remove(i, 1);
@ -158,7 +158,7 @@ struct FsmOpt
void opt_alias_inputs() void opt_alias_inputs()
{ {
RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
for (int i = 0; i < ctrl_in.size(); i++) for (int i = 0; i < ctrl_in.size(); i++)
for (int j = i+1; j < ctrl_in.size(); j++) for (int j = i+1; j < ctrl_in.size(); j++)
@ -195,8 +195,8 @@ struct FsmOpt
void opt_feedback_inputs() void opt_feedback_inputs()
{ {
RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"]; RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"]; RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT];
for (int j = 0; j < ctrl_out.size(); j++) for (int j = 0; j < ctrl_out.size(); j++)
for (int i = 0; i < ctrl_in.size(); i++) for (int i = 0; i < ctrl_in.size(); i++)
@ -340,12 +340,10 @@ struct FsmOptPass : public Pass {
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n"); log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
extra_args(args, 1, design); extra_args(args, 1, design);
for (auto &mod_it : design->modules_) { for (auto mod : design->selected_modules())
if (design->selected(mod_it.second)) for (auto cell : mod->selected_cells())
for (auto &cell_it : mod_it.second->cells_) if (cell->type == ID($fsm))
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) FsmData::optimize_fsm(cell, mod);
FsmData::optimize_fsm(cell_it.second, mod_it.second);
}
} }
} FsmOptPass; } FsmOptPass;

13
passes/fsm/fsm_recode.cc
View file

@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f) static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
{ {
std::string name = cell->parameters["\\NAME"].decode_string(); std::string name = cell->parameters[ID::NAME].decode_string();
fprintf(f, "set_fsm_state_vector {"); fprintf(f, "set_fsm_state_vector {");
for (int i = fsm_data.state_bits-1; i >= 0; i--) for (int i = fsm_data.state_bits-1; i >= 0; i--)
@ -95,7 +95,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str()); log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
if (encfile) if (encfile)
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str()); fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0; int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
for (int i = 0; i < int(fsm_data.state_table.size()); i++) for (int i = 0; i < int(fsm_data.state_table.size()); i++)
@ -181,11 +181,10 @@ struct FsmRecodePass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
if (design->selected(mod_it.second)) for (auto cell : mod->selected_cells())
for (auto &cell_it : mod_it.second->cells_) if (cell->type == ID($fsm))
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, encfile, default_encoding);
if (fm_set_fsm_file != NULL) if (fm_set_fsm_file != NULL)
fclose(fm_set_fsm_file); fclose(fm_set_fsm_file);

46
passes/fsm/fsmdata.h
View file

@ -33,31 +33,31 @@ struct FsmData
void copy_to_cell(RTLIL::Cell *cell) void copy_to_cell(RTLIL::Cell *cell)
{ {
cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs); cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);
cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs); cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);
int state_num_log2 = 0; int state_num_log2 = 0;
for (int i = state_table.size(); i > 0; i = i >> 1) for (int i = state_table.size(); i > 0; i = i >> 1)
state_num_log2++; state_num_log2++;
state_num_log2 = max(state_num_log2, 1); state_num_log2 = max(state_num_log2, 1);
cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits); cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);
cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size()); cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2); cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state); cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
cell->parameters["\\STATE_TABLE"] = RTLIL::Const(); cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
for (int i = 0; i < int(state_table.size()); i++) { for (int i = 0; i < int(state_table.size()); i++) {
std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits; std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
std::vector<RTLIL::State> &bits_state = state_table[i].bits; std::vector<RTLIL::State> &bits_state = state_table[i].bits;
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end()); bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
} }
cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size()); cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
cell->parameters["\\TRANS_TABLE"] = RTLIL::Const(); cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
for (int i = 0; i < int(transition_table.size()); i++) for (int i = 0; i < int(transition_table.size()); i++)
{ {
std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits; std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
transition_t &tr = transition_table[i]; transition_t &tr = transition_table[i];
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2); RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
@ -78,21 +78,21 @@ struct FsmData
void copy_from_cell(RTLIL::Cell *cell) void copy_from_cell(RTLIL::Cell *cell)
{ {
num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int(); num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();
num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int(); num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();
state_bits = cell->parameters["\\STATE_BITS"].as_int(); state_bits = cell->parameters[ID::STATE_BITS].as_int();
reset_state = cell->parameters["\\STATE_RST"].as_int(); reset_state = cell->parameters[ID::STATE_RST].as_int();
int state_num = cell->parameters["\\STATE_NUM"].as_int(); int state_num = cell->parameters[ID::STATE_NUM].as_int();
int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int(); int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();
int trans_num = cell->parameters["\\TRANS_NUM"].as_int(); int trans_num = cell->parameters[ID::TRANS_NUM].as_int();
if (reset_state < 0 || reset_state >= state_num) if (reset_state < 0 || reset_state >= state_num)
reset_state = -1; reset_state = -1;
RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"]; RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"]; RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
for (int i = 0; i < state_num; i++) { for (int i = 0; i < state_num; i++) {
RTLIL::Const state_code; RTLIL::Const state_code;
@ -134,7 +134,7 @@ struct FsmData
{ {
log("-------------------------------------\n"); log("-------------------------------------\n");
log("\n"); log("\n");
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str()); log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
log("\n"); log("\n");
log(" Number of input signals: %3d\n", num_inputs); log(" Number of input signals: %3d\n", num_inputs);
log(" Number of output signals: %3d\n", num_outputs); log(" Number of output signals: %3d\n", num_outputs);
@ -142,13 +142,13 @@ struct FsmData
log("\n"); log("\n");
log(" Input signals:\n"); log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN"); RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
for (int i = 0; i < GetSize(sig_in); i++) for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i])); log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n"); log("\n");
log(" Output signals:\n"); log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT"); RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
for (int i = 0; i < GetSize(sig_out); i++) for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i])); log(" %3d: %s\n", i, log_signal(sig_out[i]));

36
passes/hierarchy/hierarchy.cc
View file

@ -120,7 +120,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
RTLIL::Module *mod = new RTLIL::Module; RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype; mod->name = celltype;
mod->attributes["\\blackbox"] = RTLIL::Const(1); mod->attributes[ID::blackbox] = RTLIL::Const(1);
design->add(mod); design->add(mod);
for (auto &decl : ports) { for (auto &decl : ports) {
@ -166,7 +166,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// If any of the ports are actually interface ports, we will always need to // If any of the ports are actually interface ports, we will always need to
// reprocess the module: // reprocess the module:
if(!module->get_bool_attribute("\\interfaces_replaced_in_module")) { if(!module->get_bool_attribute(ID::interfaces_replaced_in_module)) {
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface)) if ((wire->port_input || wire->port_output) && wire->get_bool_attribute(ID::is_interface))
has_interface_ports = true; has_interface_ports = true;
@ -254,12 +254,12 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// some lists, so that the ports for sub-modules can be replaced further down: // some lists, so that the ports for sub-modules can be replaced further down:
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list if(mod->wire(conn.first) != nullptr && mod->wire(conn.first)->get_bool_attribute(ID::is_interface)) { // Check if the connection is present as an interface in the sub-module's port list
//const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_type"); //const pool<string> &interface_type_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_type);
//for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness) //for (auto &d : interface_type_pool) { // TODO: Compare interface type to type in parent module (not crucially important, but good for robustness)
//} //}
// Find if the sub-module has set a modport for the current interface connection: // Find if the sub-module has set a modport for the current interface connection:
const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute("\\interface_modport"); const pool<string> &interface_modport_pool = mod->wire(conn.first)->get_strpool_attribute(ID::interface_modport);
std::string interface_modport = ""; std::string interface_modport = "";
for (auto &d : interface_modport_pool) { for (auto &d : interface_modport_pool) {
interface_modport = "\\" + d; interface_modport = "\\" + d;
@ -270,7 +270,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
interface_name_str = "\\" + interface_name_str; interface_name_str = "\\" + interface_name_str;
RTLIL::IdString interface_name = interface_name_str; RTLIL::IdString interface_name = interface_name_str;
bool not_found_interface = false; bool not_found_interface = false;
if(module->get_bool_attribute("\\interfaces_replaced_in_module")) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either if(module->get_bool_attribute(ID::interfaces_replaced_in_module)) { // If 'interfaces' in the cell have not be been handled yet, there is no need to derive the sub-module either
// Check if the interface instance is present in module: // Check if the interface instance is present in module:
// Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'. // Interface instances may either have the plain name or the name appended with '_inst_from_top_dummy'.
// Check for both of them here // Check for both of them here
@ -309,7 +309,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// which will delay the expansion of this cell: // which will delay the expansion of this cell:
if (not_found_interface) { if (not_found_interface) {
// If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error: // If we have already gone over all cells in this module, and the interface has still not been found - flag it as an error:
if(!(module->get_bool_attribute("\\cells_not_processed"))) { if(!(module->get_bool_attribute(ID::cells_not_processed))) {
log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module)); log_warning("Could not find interface instance for `%s' in `%s'\n", log_id(interface_name), log_id(module));
} }
else { else {
@ -367,7 +367,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type // If there are no overridden parameters AND not interfaces, then we can use the existing module instance as the type
// for the cell: // for the cell:
if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute("\\module_not_derived")))) { if (cell->parameters.size() == 0 && (interfaces_to_add_to_submodule.size() == 0 || !(cell->get_bool_attribute(ID::module_not_derived)))) {
// If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:", // If the cell being processed is an the interface instance itself, go down to "handle_interface_instance:",
// so that the signals of the interface are added to the parent module. // so that the signals of the interface are added to the parent module.
if (mod->get_bool_attribute(ID::is_interface)) { if (mod->get_bool_attribute(ID::is_interface)) {
@ -384,23 +384,23 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
// We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter // We add all the signals of the interface explicitly to the parent module. This is always needed when we encounter
// an interface instance: // an interface instance:
if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute("\\module_not_derived")) { if (mod->get_bool_attribute(ID::is_interface) && cell->get_bool_attribute(ID::module_not_derived)) {
cell->set_bool_attribute(ID::is_interface); cell->set_bool_attribute(ID::is_interface);
RTLIL::Module *derived_module = design->module(cell->type); RTLIL::Module *derived_module = design->module(cell->type);
interfaces_in_module[cell->name] = derived_module; interfaces_in_module[cell->name] = derived_module;
did_something = true; did_something = true;
} }
// We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell) // We clear 'module_not_derived' such that we will not rederive the cell again (needed when there are interfaces connected to the cell)
cell->attributes.erase("\\module_not_derived"); cell->attributes.erase(ID::module_not_derived);
} }
// Clear the attribute 'cells_not_processed' such that it can be known that we // Clear the attribute 'cells_not_processed' such that it can be known that we
// have been through all cells at least once, and that we can know whether // have been through all cells at least once, and that we can know whether
// to flag an error because of interface instances not found: // to flag an error because of interface instances not found:
module->attributes.erase("\\cells_not_processed"); module->attributes.erase(ID::cells_not_processed);
// If any interface instances or interface ports were found in the module, we need to rederive it completely: // If any interface instances or interface ports were found in the module, we need to rederive it completely:
if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute("\\interfaces_replaced_in_module")) { if ((interfaces_in_module.size() > 0 || has_interface_ports) && !module->get_bool_attribute(ID::interfaces_replaced_in_module)) {
module->reprocess_module(design, interfaces_in_module); module->reprocess_module(design, interfaces_in_module);
return did_something; return did_something;
} }
@ -502,7 +502,7 @@ bool set_keep_assert(std::map<RTLIL::Module*, bool> &cache, RTLIL::Module *mod)
if (cache.count(mod) == 0) if (cache.count(mod) == 0)
for (auto c : mod->cells()) { for (auto c : mod->cells()) {
RTLIL::Module *m = mod->design->module(c->type); RTLIL::Module *m = mod->design->module(c->type);
if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in("$assert", "$assume", "$live", "$fair", "$cover")) if ((m != nullptr && set_keep_assert(cache, m)) || c->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover)))
return cache[mod] = true; return cache[mod] = true;
} }
return cache[mod]; return cache[mod];
@ -897,7 +897,7 @@ struct HierarchyPass : public Pass {
// Delete modules marked as 'to_delete': // Delete modules marked as 'to_delete':
std::vector<RTLIL::Module *> modules_to_delete; std::vector<RTLIL::Module *> modules_to_delete;
for(auto mod : design->modules()) { for(auto mod : design->modules()) {
if (mod->get_bool_attribute("\\to_delete")) { if (mod->get_bool_attribute(ID::to_delete)) {
modules_to_delete.push_back(mod); modules_to_delete.push_back(mod);
} }
} }
@ -927,7 +927,7 @@ struct HierarchyPass : public Pass {
for (auto mod : design->modules()) for (auto mod : design->modules())
if (set_keep_assert(cache, mod)) { if (set_keep_assert(cache, mod)) {
log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod)); log("Module %s directly or indirectly contains formal properties -> setting \"keep\" attribute.\n", log_id(mod));
mod->set_bool_attribute("\\keep"); mod->set_bool_attribute(ID::keep);
} }
} }
@ -994,7 +994,7 @@ struct HierarchyPass : public Pass {
{ {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (!cell->get_bool_attribute(ID(wildcard_port_conns))) if (!cell->get_bool_attribute(ID::wildcard_port_conns))
continue; continue;
Module *m = design->module(cell->type); Module *m = design->module(cell->type);
@ -1003,7 +1003,7 @@ struct HierarchyPass : public Pass {
RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
// Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths // Need accurate port widths for error checking; so must derive blackboxes with dynamic port widths
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true); IdString new_m_name = m->derive(design, cell->parameters, true);
if (new_m_name.empty()) if (new_m_name.empty())
continue; continue;
@ -1036,7 +1036,7 @@ struct HierarchyPass : public Pass {
RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type)); RTLIL::id2cstr(wire->name), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
cell->setPort(wire->name, parent_wire); cell->setPort(wire->name, parent_wire);
} }
cell->attributes.erase(ID(wildcard_port_conns)); cell->attributes.erase(ID::wildcard_port_conns);
} }
} }
@ -1186,7 +1186,7 @@ struct HierarchyPass : public Pass {
if (m == nullptr) if (m == nullptr)
continue; continue;
if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute("\\dynports")) { if (m->get_blackbox_attribute() && !cell->parameters.empty() && m->get_bool_attribute(ID::dynports)) {
IdString new_m_name = m->derive(design, cell->parameters, true); IdString new_m_name = m->derive(design, cell->parameters, true);
if (new_m_name.empty()) if (new_m_name.empty())
continue; continue;

16
passes/hierarchy/submod.cc
View file

@ -176,16 +176,16 @@ struct SubmodWorker
new_wire->start_offset = wire->start_offset; new_wire->start_offset = wire->start_offset;
new_wire->attributes = wire->attributes; new_wire->attributes = wire->attributes;
if (!flags.is_int_driven.is_fully_zero()) { if (!flags.is_int_driven.is_fully_zero()) {
new_wire->attributes.erase(ID(init)); new_wire->attributes.erase(ID::init);
auto sig = sigmap(wire); auto sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++) { for (int i = 0; i < GetSize(sig); i++) {
if (flags.is_int_driven[i] == State::S0) if (flags.is_int_driven[i] == State::S0)
continue; continue;
if (!sig[i].wire) if (!sig[i].wire)
continue; continue;
auto it = sig[i].wire->attributes.find(ID(init)); auto it = sig[i].wire->attributes.find(ID::init);
if (it != sig[i].wire->attributes.end()) { if (it != sig[i].wire->attributes.end()) {
auto jt = new_wire->attributes.insert(std::make_pair(ID(init), Const(State::Sx, GetSize(sig)))).first; auto jt = new_wire->attributes.insert(std::make_pair(ID::init, Const(State::Sx, GetSize(sig)))).first;
jt->second[i] = it->second[sig[i].offset]; jt->second[i] = it->second[sig[i].offset];
it->second[sig[i].offset] = State::Sx; it->second[sig[i].offset] = State::Sx;
} }
@ -275,18 +275,18 @@ struct SubmodWorker
if (opt_name.empty()) if (opt_name.empty())
{ {
for (auto &it : module->wires_) for (auto &it : module->wires_)
it.second->attributes.erase("\\submod"); it.second->attributes.erase(ID::submod);
for (auto &it : module->cells_) for (auto &it : module->cells_)
{ {
RTLIL::Cell *cell = it.second; RTLIL::Cell *cell = it.second;
if (cell->attributes.count("\\submod") == 0 || cell->attributes["\\submod"].bits.size() == 0) { if (cell->attributes.count(ID::submod) == 0 || cell->attributes[ID::submod].bits.size() == 0) {
cell->attributes.erase("\\submod"); cell->attributes.erase(ID::submod);
continue; continue;
} }
std::string submod_str = cell->attributes["\\submod"].decode_string(); std::string submod_str = cell->attributes[ID::submod].decode_string();
cell->attributes.erase("\\submod"); cell->attributes.erase(ID::submod);
if (submodules.count(submod_str) == 0) { if (submodules.count(submod_str) == 0) {
submodules[submod_str].name = submod_str; submodules[submod_str].name = submod_str;

10
passes/hierarchy/uniquify.cc
View file

@ -64,7 +64,7 @@ struct UniquifyPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
{ {
if (!module->get_bool_attribute("\\unique") && !module->get_bool_attribute(ID::top)) if (!module->get_bool_attribute(ID::unique) && !module->get_bool_attribute(ID::top))
continue; continue;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
@ -78,7 +78,7 @@ struct UniquifyPass : public Pass {
if (tmod->get_blackbox_attribute()) if (tmod->get_blackbox_attribute())
continue; continue;
if (tmod->get_bool_attribute("\\unique") && newname == tmod->name) if (tmod->get_bool_attribute(ID::unique) && newname == tmod->name)
continue; continue;
log("Creating module %s from %s.\n", log_id(newname), log_id(tmod)); log("Creating module %s from %s.\n", log_id(newname), log_id(tmod));
@ -86,9 +86,9 @@ struct UniquifyPass : public Pass {
auto smod = tmod->clone(); auto smod = tmod->clone();
smod->name = newname; smod->name = newname;
cell->type = newname; cell->type = newname;
smod->set_bool_attribute("\\unique"); smod->set_bool_attribute(ID::unique);
if (smod->attributes.count("\\hdlname") == 0) if (smod->attributes.count(ID::hdlname) == 0)
smod->attributes["\\hdlname"] = string(log_id(tmod->name)); smod->attributes[ID::hdlname] = string(log_id(tmod->name));
design->add(smod); design->add(smod);
did_something = true; did_something = true;

64
passes/memory/memory_bram.cc
View file

@ -105,11 +105,11 @@ struct rules_t
log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant); log_error("Bram %s variants %d and %d have different values for 'groups'.\n", log_id(name), variant, other.variant);
if (abits != other.abits) if (abits != other.abits)
variant_params["\\CFG_ABITS"] = abits; variant_params[ID::CFG_ABITS] = abits;
if (dbits != other.dbits) if (dbits != other.dbits)
variant_params["\\CFG_DBITS"] = dbits; variant_params[ID::CFG_DBITS] = dbits;
if (init != other.init) if (init != other.init)
variant_params["\\CFG_INIT"] = init; variant_params[ID::CFG_INIT] = init;
for (int i = 0; i < groups; i++) for (int i = 0; i < groups; i++)
{ {
@ -414,44 +414,44 @@ bool replace_cell(Cell *cell, const rules_t &rules, const rules_t::bram_t &bram,
log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant); log(" Mapping to bram type %s (variant %d):\n", log_id(bram.name), bram.variant);
// bram.dump_config(); // bram.dump_config();
int mem_size = cell->getParam("\\SIZE").as_int(); int mem_size = cell->getParam(ID::SIZE).as_int();
int mem_abits = cell->getParam("\\ABITS").as_int(); int mem_abits = cell->getParam(ID::ABITS).as_int();
int mem_width = cell->getParam("\\WIDTH").as_int(); int mem_width = cell->getParam(ID::WIDTH).as_int();
// int mem_offset = cell->getParam("\\OFFSET").as_int(); // int mem_offset = cell->getParam(ID::OFFSET).as_int();
bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
vector<Const> initdata; vector<Const> initdata;
if (cell_init) { if (cell_init) {
Const initparam = cell->getParam("\\INIT"); Const initparam = cell->getParam(ID::INIT);
initdata.reserve(mem_size); initdata.reserve(mem_size);
for (int i=0; i < mem_size; i++) for (int i=0; i < mem_size; i++)
initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx)); initdata.push_back(initparam.extract(mem_width*i, mem_width, State::Sx));
} }
int wr_ports = cell->getParam("\\WR_PORTS").as_int(); int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
auto wr_clken = SigSpec(cell->getParam("\\WR_CLK_ENABLE")); auto wr_clken = SigSpec(cell->getParam(ID::WR_CLK_ENABLE));
auto wr_clkpol = SigSpec(cell->getParam("\\WR_CLK_POLARITY")); auto wr_clkpol = SigSpec(cell->getParam(ID::WR_CLK_POLARITY));
wr_clken.extend_u0(wr_ports); wr_clken.extend_u0(wr_ports);
wr_clkpol.extend_u0(wr_ports); wr_clkpol.extend_u0(wr_ports);
SigSpec wr_en = cell->getPort("\\WR_EN"); SigSpec wr_en = cell->getPort(ID::WR_EN);
SigSpec wr_clk = cell->getPort("\\WR_CLK"); SigSpec wr_clk = cell->getPort(ID::WR_CLK);
SigSpec wr_data = cell->getPort("\\WR_DATA"); SigSpec wr_data = cell->getPort(ID::WR_DATA);
SigSpec wr_addr = cell->getPort("\\WR_ADDR"); SigSpec wr_addr = cell->getPort(ID::WR_ADDR);
int rd_ports = cell->getParam("\\RD_PORTS").as_int(); int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
auto rd_clken = SigSpec(cell->getParam("\\RD_CLK_ENABLE")); auto rd_clken = SigSpec(cell->getParam(ID::RD_CLK_ENABLE));
auto rd_clkpol = SigSpec(cell->getParam("\\RD_CLK_POLARITY")); auto rd_clkpol = SigSpec(cell->getParam(ID::RD_CLK_POLARITY));
auto rd_transp = SigSpec(cell->getParam("\\RD_TRANSPARENT")); auto rd_transp = SigSpec(cell->getParam(ID::RD_TRANSPARENT));
rd_clken.extend_u0(rd_ports); rd_clken.extend_u0(rd_ports);
rd_clkpol.extend_u0(rd_ports); rd_clkpol.extend_u0(rd_ports);
rd_transp.extend_u0(rd_ports); rd_transp.extend_u0(rd_ports);
SigSpec rd_en = cell->getPort("\\RD_EN"); SigSpec rd_en = cell->getPort(ID::RD_EN);
SigSpec rd_clk = cell->getPort("\\RD_CLK"); SigSpec rd_clk = cell->getPort(ID::RD_CLK);
SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_data = cell->getPort(ID::RD_DATA);
SigSpec rd_addr = cell->getPort("\\RD_ADDR"); SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0) if (match.shuffle_enable && bram.dbits >= portinfos.at(match.shuffle_enable - 'A').enable*2 && portinfos.at(match.shuffle_enable - 'A').enable > 0 && wr_ports > 0)
{ {
@ -915,7 +915,7 @@ grow_read_ports:;
else else
initparam[i*bram.dbits+j] = padding; initparam[i*bram.dbits+j] = padding;
} }
c->setParam("\\INIT", initparam); c->setParam(ID::INIT, initparam);
} }
for (auto &pi : portinfos) for (auto &pi : portinfos)
@ -1048,14 +1048,14 @@ void handle_cell(Cell *cell, const rules_t &rules)
{ {
log("Processing %s.%s:\n", log_id(cell->module), log_id(cell)); log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
bool cell_init = !SigSpec(cell->getParam("\\INIT")).is_fully_undef(); bool cell_init = !SigSpec(cell->getParam(ID::INIT)).is_fully_undef();
dict<string, int> match_properties; dict<string, int> match_properties;
match_properties["words"] = cell->getParam("\\SIZE").as_int(); match_properties["words"] = cell->getParam(ID::SIZE).as_int();
match_properties["abits"] = cell->getParam("\\ABITS").as_int(); match_properties["abits"] = cell->getParam(ID::ABITS).as_int();
match_properties["dbits"] = cell->getParam("\\WIDTH").as_int(); match_properties["dbits"] = cell->getParam(ID::WIDTH).as_int();
match_properties["wports"] = cell->getParam("\\WR_PORTS").as_int(); match_properties["wports"] = cell->getParam(ID::WR_PORTS).as_int();
match_properties["rports"] = cell->getParam("\\RD_PORTS").as_int(); match_properties["rports"] = cell->getParam(ID::RD_PORTS).as_int();
match_properties["bits"] = match_properties["words"] * match_properties["dbits"]; match_properties["bits"] = match_properties["words"] * match_properties["dbits"];
match_properties["ports"] = match_properties["wports"] + match_properties["rports"]; match_properties["ports"] = match_properties["wports"] + match_properties["rports"];
@ -1357,7 +1357,7 @@ struct MemoryBramPass : public Pass {
for (auto mod : design->selected_modules()) for (auto mod : design->selected_modules())
for (auto cell : mod->selected_cells()) for (auto cell : mod->selected_cells())
if (cell->type == "$mem") if (cell->type == ID($mem))
handle_cell(cell, rules); handle_cell(cell, rules);
} }
} MemoryBramPass; } MemoryBramPass;

92
passes/memory/memory_collect.cc
View file

@ -25,11 +25,11 @@ PRIVATE_NAMESPACE_BEGIN
bool memcells_cmp(Cell *a, Cell *b) bool memcells_cmp(Cell *a, Cell *b)
{ {
if (a->type == "$memrd" && b->type == "$memrd") if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name; return a->name < b->name;
if (a->type == "$memrd" || b->type == "$memrd") if (a->type == ID($memrd) || b->type == ID($memrd))
return (a->type == "$memrd") < (b->type == "$memrd"); return (a->type == ID($memrd)) < (b->type == ID($memrd));
return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
} }
Cell *handle_memory(Module *module, RTLIL::Memory *memory) Cell *handle_memory(Module *module, RTLIL::Memory *memory)
@ -62,8 +62,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
for (auto &cell_it : module->cells_) { for (auto &cell_it : module->cells_) {
Cell *cell = cell_it.second; Cell *cell = cell_it.second;
if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) { if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) {
SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec addr = sigmap(cell->getPort(ID::ADDR));
for (int i = 0; i < GetSize(addr); i++) for (int i = 0; i < GetSize(addr); i++)
if (addr[i] != State::S0) if (addr[i] != State::S0)
addr_bits = std::max(addr_bits, i+1); addr_bits = std::max(addr_bits, i+1);
@ -90,10 +90,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
{ {
log(" %s (%s)\n", log_id(cell), log_id(cell->type)); log(" %s (%s)\n", log_id(cell), log_id(cell->type));
if (cell->type == "$meminit") if (cell->type == ID($meminit))
{ {
SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec addr = sigmap(cell->getPort(ID::ADDR));
SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec data = sigmap(cell->getPort(ID::DATA));
if (!addr.is_fully_const()) if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell)); log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
@ -112,14 +112,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
continue; continue;
} }
if (cell->type == "$memwr") if (cell->type == ID($memwr))
{ {
SigSpec clk = sigmap(cell->getPort("\\CLK")); SigSpec clk = sigmap(cell->getPort(ID::CLK));
SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]); SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]); SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec addr = sigmap(cell->getPort(ID::ADDR));
SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec data = sigmap(cell->getPort(ID::DATA));
SigSpec en = sigmap(cell->getPort("\\EN")); SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero()) if (!en.is_fully_zero())
{ {
@ -142,15 +142,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
continue; continue;
} }
if (cell->type == "$memrd") if (cell->type == ID($memrd))
{ {
SigSpec clk = sigmap(cell->getPort("\\CLK")); SigSpec clk = sigmap(cell->getPort(ID::CLK));
SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]); SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]); SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]); SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]);
SigSpec addr = sigmap(cell->getPort("\\ADDR")); SigSpec addr = sigmap(cell->getPort(ID::ADDR));
SigSpec data = sigmap(cell->getPort("\\DATA")); SigSpec data = sigmap(cell->getPort(ID::DATA));
SigSpec en = sigmap(cell->getPort("\\EN")); SigSpec en = sigmap(cell->getPort(ID::EN));
if (!en.is_fully_zero()) if (!en.is_fully_zero())
{ {
@ -178,13 +178,13 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
std::stringstream sstr; std::stringstream sstr;
sstr << "$mem$" << memory->name.str() << "$" << (autoidx++); sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
Cell *mem = module->addCell(sstr.str(), "$mem"); Cell *mem = module->addCell(sstr.str(), ID($mem));
mem->parameters["\\MEMID"] = Const(memory->name.str()); mem->parameters[ID::MEMID] = Const(memory->name.str());
mem->parameters["\\WIDTH"] = Const(memory->width); mem->parameters[ID::WIDTH] = Const(memory->width);
mem->parameters["\\OFFSET"] = Const(memory->start_offset); mem->parameters[ID::OFFSET] = Const(memory->start_offset);
mem->parameters["\\SIZE"] = Const(memory->size); mem->parameters[ID::SIZE] = Const(memory->size);
mem->parameters["\\ABITS"] = Const(addr_bits); mem->parameters[ID::ABITS] = Const(addr_bits);
mem->parameters["\\INIT"] = init_data; mem->parameters[ID::INIT] = init_data;
log_assert(sig_wr_clk.size() == wr_ports); log_assert(sig_wr_clk.size() == wr_ports);
log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const()); log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
@ -193,14 +193,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
log_assert(sig_wr_data.size() == wr_ports * memory->width); log_assert(sig_wr_data.size() == wr_ports * memory->width);
log_assert(sig_wr_en.size() == wr_ports * memory->width); log_assert(sig_wr_en.size() == wr_ports * memory->width);
mem->parameters["\\WR_PORTS"] = Const(wr_ports); mem->parameters[ID::WR_PORTS] = Const(wr_ports);
mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0; mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0; mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
mem->setPort("\\WR_CLK", sig_wr_clk); mem->setPort(ID::WR_CLK, sig_wr_clk);
mem->setPort("\\WR_ADDR", sig_wr_addr); mem->setPort(ID::WR_ADDR, sig_wr_addr);
mem->setPort("\\WR_DATA", sig_wr_data); mem->setPort(ID::WR_DATA, sig_wr_data);
mem->setPort("\\WR_EN", sig_wr_en); mem->setPort(ID::WR_EN, sig_wr_en);
log_assert(sig_rd_clk.size() == rd_ports); log_assert(sig_rd_clk.size() == rd_ports);
log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const()); log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
@ -208,15 +208,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
log_assert(sig_rd_addr.size() == rd_ports * addr_bits); log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
log_assert(sig_rd_data.size() == rd_ports * memory->width); log_assert(sig_rd_data.size() == rd_ports * memory->width);
mem->parameters["\\RD_PORTS"] = Const(rd_ports); mem->parameters[ID::RD_PORTS] = Const(rd_ports);
mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0; mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0; mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0; mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
mem->setPort("\\RD_CLK", sig_rd_clk); mem->setPort(ID::RD_CLK, sig_rd_clk);
mem->setPort("\\RD_ADDR", sig_rd_addr); mem->setPort(ID::RD_ADDR, sig_rd_addr);
mem->setPort("\\RD_DATA", sig_rd_data); mem->setPort(ID::RD_DATA, sig_rd_data);
mem->setPort("\\RD_EN", sig_rd_en); mem->setPort(ID::RD_EN, sig_rd_en);
// Copy attributes from RTLIL memory to $mem // Copy attributes from RTLIL memory to $mem
for (auto attr : memory->attributes) for (auto attr : memory->attributes)

92
passes/memory/memory_dff.cc
View file

@ -39,10 +39,10 @@ struct MemoryDffWorker
MemoryDffWorker(Module *module) : module(module), sigmap(module) MemoryDffWorker(Module *module) : module(module), sigmap(module)
{ {
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->attributes.count("\\init") == 0) if (wire->attributes.count(ID::init) == 0)
continue; continue;
SigSpec sig = sigmap(wire); SigSpec sig = sigmap(wire);
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++) for (int i = 0; i < GetSize(sig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sig[i]); init_bits.insert(sig[i]);
@ -66,8 +66,8 @@ struct MemoryDffWorker
if (after && forward_merged_dffs.count(cell)) if (after && forward_merged_dffs.count(cell))
continue; continue;
SigSpec this_clk = cell->getPort("\\CLK"); SigSpec this_clk = cell->getPort(ID::CLK);
bool this_clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool(); bool this_clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (invbits.count(this_clk)) { if (invbits.count(this_clk)) {
this_clk = invbits.at(this_clk); this_clk = invbits.at(this_clk);
@ -81,10 +81,10 @@ struct MemoryDffWorker
continue; continue;
} }
RTLIL::SigSpec q_norm = cell->getPort(after ? "\\D" : "\\Q"); RTLIL::SigSpec q_norm = cell->getPort(after ? ID::D : ID::Q);
sigmap.apply(q_norm); sigmap.apply(q_norm);
RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? "\\Q" : "\\D")); RTLIL::SigSpec d = q_norm.extract(bit, &cell->getPort(after ? ID::Q : ID::D));
if (d.size() != 1) if (d.size() != 1)
continue; continue;
@ -113,19 +113,19 @@ struct MemoryDffWorker
bool clk_polarity = 0; bool clk_polarity = 0;
candidate_dffs.clear(); candidate_dffs.clear();
RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) { if (!find_sig_before_dff(sig_addr, clk, clk_polarity)) {
log("no (compatible) $dff for address input found.\n"); log("no (compatible) $dff for address input found.\n");
return; return;
} }
RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
if (!find_sig_before_dff(sig_data, clk, clk_polarity)) { if (!find_sig_before_dff(sig_data, clk, clk_polarity)) {
log("no (compatible) $dff for data input found.\n"); log("no (compatible) $dff for data input found.\n");
return; return;
} }
RTLIL::SigSpec sig_en = cell->getPort("\\EN"); RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
if (!find_sig_before_dff(sig_en, clk, clk_polarity)) { if (!find_sig_before_dff(sig_en, clk, clk_polarity)) {
log("no (compatible) $dff for enable input found.\n"); log("no (compatible) $dff for enable input found.\n");
return; return;
@ -136,12 +136,12 @@ struct MemoryDffWorker
for (auto cell : candidate_dffs) for (auto cell : candidate_dffs)
forward_merged_dffs.insert(cell); forward_merged_dffs.insert(cell);
cell->setPort("\\CLK", clk); cell->setPort(ID::CLK, clk);
cell->setPort("\\ADDR", sig_addr); cell->setPort(ID::ADDR, sig_addr);
cell->setPort("\\DATA", sig_data); cell->setPort(ID::DATA, sig_data);
cell->setPort("\\EN", sig_en); cell->setPort(ID::EN, sig_en);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
log("merged $dff to cell.\n"); log("merged $dff to cell.\n");
return; return;
@ -161,10 +161,10 @@ struct MemoryDffWorker
RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size()); RTLIL::SigSpec new_sig = module->addWire(sstr.str(), sig.size());
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == "$dff") { if (cell->type == ID($dff)) {
RTLIL::SigSpec new_q = cell->getPort("\\Q"); RTLIL::SigSpec new_q = cell->getPort(ID::Q);
new_q.replace(sig, new_sig); new_q.replace(sig, new_sig);
cell->setPort("\\Q", new_q); cell->setPort(ID::Q, new_q);
} }
} }
@ -175,7 +175,7 @@ struct MemoryDffWorker
bool clk_polarity = 0; bool clk_polarity = 0;
RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx); RTLIL::SigSpec clk_data = RTLIL::SigSpec(RTLIL::State::Sx);
RTLIL::SigSpec sig_data = cell->getPort("\\DATA"); RTLIL::SigSpec sig_data = cell->getPort(ID::DATA);
for (auto bit : sigmap(sig_data)) for (auto bit : sigmap(sig_data))
if (sigbit_users_count[bit] > 1) if (sigbit_users_count[bit] > 1)
@ -202,12 +202,12 @@ struct MemoryDffWorker
std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; })) std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
{ {
disconnect_dff(sig_data); disconnect_dff(sig_data);
cell->setPort("\\CLK", clk_data); cell->setPort(ID::CLK, clk_data);
cell->setPort("\\EN", en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en); cell->setPort(ID::EN, en.size() > 1 ? module->ReduceAnd(NEW_ID, en) : en);
cell->setPort("\\DATA", sig_data); cell->setPort(ID::DATA, sig_data);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff with rd enable to cell.\n"); log("merged data $dff with rd enable to cell.\n");
return; return;
} }
@ -217,12 +217,12 @@ struct MemoryDffWorker
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx)) if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx))
{ {
disconnect_dff(sig_data); disconnect_dff(sig_data);
cell->setPort("\\CLK", clk_data); cell->setPort(ID::CLK, clk_data);
cell->setPort("\\EN", State::S1); cell->setPort(ID::EN, State::S1);
cell->setPort("\\DATA", sig_data); cell->setPort(ID::DATA, sig_data);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(0); cell->parameters[ID::TRANSPARENT] = RTLIL::Const(0);
log("merged data $dff to cell.\n"); log("merged data $dff to cell.\n");
return; return;
} }
@ -230,16 +230,16 @@ struct MemoryDffWorker
skip_ff_after_read_merging:; skip_ff_after_read_merging:;
RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx); RTLIL::SigSpec clk_addr = RTLIL::SigSpec(RTLIL::State::Sx);
RTLIL::SigSpec sig_addr = cell->getPort("\\ADDR"); RTLIL::SigSpec sig_addr = cell->getPort(ID::ADDR);
if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) && if (find_sig_before_dff(sig_addr, clk_addr, clk_polarity) &&
clk_addr != RTLIL::SigSpec(RTLIL::State::Sx)) clk_addr != RTLIL::SigSpec(RTLIL::State::Sx))
{ {
cell->setPort("\\CLK", clk_addr); cell->setPort(ID::CLK, clk_addr);
cell->setPort("\\EN", State::S1); cell->setPort(ID::EN, State::S1);
cell->setPort("\\ADDR", sig_addr); cell->setPort(ID::ADDR, sig_addr);
cell->parameters["\\CLK_ENABLE"] = RTLIL::Const(1); cell->parameters[ID::CLK_ENABLE] = RTLIL::Const(1);
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity);
cell->parameters["\\TRANSPARENT"] = RTLIL::Const(1); cell->parameters[ID::TRANSPARENT] = RTLIL::Const(1);
log("merged address $dff to cell.\n"); log("merged address $dff to cell.\n");
return; return;
} }
@ -256,18 +256,18 @@ struct MemoryDffWorker
} }
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type == "$dff") if (cell->type == ID($dff))
dff_cells.push_back(cell); dff_cells.push_back(cell);
if (cell->type == "$mux") { if (cell->type == ID($mux)) {
mux_cells_a[sigmap(cell->getPort(ID::A))] = cell; mux_cells_a[sigmap(cell->getPort(ID::A))] = cell;
mux_cells_b[sigmap(cell->getPort(ID::B))] = cell; mux_cells_b[sigmap(cell->getPort(ID::B))] = cell;
} }
if (cell->type.in("$not", "$_NOT_") || (cell->type == "$logic_not" && GetSize(cell->getPort(ID::A)) == 1)) { if (cell->type.in(ID($not), ID($_NOT_)) || (cell->type == ID($logic_not) && GetSize(cell->getPort(ID::A)) == 1)) {
SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y); SigSpec sig_y = cell->getPort(ID::Y);
if (cell->type == "$not") if (cell->type == ID($not))
sig_a.extend_u0(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
if (cell->type == "$logic_not") if (cell->type == ID($logic_not))
sig_y.extend_u0(1); sig_y.extend_u0(1);
for (int i = 0; i < GetSize(sig_y); i++) for (int i = 0; i < GetSize(sig_y); i++)
invbits[sig_y[i]] = sig_a[i]; invbits[sig_y[i]] = sig_a[i];
@ -279,12 +279,12 @@ struct MemoryDffWorker
} }
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$memwr" && !cell->parameters["\\CLK_ENABLE"].as_bool()) if (cell->type == ID($memwr) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_wr_cell(cell); handle_wr_cell(cell);
if (!flag_wr_only) if (!flag_wr_only)
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$memrd" && !cell->parameters["\\CLK_ENABLE"].as_bool()) if (cell->type == ID($memrd) && !cell->parameters[ID::CLK_ENABLE].as_bool())
handle_rd_cell(cell); handle_rd_cell(cell);
} }
}; };

116
passes/memory/memory_map.cc
View file

@ -81,15 +81,15 @@ struct MemoryMapWorker
std::set<int> static_ports; std::set<int> static_ports;
std::map<int, RTLIL::SigSpec> static_cells_map; std::map<int, RTLIL::SigSpec> static_cells_map;
int wr_ports = cell->parameters["\\WR_PORTS"].as_int(); int wr_ports = cell->parameters[ID::WR_PORTS].as_int();
int rd_ports = cell->parameters["\\RD_PORTS"].as_int(); int rd_ports = cell->parameters[ID::RD_PORTS].as_int();
int mem_size = cell->parameters["\\SIZE"].as_int(); int mem_size = cell->parameters[ID::SIZE].as_int();
int mem_width = cell->parameters["\\WIDTH"].as_int(); int mem_width = cell->parameters[ID::WIDTH].as_int();
int mem_offset = cell->parameters["\\OFFSET"].as_int(); int mem_offset = cell->parameters[ID::OFFSET].as_int();
int mem_abits = cell->parameters["\\ABITS"].as_int(); int mem_abits = cell->parameters[ID::ABITS].as_int();
SigSpec init_data = cell->getParam("\\INIT"); SigSpec init_data = cell->getParam(ID::INIT);
init_data.extend_u0(mem_size*mem_width, true); init_data.extend_u0(mem_size*mem_width, true);
// delete unused memory cell // delete unused memory cell
@ -99,22 +99,22 @@ struct MemoryMapWorker
} }
// all write ports must share the same clock // all write ports must share the same clock
RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK"); RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"]; RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"]; RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
clocks_pol.bits.resize(wr_ports); clocks_pol.bits.resize(wr_ports);
clocks_en.bits.resize(wr_ports); clocks_en.bits.resize(wr_ports);
RTLIL::SigSpec refclock; RTLIL::SigSpec refclock;
RTLIL::State refclock_pol = RTLIL::State::Sx; RTLIL::State refclock_pol = RTLIL::State::Sx;
for (int i = 0; i < clocks.size(); i++) { for (int i = 0; i < clocks.size(); i++) {
RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width); RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width);
if (wr_en.is_fully_const() && !wr_en.as_bool()) { if (wr_en.is_fully_const() && !wr_en.as_bool()) {
static_ports.insert(i); static_ports.insert(i);
continue; continue;
} }
if (clocks_en.bits[i] != RTLIL::State::S1) { if (clocks_en.bits[i] != RTLIL::State::S1) {
RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits); RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits);
RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width); RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width);
if (wr_addr.is_fully_const()) { if (wr_addr.is_fully_const()) {
// FIXME: Actually we should check for wr_en.is_fully_const() also and // FIXME: Actually we should check for wr_en.is_fully_const() also and
// create a $adff cell with this ports wr_en input as reset pin when wr_en // create a $adff cell with this ports wr_en input as reset pin when wr_en
@ -155,21 +155,21 @@ struct MemoryMapWorker
} }
else else
{ {
RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff"); RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff));
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
if (clocks_pol.bits.size() > 0) { if (clocks_pol.bits.size() > 0) {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]);
c->setPort("\\CLK", clocks.extract(0, 1)); c->setPort(ID::CLK, clocks.extract(0, 1));
} else { } else {
c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1); c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0)); c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
} }
RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width); RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
data_reg_in.push_back(RTLIL::SigSpec(w_in)); data_reg_in.push_back(RTLIL::SigSpec(w_in));
c->setPort("\\D", data_reg_in.back()); c->setPort(ID::D, data_reg_in.back());
std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i); std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i);
if (module->wires_.count(w_out_name) > 0) if (module->wires_.count(w_out_name) > 0)
w_out_name = genid(cell->name, "", i, "$q"); w_out_name = genid(cell->name, "", i, "$q");
@ -177,10 +177,10 @@ struct MemoryMapWorker
SigSpec w_init = init_data.extract(i*mem_width, mem_width); SigSpec w_init = init_data.extract(i*mem_width, mem_width);
if (!w_init.is_fully_undef()) if (!w_init.is_fully_undef())
w_out->attributes["\\init"] = w_init.as_const(); w_out->attributes[ID::init] = w_init.as_const();
data_reg_out.push_back(RTLIL::SigSpec(w_out)); data_reg_out.push_back(RTLIL::SigSpec(w_out));
c->setPort("\\Q", data_reg_out.back()); c->setPort(ID::Q, data_reg_out.back());
} }
} }
@ -188,55 +188,55 @@ struct MemoryMapWorker
int count_dff = 0, count_mux = 0, count_wrmux = 0; int count_dff = 0, count_mux = 0, count_wrmux = 0;
for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++) for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++)
{ {
RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits); RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits);
if (mem_offset) if (mem_offset)
rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr))); rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
std::vector<RTLIL::SigSpec> rd_signals; std::vector<RTLIL::SigSpec> rd_signals;
rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width)); rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width));
if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1) if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1)
{ {
RTLIL::Cell *dff_cell = nullptr; RTLIL::Cell *dff_cell = nullptr;
if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1) if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1)
{ {
dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits); dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits);
dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
dff_cell->setPort("\\D", rd_addr); dff_cell->setPort(ID::D, rd_addr);
count_dff++; count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits); RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
dff_cell->setPort("\\Q", RTLIL::SigSpec(w)); dff_cell->setPort(ID::Q, RTLIL::SigSpec(w));
rd_addr = RTLIL::SigSpec(w); rd_addr = RTLIL::SigSpec(w);
} }
else else
{ {
dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff"); dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]); dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1)); dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
dff_cell->setPort("\\Q", rd_signals.back()); dff_cell->setPort(ID::Q, rd_signals.back());
count_dff++; count_dff++;
RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width); RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
rd_signals.clear(); rd_signals.clear();
rd_signals.push_back(RTLIL::SigSpec(w)); rd_signals.push_back(RTLIL::SigSpec(w));
dff_cell->setPort("\\D", rd_signals.back()); dff_cell->setPort(ID::D, rd_signals.back());
} }
SigBit en_bit = cell->getPort("\\RD_EN").extract(i); SigBit en_bit = cell->getPort(ID::RD_EN).extract(i);
if (en_bit != State::S1) { if (en_bit != State::S1) {
SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i), SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit); dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit);
dff_cell->setPort("\\D", new_d); dff_cell->setPort(ID::D, new_d);
} }
} }
@ -246,8 +246,8 @@ struct MemoryMapWorker
for (size_t k = 0; k < rd_signals.size(); k++) for (size_t k = 0; k < rd_signals.size(); k++)
{ {
RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux"); RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux));
c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"]; c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
c->setPort(ID::Y, rd_signals[k]); c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1)); c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
count_mux++; count_mux++;
@ -275,11 +275,11 @@ struct MemoryMapWorker
RTLIL::SigSpec sig = data_reg_out[i]; RTLIL::SigSpec sig = data_reg_out[i];
for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++) for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++)
{ {
RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits); RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits);
RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width); RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width);
RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width); RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width);
if (mem_offset) if (mem_offset)
wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr))); wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
@ -303,12 +303,12 @@ struct MemoryMapWorker
if (wr_bit != State::S1) if (wr_bit != State::S1)
{ {
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and"); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and));
c->parameters["\\A_SIGNED"] = RTLIL::Const(0); c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
c->parameters["\\B_SIGNED"] = RTLIL::Const(0); c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
c->parameters["\\A_WIDTH"] = RTLIL::Const(1); c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
c->parameters["\\B_WIDTH"] = RTLIL::Const(1); c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
c->parameters["\\Y_WIDTH"] = RTLIL::Const(1); c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
c->setPort(ID::A, w); c->setPort(ID::A, w);
c->setPort(ID::B, wr_bit); c->setPort(ID::B, wr_bit);
@ -316,8 +316,8 @@ struct MemoryMapWorker
c->setPort(ID::Y, RTLIL::SigSpec(w)); c->setPort(ID::Y, RTLIL::SigSpec(w));
} }
RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux"); RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux));
c->parameters["\\WIDTH"] = wr_width; c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width)); c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, wr_data.extract(wr_offset, wr_width)); c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
c->setPort(ID::S, RTLIL::SigSpec(w)); c->setPort(ID::S, RTLIL::SigSpec(w));
@ -343,7 +343,7 @@ struct MemoryMapWorker
{ {
std::vector<RTLIL::Cell*> cells; std::vector<RTLIL::Cell*> cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$mem" && design->selected(module, cell)) if (cell->type == ID($mem))
cells.push_back(cell); cells.push_back(cell);
for (auto cell : cells) for (auto cell : cells)
handle_cell(cell); handle_cell(cell);

20
passes/memory/memory_memx.cc
View file

@ -47,18 +47,18 @@ struct MemoryMemxPass : public Pass {
vector<Cell*> mem_port_cells; vector<Cell*> mem_port_cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type.in("$memrd", "$memwr")) if (cell->type.in(ID($memrd), ID($memwr)))
mem_port_cells.push_back(cell); mem_port_cells.push_back(cell);
for (auto cell : mem_port_cells) for (auto cell : mem_port_cells)
{ {
IdString memid = cell->getParam("\\MEMID").decode_string(); IdString memid = cell->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid); RTLIL::Memory *mem = module->memories.at(memid);
int lowest_addr = mem->start_offset; int lowest_addr = mem->start_offset;
int highest_addr = mem->start_offset + mem->size - 1; int highest_addr = mem->start_offset + mem->size - 1;
SigSpec addr = cell->getPort("\\ADDR"); SigSpec addr = cell->getPort(ID::ADDR);
addr.extend_u0(32); addr.extend_u0(32);
SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1})); SigSpec addr_ok = module->Nex(NEW_ID, module->ReduceXor(NEW_ID, addr), module->ReduceXor(NEW_ID, {addr, State::S1}));
@ -66,23 +66,23 @@ struct MemoryMemxPass : public Pass {
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr)); addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Ge(NEW_ID, addr, lowest_addr));
addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr)); addr_ok = module->LogicAnd(NEW_ID, addr_ok, module->Le(NEW_ID, addr, highest_addr));
if (cell->type == "$memrd") if (cell->type == ID($memrd))
{ {
if (cell->getParam("\\CLK_ENABLE").as_bool()) if (cell->getParam(ID::CLK_ENABLE).as_bool())
log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n", log_error("Cell %s.%s (%s) has an enabled clock. Clocked $memrd cells are not supported by memory_memx!\n",
log_id(module), log_id(cell), log_id(cell->type)); log_id(module), log_id(cell), log_id(cell->type));
SigSpec rdata = cell->getPort("\\DATA"); SigSpec rdata = cell->getPort(ID::DATA);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata)); Wire *raw_rdata = module->addWire(NEW_ID, GetSize(rdata));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata); module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(rdata)), raw_rdata, addr_ok, rdata);
cell->setPort("\\DATA", raw_rdata); cell->setPort(ID::DATA, raw_rdata);
} }
if (cell->type == "$memwr") if (cell->type == ID($memwr))
{ {
SigSpec en = cell->getPort("\\EN"); SigSpec en = cell->getPort(ID::EN);
en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en))); en = module->And(NEW_ID, en, addr_ok.repeat(GetSize(en)));
cell->setPort("\\EN", en); cell->setPort(ID::EN, en);
} }
} }
} }

40
passes/memory/memory_nordff.cc
View file

@ -52,19 +52,19 @@ struct MemoryNordffPass : public Pass {
for (auto module : design->selected_modules()) for (auto module : design->selected_modules())
for (auto cell : vector<Cell*>(module->selected_cells())) for (auto cell : vector<Cell*>(module->selected_cells()))
{ {
if (cell->type != "$mem") if (cell->type != ID($mem))
continue; continue;
int rd_ports = cell->getParam("\\RD_PORTS").as_int(); int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
SigSpec rd_addr = cell->getPort("\\RD_ADDR"); SigSpec rd_addr = cell->getPort(ID::RD_ADDR);
SigSpec rd_data = cell->getPort("\\RD_DATA"); SigSpec rd_data = cell->getPort(ID::RD_DATA);
SigSpec rd_clk = cell->getPort("\\RD_CLK"); SigSpec rd_clk = cell->getPort(ID::RD_CLK);
SigSpec rd_en = cell->getPort("\\RD_EN"); SigSpec rd_en = cell->getPort(ID::RD_EN);
Const rd_clk_enable = cell->getParam("\\RD_CLK_ENABLE"); Const rd_clk_enable = cell->getParam(ID::RD_CLK_ENABLE);
Const rd_clk_polarity = cell->getParam("\\RD_CLK_POLARITY"); Const rd_clk_polarity = cell->getParam(ID::RD_CLK_POLARITY);
for (int i = 0; i < rd_ports; i++) for (int i = 0; i < rd_ports; i++)
{ {
@ -72,11 +72,11 @@ struct MemoryNordffPass : public Pass {
if (clk_enable) if (clk_enable)
{ {
bool clk_polarity = cell->getParam("\\RD_CLK_POLARITY")[i] == State::S1; bool clk_polarity = cell->getParam(ID::RD_CLK_POLARITY)[i] == State::S1;
bool transparent = cell->getParam("\\RD_TRANSPARENT")[i] == State::S1; bool transparent = cell->getParam(ID::RD_TRANSPARENT)[i] == State::S1;
SigSpec clk = cell->getPort("\\RD_CLK")[i] ; SigSpec clk = cell->getPort(ID::RD_CLK)[i] ;
SigSpec en = cell->getPort("\\RD_EN")[i]; SigSpec en = cell->getPort(ID::RD_EN)[i];
Cell *c; Cell *c;
if (transparent) if (transparent)
@ -108,12 +108,12 @@ struct MemoryNordffPass : public Pass {
rd_clk_polarity[i] = State::S1; rd_clk_polarity[i] = State::S1;
} }
cell->setPort("\\RD_ADDR", rd_addr); cell->setPort(ID::RD_ADDR, rd_addr);
cell->setPort("\\RD_DATA", rd_data); cell->setPort(ID::RD_DATA, rd_data);
cell->setPort("\\RD_CLK", rd_clk); cell->setPort(ID::RD_CLK, rd_clk);
cell->setPort("\\RD_EN", rd_en); cell->setPort(ID::RD_EN, rd_en);
cell->setParam("\\RD_CLK_ENABLE", rd_clk_enable); cell->setParam(ID::RD_CLK_ENABLE, rd_clk_enable);
cell->setParam("\\RD_CLK_POLARITY", rd_clk_polarity); cell->setParam(ID::RD_CLK_POLARITY, rd_clk_polarity);
} }
} }
} MemoryNordffPass; } MemoryNordffPass;

138
passes/memory/memory_share.cc
View file

@ -27,11 +27,11 @@ PRIVATE_NAMESPACE_BEGIN
bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b) bool memcells_cmp(RTLIL::Cell *a, RTLIL::Cell *b)
{ {
if (a->type == "$memrd" && b->type == "$memrd") if (a->type == ID($memrd) && b->type == ID($memrd))
return a->name < b->name; return a->name < b->name;
if (a->type == "$memrd" || b->type == "$memrd") if (a->type == ID($memrd) || b->type == ID($memrd))
return (a->type == "$memrd") < (b->type == "$memrd"); return (a->type == ID($memrd)) < (b->type == ID($memrd));
return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int(); return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
} }
struct MemoryShareWorker struct MemoryShareWorker
@ -155,7 +155,7 @@ struct MemoryShareWorker
{ {
bool ignore_data_port = false; bool ignore_data_port = false;
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A)); std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B)); std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
@ -173,13 +173,13 @@ struct MemoryShareWorker
continue; continue;
} }
if (cell->type.in("$memwr", "$memrd") && if (cell->type.in(ID($memwr), ID($memrd)) &&
cell->parameters.at("\\MEMID").decode_string() == memid) cell->parameters.at(ID::MEMID).decode_string() == memid)
ignore_data_port = true; ignore_data_port = true;
for (auto conn : cell->connections()) for (auto conn : cell->connections())
{ {
if (ignore_data_port && conn.first == "\\DATA") if (ignore_data_port && conn.first == ID::DATA)
continue; continue;
std::vector<RTLIL::SigBit> bits = sigmap(conn.second); std::vector<RTLIL::SigBit> bits = sigmap(conn.second);
non_feedback_nets.insert(bits.begin(), bits.end()); non_feedback_nets.insert(bits.begin(), bits.end());
@ -204,11 +204,11 @@ struct MemoryShareWorker
for (auto cell : rd_ports) for (auto cell : rd_ports)
{ {
if (cell->parameters.at("\\CLK_ENABLE").as_bool()) if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue; continue;
RTLIL::SigSpec sig_addr = sigmap(cell->getPort("\\ADDR")); RTLIL::SigSpec sig_addr = sigmap(cell->getPort(ID::ADDR));
std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort("\\DATA")); std::vector<RTLIL::SigBit> sig_data = sigmap(cell->getPort(ID::DATA));
for (int i = 0; i < int(sig_data.size()); i++) for (int i = 0; i < int(sig_data.size()); i++)
if (non_feedback_nets.count(sig_data[i])) if (non_feedback_nets.count(sig_data[i]))
@ -228,14 +228,14 @@ struct MemoryShareWorker
for (auto cell : wr_ports) for (auto cell : wr_ports)
{ {
RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort("\\ADDR")); RTLIL::SigSpec sig_addr = sigmap_xmux(cell->getPort(ID::ADDR));
if (!async_rd_bits.count(sig_addr)) if (!async_rd_bits.count(sig_addr))
continue; continue;
log(" Analyzing write port %s.\n", log_id(cell)); log(" Analyzing write port %s.\n", log_id(cell));
std::vector<RTLIL::SigBit> cell_data = cell->getPort("\\DATA"); std::vector<RTLIL::SigBit> cell_data = cell->getPort(ID::DATA);
std::vector<RTLIL::SigBit> cell_en = cell->getPort("\\EN"); std::vector<RTLIL::SigBit> cell_en = cell->getPort(ID::EN);
int created_conditions = 0; int created_conditions = 0;
for (int i = 0; i < int(cell_data.size()); i++) for (int i = 0; i < int(cell_data.size()); i++)
@ -250,7 +250,7 @@ struct MemoryShareWorker
if (created_conditions) { if (created_conditions) {
log(" Added enable logic for %d different cases.\n", created_conditions); log(" Added enable logic for %d different cases.\n", created_conditions);
cell->setPort("\\EN", cell_en); cell->setPort(ID::EN, cell_en);
} }
} }
} }
@ -368,15 +368,15 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++) for (int i = 0; i < int(wr_ports.size()); i++)
{ {
RTLIL::Cell *cell = wr_ports.at(i); RTLIL::Cell *cell = wr_ports.at(i);
RTLIL::SigSpec addr = sigmap_xmux(cell->getPort("\\ADDR")); RTLIL::SigSpec addr = sigmap_xmux(cell->getPort(ID::ADDR));
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
(cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{ {
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
cache_clk = sigmap(cell->getPort("\\CLK")); cache_clk = sigmap(cell->getPort(ID::CLK));
last_port_by_addr.clear(); last_port_by_addr.clear();
if (cache_clk_enable) if (cache_clk_enable)
@ -388,7 +388,7 @@ struct MemoryShareWorker
log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr)); log(" Port %d (%s) has addr %s.\n", i, log_id(cell), log_signal(addr));
log(" Active bits: "); log(" Active bits: ");
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--) { for (int k = int(en_bits.size())-1; k >= 0; k--) {
active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0; active_bits_on_port[i][k] = en_bits[k].wire != NULL || en_bits[k].data != RTLIL::State::S0;
@ -410,13 +410,13 @@ struct MemoryShareWorker
// Force this ports addr input to addr directly (skip don't care muxes) // Force this ports addr input to addr directly (skip don't care muxes)
cell->setPort("\\ADDR", addr); cell->setPort(ID::ADDR, addr);
// If any of the ports between `last_i' and `i' write to the same address, this // If any of the ports between `last_i' and `i' write to the same address, this
// will have priority over whatever `last_i` wrote. So we need to revisit those // will have priority over whatever `last_i` wrote. So we need to revisit those
// ports and mask the EN bits accordingly. // ports and mask the EN bits accordingly.
RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort("\\EN")); RTLIL::SigSpec merged_en = sigmap(wr_ports[last_i]->getPort(ID::EN));
for (int j = last_i+1; j < i; j++) for (int j = last_i+1; j < i; j++)
{ {
@ -431,20 +431,20 @@ struct MemoryShareWorker
found_overlapping_bits_i_j: found_overlapping_bits_i_j:
log(" Creating collosion-detect logic for port %d.\n", j); log(" Creating collosion-detect logic for port %d.\n", j);
RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID); RTLIL::SigSpec is_same_addr = module->addWire(NEW_ID);
module->addEq(NEW_ID, addr, wr_ports[j]->getPort("\\ADDR"), is_same_addr); module->addEq(NEW_ID, addr, wr_ports[j]->getPort(ID::ADDR), is_same_addr);
merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort("\\EN"))); merged_en = mask_en_grouped(is_same_addr, merged_en, sigmap(wr_ports[j]->getPort(ID::EN)));
} }
} }
// Then we need to merge the (masked) EN and the DATA signals. // Then we need to merge the (masked) EN and the DATA signals.
RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort("\\DATA"); RTLIL::SigSpec merged_data = wr_ports[last_i]->getPort(ID::DATA);
if (found_overlapping_bits) { if (found_overlapping_bits) {
log(" Creating logic for merging DATA and EN ports.\n"); log(" Creating logic for merging DATA and EN ports.\n");
merge_en_data(merged_en, merged_data, sigmap(cell->getPort("\\EN")), sigmap(cell->getPort("\\DATA"))); merge_en_data(merged_en, merged_data, sigmap(cell->getPort(ID::EN)), sigmap(cell->getPort(ID::DATA)));
} else { } else {
RTLIL::SigSpec cell_en = sigmap(cell->getPort("\\EN")); RTLIL::SigSpec cell_en = sigmap(cell->getPort(ID::EN));
RTLIL::SigSpec cell_data = sigmap(cell->getPort("\\DATA")); RTLIL::SigSpec cell_data = sigmap(cell->getPort(ID::DATA));
for (int k = 0; k < int(en_bits.size()); k++) for (int k = 0; k < int(en_bits.size()); k++)
if (!active_bits_on_port[last_i][k]) { if (!active_bits_on_port[last_i][k]) {
merged_en.replace(k, cell_en.extract(k, 1)); merged_en.replace(k, cell_en.extract(k, 1));
@ -454,14 +454,14 @@ struct MemoryShareWorker
// Connect the new EN and DATA signals and remove the old write port. // Connect the new EN and DATA signals and remove the old write port.
cell->setPort("\\EN", merged_en); cell->setPort(ID::EN, merged_en);
cell->setPort("\\DATA", merged_data); cell->setPort(ID::DATA, merged_data);
module->remove(wr_ports[last_i]); module->remove(wr_ports[last_i]);
wr_ports[last_i] = NULL; wr_ports[last_i] = NULL;
log(" Active bits: "); log(" Active bits: ");
std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort("\\EN")); std::vector<RTLIL::SigBit> en_bits = sigmap(cell->getPort(ID::EN));
active_bits_on_port.push_back(std::vector<bool>(en_bits.size())); active_bits_on_port.push_back(std::vector<bool>(en_bits.size()));
for (int k = int(en_bits.size())-1; k >= 0; k--) for (int k = int(en_bits.size())-1; k >= 0; k--)
log("%c", active_bits_on_port[i][k] ? '1' : '0'); log("%c", active_bits_on_port[i][k] ? '1' : '0');
@ -500,7 +500,7 @@ struct MemoryShareWorker
std::set<int> considered_port_pairs; std::set<int> considered_port_pairs;
for (int i = 0; i < int(wr_ports.size()); i++) { for (int i = 0; i < int(wr_ports.size()); i++) {
std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); std::vector<RTLIL::SigBit> bits = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
for (auto bit : bits) for (auto bit : bits)
if (bit == RTLIL::State::S1) if (bit == RTLIL::State::S1)
goto port_is_always_active; goto port_is_always_active;
@ -519,13 +519,13 @@ struct MemoryShareWorker
{ {
RTLIL::Cell *cell = wr_ports.at(i); RTLIL::Cell *cell = wr_ports.at(i);
if (cell->parameters.at("\\CLK_ENABLE").as_bool() != cache_clk_enable || if (cell->parameters.at(ID::CLK_ENABLE).as_bool() != cache_clk_enable ||
(cache_clk_enable && (sigmap(cell->getPort("\\CLK")) != cache_clk || (cache_clk_enable && (sigmap(cell->getPort(ID::CLK)) != cache_clk ||
cell->parameters.at("\\CLK_POLARITY").as_bool() != cache_clk_polarity))) cell->parameters.at(ID::CLK_POLARITY).as_bool() != cache_clk_polarity)))
{ {
cache_clk_enable = cell->parameters.at("\\CLK_ENABLE").as_bool(); cache_clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
cache_clk_polarity = cell->parameters.at("\\CLK_POLARITY").as_bool(); cache_clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
cache_clk = sigmap(cell->getPort("\\CLK")); cache_clk = sigmap(cell->getPort(ID::CLK));
} }
else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i)) else if (i > 0 && considered_ports.count(i-1) && considered_ports.count(i))
considered_port_pairs.insert(i); considered_port_pairs.insert(i);
@ -554,7 +554,7 @@ struct MemoryShareWorker
for (int i = 0; i < int(wr_ports.size()); i++) for (int i = 0; i < int(wr_ports.size()); i++)
if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1)) if (considered_port_pairs.count(i) || considered_port_pairs.count(i+1))
{ {
RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); RTLIL::SigSpec sig = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig)); port_to_sat_variable[i] = ez->expression(ez->OpOr, satgen.importSigSpec(sig));
std::vector<RTLIL::SigBit> bits = sig; std::vector<RTLIL::SigBit> bits = sig;
@ -564,7 +564,7 @@ struct MemoryShareWorker
while (!bits_queue.empty()) while (!bits_queue.empty())
{ {
for (auto bit : bits_queue) for (auto bit : bits_queue)
if (bit.wire && bit.wire->get_bool_attribute("\\onehot")) if (bit.wire && bit.wire->get_bool_attribute(ID::onehot))
one_hot_wires.insert(bit.wire); one_hot_wires.insert(bit.wire);
pool<ModWalker::PortBit> portbits; pool<ModWalker::PortBit> portbits;
@ -609,13 +609,13 @@ struct MemoryShareWorker
log(" Merging port %d into port %d.\n", i-1, i); log(" Merging port %d into port %d.\n", i-1, i);
port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i)); port_to_sat_variable.at(i) = ez->OR(port_to_sat_variable.at(i-1), port_to_sat_variable.at(i));
RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort("\\ADDR"); RTLIL::SigSpec last_addr = wr_ports[i-1]->getPort(ID::ADDR);
RTLIL::SigSpec last_data = wr_ports[i-1]->getPort("\\DATA"); RTLIL::SigSpec last_data = wr_ports[i-1]->getPort(ID::DATA);
std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort("\\EN")); std::vector<RTLIL::SigBit> last_en = modwalker.sigmap(wr_ports[i-1]->getPort(ID::EN));
RTLIL::SigSpec this_addr = wr_ports[i]->getPort("\\ADDR"); RTLIL::SigSpec this_addr = wr_ports[i]->getPort(ID::ADDR);
RTLIL::SigSpec this_data = wr_ports[i]->getPort("\\DATA"); RTLIL::SigSpec this_data = wr_ports[i]->getPort(ID::DATA);
std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort("\\EN")); std::vector<RTLIL::SigBit> this_en = modwalker.sigmap(wr_ports[i]->getPort(ID::EN));
RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en); RTLIL::SigBit this_en_active = module->ReduceOr(NEW_ID, this_en);
@ -624,9 +624,9 @@ struct MemoryShareWorker
else else
this_addr.extend_u0(GetSize(last_addr)); this_addr.extend_u0(GetSize(last_addr));
wr_ports[i]->setParam("\\ABITS", GetSize(this_addr)); wr_ports[i]->setParam(ID::ABITS, GetSize(this_addr));
wr_ports[i]->setPort("\\ADDR", module->Mux(NEW_ID, last_addr, this_addr, this_en_active)); wr_ports[i]->setPort(ID::ADDR, module->Mux(NEW_ID, last_addr, this_addr, this_en_active));
wr_ports[i]->setPort("\\DATA", module->Mux(NEW_ID, last_data, this_data, this_en_active)); wr_ports[i]->setPort(ID::DATA, module->Mux(NEW_ID, last_data, this_data, this_en_active));
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en; RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
@ -644,7 +644,7 @@ struct MemoryShareWorker
} }
module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en); module->addMux(NEW_ID, grouped_last_en, grouped_this_en, this_en_active, grouped_en);
wr_ports[i]->setPort("\\EN", en); wr_ports[i]->setPort(ID::EN, en);
module->remove(wr_ports[i-1]); module->remove(wr_ports[i-1]);
wr_ports[i-1] = NULL; wr_ports[i-1] = NULL;
@ -679,13 +679,13 @@ struct MemoryShareWorker
sigmap_xmux = sigmap; sigmap_xmux = sigmap;
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == "$memrd") if (cell->type == ID($memrd))
memindex[cell->parameters.at("\\MEMID").decode_string()].first.push_back(cell); memindex[cell->parameters.at(ID::MEMID).decode_string()].first.push_back(cell);
if (cell->type == "$memwr") if (cell->type == ID($memwr))
memindex[cell->parameters.at("\\MEMID").decode_string()].second.push_back(cell); memindex[cell->parameters.at(ID::MEMID).decode_string()].second.push_back(cell);
if (cell->type == "$mux") if (cell->type == ID($mux))
{ {
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B)); RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
@ -696,7 +696,7 @@ struct MemoryShareWorker
sigmap_xmux.add(cell->getPort(ID::Y), sig_a); sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
} }
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y)); std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < int(sig_y.size()); i++) for (int i = 0; i < int(sig_y.size()); i++)
@ -712,16 +712,16 @@ struct MemoryShareWorker
} }
cone_ct.setup_internals(); cone_ct.setup_internals();
cone_ct.cell_types.erase("$mul"); cone_ct.cell_types.erase(ID($mul));
cone_ct.cell_types.erase("$mod"); cone_ct.cell_types.erase(ID($mod));
cone_ct.cell_types.erase("$div"); cone_ct.cell_types.erase(ID($div));
cone_ct.cell_types.erase("$pow"); cone_ct.cell_types.erase(ID($pow));
cone_ct.cell_types.erase("$shl"); cone_ct.cell_types.erase(ID($shl));
cone_ct.cell_types.erase("$shr"); cone_ct.cell_types.erase(ID($shr));
cone_ct.cell_types.erase("$sshl"); cone_ct.cell_types.erase(ID($sshl));
cone_ct.cell_types.erase("$sshr"); cone_ct.cell_types.erase(ID($sshr));
cone_ct.cell_types.erase("$shift"); cone_ct.cell_types.erase(ID($shift));
cone_ct.cell_types.erase("$shiftx"); cone_ct.cell_types.erase(ID($shiftx));
modwalker.setup(module, &cone_ct); modwalker.setup(module, &cone_ct);

82
passes/memory/memory_unpack.cc
View file

@ -31,53 +31,53 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
log("Creating $memrd and $memwr for memory `%s' in module `%s':\n", log("Creating $memrd and $memwr for memory `%s' in module `%s':\n",
memory->name.c_str(), module->name.c_str()); memory->name.c_str(), module->name.c_str());
RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string()); RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at(ID::MEMID).decode_string());
while (module->memories.count(mem_name) != 0) while (module->memories.count(mem_name) != 0)
mem_name = mem_name.str() + stringf("_%d", autoidx++); mem_name = mem_name.str() + stringf("_%d", autoidx++);
RTLIL::Memory *mem = new RTLIL::Memory; RTLIL::Memory *mem = new RTLIL::Memory;
mem->name = mem_name; mem->name = mem_name;
mem->width = memory->parameters.at("\\WIDTH").as_int(); mem->width = memory->parameters.at(ID::WIDTH).as_int();
mem->start_offset = memory->parameters.at("\\OFFSET").as_int(); mem->start_offset = memory->parameters.at(ID::OFFSET).as_int();
mem->size = memory->parameters.at("\\SIZE").as_int(); mem->size = memory->parameters.at(ID::SIZE).as_int();
module->memories[mem_name] = mem; module->memories[mem_name] = mem;
int abits = memory->parameters.at("\\ABITS").as_int(); int abits = memory->parameters.at(ID::ABITS).as_int();
int num_rd_ports = memory->parameters.at("\\RD_PORTS").as_int(); int num_rd_ports = memory->parameters.at(ID::RD_PORTS).as_int();
int num_wr_ports = memory->parameters.at("\\WR_PORTS").as_int(); int num_wr_ports = memory->parameters.at(ID::WR_PORTS).as_int();
for (int i = 0; i < num_rd_ports; i++) for (int i = 0; i < num_rd_ports; i++)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memrd));
cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters[ID::MEMID] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_ENABLE)).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::RD_CLK_POLARITY)).extract(i, 1).as_const();
cell->parameters["\\TRANSPARENT"] = RTLIL::SigSpec(memory->parameters.at("\\RD_TRANSPARENT")).extract(i, 1).as_const(); cell->parameters[ID::TRANSPARENT] = RTLIL::SigSpec(memory->parameters.at(ID::RD_TRANSPARENT)).extract(i, 1).as_const();
cell->setPort("\\CLK", memory->getPort("\\RD_CLK").extract(i, 1)); cell->setPort(ID::CLK, memory->getPort(ID::RD_CLK).extract(i, 1));
cell->setPort("\\EN", memory->getPort("\\RD_EN").extract(i, 1)); cell->setPort(ID::EN, memory->getPort(ID::RD_EN).extract(i, 1));
cell->setPort("\\ADDR", memory->getPort("\\RD_ADDR").extract(i*abits, abits)); cell->setPort(ID::ADDR, memory->getPort(ID::RD_ADDR).extract(i*abits, abits));
cell->setPort("\\DATA", memory->getPort("\\RD_DATA").extract(i*mem->width, mem->width)); cell->setPort(ID::DATA, memory->getPort(ID::RD_DATA).extract(i*mem->width, mem->width));
} }
for (int i = 0; i < num_wr_ports; i++) for (int i = 0; i < num_wr_ports; i++)
{ {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($memwr));
cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters[ID::MEMID] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const(); cell->parameters[ID::CLK_ENABLE] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_ENABLE)).extract(i, 1).as_const();
cell->parameters["\\CLK_POLARITY"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_POLARITY")).extract(i, 1).as_const(); cell->parameters[ID::CLK_POLARITY] = RTLIL::SigSpec(memory->parameters.at(ID::WR_CLK_POLARITY)).extract(i, 1).as_const();
cell->parameters["\\PRIORITY"] = i; cell->parameters[ID::PRIORITY] = i;
cell->setPort("\\CLK", memory->getPort("\\WR_CLK").extract(i, 1)); cell->setPort(ID::CLK, memory->getPort(ID::WR_CLK).extract(i, 1));
cell->setPort("\\EN", memory->getPort("\\WR_EN").extract(i*mem->width, mem->width)); cell->setPort(ID::EN, memory->getPort(ID::WR_EN).extract(i*mem->width, mem->width));
cell->setPort("\\ADDR", memory->getPort("\\WR_ADDR").extract(i*abits, abits)); cell->setPort(ID::ADDR, memory->getPort(ID::WR_ADDR).extract(i*abits, abits));
cell->setPort("\\DATA", memory->getPort("\\WR_DATA").extract(i*mem->width, mem->width)); cell->setPort(ID::DATA, memory->getPort(ID::WR_DATA).extract(i*mem->width, mem->width));
} }
Const initval = memory->parameters.at("\\INIT"); Const initval = memory->parameters.at(ID::INIT);
RTLIL::Cell *last_init_cell = nullptr; RTLIL::Cell *last_init_cell = nullptr;
SigSpec last_init_data; SigSpec last_init_data;
int last_init_addr=0; int last_init_addr=0;
@ -90,19 +90,19 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
continue; continue;
found_non_undef_initval: found_non_undef_initval:
if (last_init_cell && last_init_addr+1 == i/mem->width) { if (last_init_cell && last_init_addr+1 == i/mem->width) {
last_init_cell->parameters["\\WORDS"] = last_init_cell->parameters["\\WORDS"].as_int() + 1; last_init_cell->parameters[ID::WORDS] = last_init_cell->parameters[ID::WORDS].as_int() + 1;
last_init_data.append(val); last_init_data.append(val);
last_init_addr++; last_init_addr++;
} else { } else {
if (last_init_cell) if (last_init_cell)
last_init_cell->setPort("\\DATA", last_init_data); last_init_cell->setPort(ID::DATA, last_init_data);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$meminit"); RTLIL::Cell *cell = module->addCell(NEW_ID, ID($meminit));
cell->parameters["\\MEMID"] = mem_name.str(); cell->parameters[ID::MEMID] = mem_name.str();
cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS"); cell->parameters[ID::ABITS] = memory->parameters.at(ID::ABITS);
cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH"); cell->parameters[ID::WIDTH] = memory->parameters.at(ID::WIDTH);
cell->parameters["\\WORDS"] = 1; cell->parameters[ID::WORDS] = 1;
cell->parameters["\\PRIORITY"] = i/mem->width; cell->parameters[ID::PRIORITY] = i/mem->width;
cell->setPort("\\ADDR", SigSpec(i/mem->width, abits)); cell->setPort(ID::ADDR, SigSpec(i/mem->width, abits));
last_init_cell = cell; last_init_cell = cell;
last_init_addr = i/mem->width; last_init_addr = i/mem->width;
last_init_data = val; last_init_data = val;
@ -110,7 +110,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
} }
if (last_init_cell) if (last_init_cell)
last_init_cell->setPort("\\DATA", last_init_data); last_init_cell->setPort(ID::DATA, last_init_data);
module->remove(memory); module->remove(memory);
} }
@ -119,7 +119,7 @@ void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{ {
std::vector<RTLIL::IdString> memcells; std::vector<RTLIL::IdString> memcells;
for (auto &cell_it : module->cells_) for (auto &cell_it : module->cells_)
if (cell_it.second->type == "$mem" && design->selected(module, cell_it.second)) if (cell_it.second->type == ID($mem) && design->selected(module, cell_it.second))
memcells.push_back(cell_it.first); memcells.push_back(cell_it.first);
for (auto &it : memcells) for (auto &it : memcells)
handle_memory(module, module->cells_.at(it)); handle_memory(module, module->cells_.at(it));

14
passes/opt/muxpack.cc
View file

@ -208,8 +208,8 @@ struct MuxpackWorker
{ {
Cell *prev_cell = sig_chain_prev.at(a_sig); Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell); log_assert(prev_cell);
SigSpec s_sig = sigmap(cell->getPort(ID(S))); SigSpec s_sig = sigmap(cell->getPort(ID::S));
s_sig.append(sigmap(prev_cell->getPort(ID(S)))); s_sig.append(sigmap(prev_cell->getPort(ID::S)));
if (!excl_db.query(s_sig)) if (!excl_db.query(s_sig))
goto start_cell; goto start_cell;
} }
@ -271,26 +271,26 @@ struct MuxpackWorker
first_cell->type = ID($pmux); first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B); SigSpec b_sig = first_cell->getPort(ID::B);
SigSpec s_sig = first_cell->getPort(ID(S)); SigSpec s_sig = first_cell->getPort(ID::S);
for (int i = 1; i < cases; i++) { for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1]; Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i]; Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) { if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B)); b_sig.append(cursor_cell->getPort(ID::B));
s_sig.append(cursor_cell->getPort(ID(S))); s_sig.append(cursor_cell->getPort(ID::S));
} }
else { else {
log_assert(cursor_cell->type == ID($mux)); log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A)); b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID(S)))); s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
} }
remove_cells.insert(cursor_cell); remove_cells.insert(cursor_cell);
} }
first_cell->setPort(ID::B, b_sig); first_cell->setPort(ID::B, b_sig);
first_cell->setPort(ID(S), s_sig); first_cell->setPort(ID::S, s_sig);
first_cell->setParam(ID(S_WIDTH), GetSize(s_sig)); first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y)); first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
cursor += cases; cursor += cases;

36
passes/opt/opt_clean.cc
View file

@ -183,8 +183,8 @@ void rmunused_module_cells(Module *module, bool verbose)
int count_nontrivial_wire_attrs(RTLIL::Wire *w) int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{ {
int count = w->attributes.size(); int count = w->attributes.size();
count -= w->attributes.count(ID(src)); count -= w->attributes.count(ID::src);
count -= w->attributes.count(ID(unused_bits)); count -= w->attributes.count(ID::unused_bits);
return count; return count;
} }
@ -317,12 +317,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
log_assert(GetSize(s1) == GetSize(s2)); log_assert(GetSize(s1) == GetSize(s2));
Const initval; Const initval;
if (wire->attributes.count(ID(init))) if (wire->attributes.count(ID::init))
initval = wire->attributes.at(ID(init)); initval = wire->attributes.at(ID::init);
if (GetSize(initval) != GetSize(wire)) if (GetSize(initval) != GetSize(wire))
initval.bits.resize(GetSize(wire), State::Sx); initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) if (initval.is_fully_undef())
wire->attributes.erase(ID(init)); wire->attributes.erase(ID::init);
if (GetSize(wire) == 0) { if (GetSize(wire) == 0) {
// delete zero-width wires, unless they are module ports // delete zero-width wires, unless they are module ports
@ -363,9 +363,9 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
} }
if (new_conn.first.size() > 0) { if (new_conn.first.size() > 0) {
if (initval.is_fully_undef()) if (initval.is_fully_undef())
wire->attributes.erase(ID(init)); wire->attributes.erase(ID::init);
else else
wire->attributes.at(ID(init)) = initval; wire->attributes.at(ID::init) = initval;
used_signals.add(new_conn.first); used_signals.add(new_conn.first);
used_signals.add(new_conn.second); used_signals.add(new_conn.second);
module->connect(new_conn); module->connect(new_conn);
@ -383,11 +383,11 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
} }
} }
if (unused_bits.empty() || wire->port_id != 0) if (unused_bits.empty() || wire->port_id != 0)
wire->attributes.erase(ID(unused_bits)); wire->attributes.erase(ID::unused_bits);
else else
wire->attributes[ID(unused_bits)] = RTLIL::Const(unused_bits); wire->attributes[ID::unused_bits] = RTLIL::Const(unused_bits);
} else { } else {
wire->attributes.erase(ID(unused_bits)); wire->attributes.erase(ID::unused_bits);
} }
} }
} }
@ -419,18 +419,18 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
dict<SigBit, State> qbits; dict<SigBit, State> qbits;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (fftypes.cell_known(cell->type) && cell->hasPort(ID(Q))) if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
{ {
SigSpec sig = cell->getPort(ID(Q)); SigSpec sig = cell->getPort(ID::Q);
for (int i = 0; i < GetSize(sig); i++) for (int i = 0; i < GetSize(sig); i++)
{ {
SigBit bit = sig[i]; SigBit bit = sig[i];
if (bit.wire == nullptr || bit.wire->attributes.count(ID(init)) == 0) if (bit.wire == nullptr || bit.wire->attributes.count(ID::init) == 0)
continue; continue;
Const init = bit.wire->attributes.at(ID(init)); Const init = bit.wire->attributes.at(ID::init);
if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz) if (i >= GetSize(init) || init[i] == State::Sx || init[i] == State::Sz)
continue; continue;
@ -445,10 +445,10 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
if (!purge_mode && wire->name[0] == '\\') if (!purge_mode && wire->name[0] == '\\')
continue; continue;
if (wire->attributes.count(ID(init)) == 0) if (wire->attributes.count(ID::init) == 0)
continue; continue;
Const init = wire->attributes.at(ID(init)); Const init = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++) for (int i = 0; i < GetSize(wire) && i < GetSize(init); i++)
{ {
@ -471,7 +471,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool purge_mode, bool verbose)
if (verbose) if (verbose)
log_debug(" removing redundant init attribute on %s.\n", log_id(wire)); log_debug(" removing redundant init attribute on %s.\n", log_id(wire));
wire->attributes.erase(ID(init)); wire->attributes.erase(ID::init);
did_something = true; did_something = true;
next_wire:; next_wire:;
} }
@ -487,7 +487,7 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose, bool
std::vector<RTLIL::Cell*> delcells; std::vector<RTLIL::Cell*> delcells;
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) { if (cell->type.in(ID($pos), ID($_BUF_)) && !cell->has_keep_attr()) {
bool is_signed = cell->type == ID($pos) && cell->getParam(ID(A_SIGNED)).as_bool(); bool is_signed = cell->type == ID($pos) && cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y); RTLIL::SigSpec y = cell->getPort(ID::Y);
a.extend_u0(GetSize(y), is_signed); a.extend_u0(GetSize(y), is_signed);

294
passes/opt/opt_expr.cc
View file

@ -50,9 +50,9 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
} }
for (auto wire : module->wires()) { for (auto wire : module->wires()) {
if (wire->attributes.count(ID(init))) { if (wire->attributes.count(ID::init)) {
SigSpec sig = sigmap(wire); SigSpec sig = sigmap(wire);
Const initval = wire->attributes.at(ID(init)); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) { for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
initbits[sig[i]] = make_pair(wire, initval[i]); initbits[sig[i]] = make_pair(wire, initval[i]);
@ -98,18 +98,18 @@ void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
for (auto wire : revisit_initwires) { for (auto wire : revisit_initwires) {
SigSpec sig = sm2(wire); SigSpec sig = sm2(wire);
Const initval = wire->attributes.at(ID(init)); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) { for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) {
if (SigBit(initval[i]) == sig[i]) if (SigBit(initval[i]) == sig[i])
initval[i] = State::Sx; initval[i] = State::Sx;
} }
if (initval.is_fully_undef()) { if (initval.is_fully_undef()) {
log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire)); log_debug("Removing init attribute from %s/%s.\n", log_id(module), log_id(wire));
wire->attributes.erase(ID(init)); wire->attributes.erase(ID::init);
did_something = true; did_something = true;
} else if (initval != wire->attributes.at(ID(init))) { } else if (initval != wire->attributes.at(ID::init)) {
log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval)); log_debug("Updating init attribute on %s/%s: %s\n", log_id(module), log_id(wire), log_signal(initval));
wire->attributes[ID(init)] = initval; wire->attributes[ID::init] = initval;
did_something = true; did_something = true;
} }
} }
@ -136,7 +136,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
{ {
IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A; IdString b_name = cell->hasPort(ID::B) ? ID::B : ID::A;
bool a_signed = cell->parameters.at(ID(A_SIGNED)).as_bool(); bool a_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool(); bool b_signed = cell->parameters.at(b_name.str() + "_SIGNED").as_bool();
RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = sigmap(cell->getPort(ID::A));
@ -209,17 +209,17 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
RTLIL::Cell *c = module->addCell(NEW_ID, cell->type); RTLIL::Cell *c = module->addCell(NEW_ID, cell->type);
c->setPort(ID::A, new_a); c->setPort(ID::A, new_a);
c->parameters[ID(A_WIDTH)] = new_a.size(); c->parameters[ID::A_WIDTH] = new_a.size();
c->parameters[ID(A_SIGNED)] = false; c->parameters[ID::A_SIGNED] = false;
if (b_name == ID::B) { if (b_name == ID::B) {
c->setPort(ID::B, new_b); c->setPort(ID::B, new_b);
c->parameters[ID(B_WIDTH)] = new_b.size(); c->parameters[ID::B_WIDTH] = new_b.size();
c->parameters[ID(B_SIGNED)] = false; c->parameters[ID::B_SIGNED] = false;
} }
c->setPort(ID::Y, new_y); c->setPort(ID::Y, new_y);
c->parameters[ID(Y_WIDTH)] = new_y->width; c->parameters[ID::Y_WIDTH] = new_y->width;
c->check(); c->check();
module->connect(new_conn); module->connect(new_conn);
@ -372,7 +372,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A)); invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::A));
if (cell->type.in(ID($mux), ID($_MUX_)) && if (cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0)) cell->getPort(ID::A) == SigSpec(State::S1) && cell->getPort(ID::B) == SigSpec(State::S0))
invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID(S))); invert_map[assign_map(cell->getPort(ID::Y))] = assign_map(cell->getPort(ID::S));
if (ct_combinational.cell_known(cell->type)) if (ct_combinational.cell_known(cell->type))
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {
RTLIL::SigSpec sig = assign_map(conn.second); RTLIL::SigSpec sig = assign_map(conn.second);
@ -401,36 +401,36 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (clkinv) if (clkinv)
{ {
if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr))) if (cell->type.in(ID($dff), ID($dffe), ID($dffsr), ID($adff), ID($fsm), ID($memrd), ID($memwr)))
handle_polarity_inv(cell, ID(CLK), ID(CLK_POLARITY), assign_map, invert_map); handle_polarity_inv(cell, ID::CLK, ID::CLK_POLARITY, assign_map, invert_map);
if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) { if (cell->type.in(ID($sr), ID($dffsr), ID($dlatchsr))) {
handle_polarity_inv(cell, ID(SET), ID(SET_POLARITY), assign_map, invert_map); handle_polarity_inv(cell, ID::SET, ID::SET_POLARITY, assign_map, invert_map);
handle_polarity_inv(cell, ID(CLR), ID(CLR_POLARITY), assign_map, invert_map); handle_polarity_inv(cell, ID::CLR, ID::CLR_POLARITY, assign_map, invert_map);
} }
if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr))) if (cell->type.in(ID($dffe), ID($dlatch), ID($dlatchsr)))
handle_polarity_inv(cell, ID(EN), ID(EN_POLARITY), assign_map, invert_map); handle_polarity_inv(cell, ID::EN, ID::EN_POLARITY, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID(S), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_SR_N?_", "$_SR_P?_", ID::S, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID(R), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_SR_?N_", "$_SR_?P_", ID::R, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID(C), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFF_N_", "$_DFF_P_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID(C), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFFE_N?_", "$_DFFE_P?_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID(E), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFFE_?N_", "$_DFFE_?P_", ID::E, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID(C), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFF_N??_", "$_DFF_P??_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID(R), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFF_?N?_", "$_DFF_?P?_", ID::R, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID(C), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFFSR_N??_", "$_DFFSR_P??_", ID::C, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID(S), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFFSR_?N?_", "$_DFFSR_?P?_", ID::S, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID(R), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DFFSR_??N_", "$_DFFSR_??P_", ID::R, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID(E), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DLATCH_N_", "$_DLATCH_P_", ID::E, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID(E), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DLATCHSR_N??_", "$_DLATCHSR_P??_", ID::E, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID(S), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DLATCHSR_?N?_", "$_DLATCHSR_?P?_", ID::S, assign_map, invert_map);
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID(R), assign_map, invert_map); handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
} }
bool detect_const_and = false; bool detect_const_and = false;
@ -439,13 +439,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type.in(ID($reduce_and), ID($_AND_))) if (cell->type.in(ID($reduce_and), ID($_AND_)))
detect_const_and = true; detect_const_and = true;
if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()) if (cell->type.in(ID($and), ID($logic_and)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_and = true; detect_const_and = true;
if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_))) if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($_OR_)))
detect_const_or = true; detect_const_or = true;
if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool()) if (cell->type.in(ID($or), ID($logic_or)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool())
detect_const_or = true; detect_const_or = true;
if (detect_const_and || detect_const_or) if (detect_const_and || detect_const_or)
@ -495,7 +495,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
} }
if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID(A_SIGNED)).as_bool())) if (cell->type.in(ID($_XOR_), ID($_XNOR_)) || (cell->type.in(ID($xor), ID($xnor)) && GetSize(cell->getPort(ID::A)) == 1 && GetSize(cell->getPort(ID::B)) == 1 && !cell->getParam(ID::A_SIGNED).as_bool()))
{ {
SigBit sig_a = assign_map(cell->getPort(ID::A)); SigBit sig_a = assign_map(cell->getPort(ID::A));
SigBit sig_b = assign_map(cell->getPort(ID::B)); SigBit sig_b = assign_map(cell->getPort(ID::B));
@ -518,7 +518,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
SigSpec sig_y; SigSpec sig_y;
if (cell->type == ID($xnor)) { if (cell->type == ID($xnor)) {
sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit()); sig_y = (sig_b == State::S1 ? sig_a : module->Not(NEW_ID, sig_a).as_bit());
int width = cell->getParam(ID(Y_WIDTH)).as_int(); int width = cell->getParam(ID::Y_WIDTH).as_int();
sig_y.append(RTLIL::Const(State::S1, width-1)); sig_y.append(RTLIL::Const(State::S1, width-1));
} }
else if (cell->type == ID($_XNOR_)) else if (cell->type == ID($_XNOR_))
@ -571,7 +571,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", log_debug("Replacing port A of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_sig_a));
cell->setPort(ID::A, new_sig_a); cell->setPort(ID::A, new_sig_a);
cell->parameters.at(ID(A_WIDTH)) = GetSize(new_sig_a); cell->parameters.at(ID::A_WIDTH) = GetSize(new_sig_a);
did_something = true; did_something = true;
} }
} }
@ -594,7 +594,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n", log_debug("Replacing port B of %s cell `%s' in module `%s' with shorter expression: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_sig_b));
cell->setPort(ID::B, new_sig_b); cell->setPort(ID::B, new_sig_b);
cell->parameters.at(ID(B_WIDTH)) = GetSize(new_sig_b); cell->parameters.at(ID::B_WIDTH) = GetSize(new_sig_b);
did_something = true; did_something = true;
} }
} }
@ -620,7 +620,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a); cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID(A_WIDTH)) = 1; cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true; did_something = true;
} }
} }
@ -646,7 +646,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", log_debug("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
cell->setPort(ID::A, sig_a = new_a); cell->setPort(ID::A, sig_a = new_a);
cell->parameters.at(ID(A_WIDTH)) = 1; cell->parameters.at(ID::A_WIDTH) = 1;
did_something = true; did_something = true;
} }
} }
@ -672,7 +672,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n", log_debug("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b)); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
cell->setPort(ID::B, sig_b = new_b); cell->setPort(ID::B, sig_b = new_b);
cell->parameters.at(ID(B_WIDTH)) = 1; cell->parameters.at(ID::B_WIDTH) = 1;
did_something = true; did_something = true;
} }
} }
@ -711,11 +711,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
{ {
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI))); RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI))); RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
RTLIL::SigSpec sig_x = cell->getPort(ID(X)); RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y); RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_co = cell->getPort(ID(CO)); RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
bool sub = (sig_ci == State::S1 && sig_bi == State::S1); bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
@ -750,9 +750,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover("opt.opt_expr.fine.$alu"); cover("opt.opt_expr.fine.$alu");
cell->setPort(ID::A, sig_a.extract_end(i)); cell->setPort(ID::A, sig_a.extract_end(i));
cell->setPort(ID::B, sig_b.extract_end(i)); cell->setPort(ID::B, sig_b.extract_end(i));
cell->setPort(ID(X), sig_x.extract_end(i)); cell->setPort(ID::X, sig_x.extract_end(i));
cell->setPort(ID::Y, sig_y.extract_end(i)); cell->setPort(ID::Y, sig_y.extract_end(i));
cell->setPort(ID(CO), sig_co.extract_end(i)); cell->setPort(ID::CO, sig_co.extract_end(i));
cell->fixup_parameters(); cell->fixup_parameters();
did_something = true; did_something = true;
} }
@ -804,7 +804,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str()); cover_list("opt.opt_expr.trim", "$shiftx", "$shift", cell->type.str());
sig_a.remove(width, GetSize(sig_a)-width); sig_a.remove(width, GetSize(sig_a)-width);
cell->setPort(ID::A, sig_a); cell->setPort(ID::A, sig_a);
cell->setParam(ID(A_WIDTH), width); cell->setParam(ID::A_WIDTH, width);
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -817,13 +817,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
goto next_cell; goto next_cell;
} }
if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID(S)))) != 0) { if (cell->type.in(ID($_MUX_), ID($mux)) && invert_map.count(assign_map(cell->getPort(ID::S))) != 0) {
cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str()); cover_list("opt.opt_expr.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module)); log_debug("Optimizing away select inverter for %s cell `%s' in module `%s'.\n", log_id(cell->type), log_id(cell), log_id(module));
RTLIL::SigSpec tmp = cell->getPort(ID::A); RTLIL::SigSpec tmp = cell->getPort(ID::A);
cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(ID::B, tmp); cell->setPort(ID::B, tmp);
cell->setPort(ID(S), invert_map.at(assign_map(cell->getPort(ID(S))))); cell->setPort(ID::S, invert_map.at(assign_map(cell->getPort(ID::S))));
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
@ -889,7 +889,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (cell->type == ID($_MUX_)) { if (cell->type == ID($_MUX_)) {
RTLIL::SigSpec input; RTLIL::SigSpec input;
input.append(cell->getPort(ID(S))); input.append(cell->getPort(ID::S));
input.append(cell->getPort(ID::B)); input.append(cell->getPort(ID::B));
input.append(cell->getPort(ID::A)); input.append(cell->getPort(ID::A));
assign_map.apply(input); assign_map.apply(input);
@ -903,7 +903,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type = ID($_NOT_); cell->type = ID($_NOT_);
cell->setPort(ID::A, input.extract(0, 1)); cell->setPort(ID::A, input.extract(0, 1));
cell->unsetPort(ID::B); cell->unsetPort(ID::B);
cell->unsetPort(ID(S)); cell->unsetPort(ID::S);
goto next_cell; goto next_cell;
} }
if (input.match("11 ")) ACTION_DO_Y(1); if (input.match("11 ")) ACTION_DO_Y(1);
@ -919,7 +919,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
if (cell->type.in(ID($_TBUF_), ID($tribuf))) { if (cell->type.in(ID($_TBUF_), ID($tribuf))) {
RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID(E) : ID(EN)); RTLIL::SigSpec input = cell->getPort(cell->type == ID($_TBUF_) ? ID::E : ID::EN);
RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec a = cell->getPort(ID::A);
assign_map.apply(input); assign_map.apply(input);
assign_map.apply(a); assign_map.apply(a);
@ -940,10 +940,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a = cell->getPort(ID::A); RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B); RTLIL::SigSpec b = cell->getPort(ID::B);
if (cell->parameters[ID(A_WIDTH)].as_int() != cell->parameters[ID(B_WIDTH)].as_int()) { if (cell->parameters[ID::A_WIDTH].as_int() != cell->parameters[ID::B_WIDTH].as_int()) {
int width = max(cell->parameters[ID(A_WIDTH)].as_int(), cell->parameters[ID(B_WIDTH)].as_int()); int width = max(cell->parameters[ID::A_WIDTH].as_int(), cell->parameters[ID::B_WIDTH].as_int());
a.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()); a.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
b.extend_u0(width, cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()); b.extend_u0(width, cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool());
} }
RTLIL::SigSpec new_a, new_b; RTLIL::SigSpec new_a, new_b;
@ -953,7 +953,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) { if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cover_list("opt.opt_expr.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S0 : RTLIL::State::S1);
new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false); new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y); replace_cell(assign_map, module, cell, "isneq", ID::Y, new_y);
goto next_cell; goto next_cell;
} }
@ -966,7 +966,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (new_a.size() == 0) { if (new_a.size() == 0) {
cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cover_list("opt.opt_expr.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0); RTLIL::SigSpec new_y = RTLIL::SigSpec(cell->type.in(ID($eq), ID($eqx)) ? RTLIL::State::S1 : RTLIL::State::S0);
new_y.extend_u0(cell->parameters[ID(Y_WIDTH)].as_int(), false); new_y.extend_u0(cell->parameters[ID::Y_WIDTH].as_int(), false);
replace_cell(assign_map, module, cell, "empty", ID::Y, new_y); replace_cell(assign_map, module, cell, "empty", ID::Y, new_y);
goto next_cell; goto next_cell;
} }
@ -975,13 +975,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str()); cover_list("opt.opt_expr.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
cell->setPort(ID::A, new_a); cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
cell->parameters[ID(A_WIDTH)] = new_a.size(); cell->parameters[ID::A_WIDTH] = new_a.size();
cell->parameters[ID(B_WIDTH)] = new_b.size(); cell->parameters[ID::B_WIDTH] = new_b.size();
} }
} }
if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID(Y_WIDTH)].as_int() == 1 && if (cell->type.in(ID($eq), ID($ne)) && cell->parameters[ID::Y_WIDTH].as_int() == 1 &&
cell->parameters[ID(A_WIDTH)].as_int() == 1 && cell->parameters[ID(B_WIDTH)].as_int() == 1) cell->parameters[ID::A_WIDTH].as_int() == 1 && cell->parameters[ID::B_WIDTH].as_int() == 1)
{ {
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
@ -1005,8 +1005,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str()); cover_list("opt.opt_expr.eqneq.isnot", "$eq", "$ne", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->type = ID($not); cell->type = ID($not);
cell->parameters.erase(ID(B_WIDTH)); cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID(B_SIGNED)); cell->parameters.erase(ID::B_SIGNED);
cell->unsetPort(ID::B); cell->unsetPort(ID::B);
did_something = true; did_something = true;
} }
@ -1023,29 +1023,29 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool); cell->type = cell->type == ID($eq) ? ID($logic_not) : ID($reduce_bool);
if (assign_map(cell->getPort(ID::A)).is_fully_zero()) { if (assign_map(cell->getPort(ID::A)).is_fully_zero()) {
cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::A, cell->getPort(ID::B));
cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED))); cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH))); cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
} }
cell->unsetPort(ID::B); cell->unsetPort(ID::B);
cell->unsetParam(ID(B_SIGNED)); cell->unsetParam(ID::B_SIGNED);
cell->unsetParam(ID(B_WIDTH)); cell->unsetParam(ID::B_WIDTH);
did_something = true; did_something = true;
goto next_cell; goto next_cell;
} }
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const()) if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)) && assign_map(cell->getPort(ID::B)).is_fully_const())
{ {
bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID(A_SIGNED)).as_bool(); bool sign_ext = cell->type == ID($sshr) && cell->getParam(ID::A_SIGNED).as_bool();
int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID(B_SIGNED)).as_bool()); int shift_bits = assign_map(cell->getPort(ID::B)).as_int(cell->type.in(ID($shift), ID($shiftx)) && cell->getParam(ID::B_SIGNED).as_bool());
if (cell->type.in(ID($shl), ID($sshl))) if (cell->type.in(ID($shl), ID($sshl)))
shift_bits *= -1; shift_bits *= -1;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID(Y_WIDTH)).as_int()); RTLIL::SigSpec sig_y(cell->type == ID($shiftx) ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam(ID::Y_WIDTH).as_int());
if (GetSize(sig_a) < GetSize(sig_y)) if (GetSize(sig_a) < GetSize(sig_y))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID(A_SIGNED)).as_bool()); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) { for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits; int idx = i + shift_bits;
@ -1081,8 +1081,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
bool sub = cell->type == ID($sub); bool sub = cell->type == ID($sub);
if (cell->type == ID($alu)) { if (cell->type == ID($alu)) {
RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI))); RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID::CI));
RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI))); RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID::BI));
sub = (sig_ci == State::S1 && sig_bi == State::S1); sub = (sig_ci == State::S1 && sig_bi == State::S1);
@ -1112,10 +1112,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID(A_SIGNED)).as_bool(), arith_inverse)) if (a.is_fully_const() && is_one_or_minus_one(a.as_const(), cell->getParam(ID::A_SIGNED).as_bool(), arith_inverse))
identity_wrt_b = true; identity_wrt_b = true;
else else
if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID(B_SIGNED)).as_bool(), arith_inverse)) if (b.is_fully_const() && is_one_or_minus_one(b.as_const(), cell->getParam(ID::B_SIGNED).as_bool(), arith_inverse))
identity_wrt_a = true; identity_wrt_a = true;
} }
@ -1138,25 +1138,25 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B'); cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
if (cell->type == ID($alu)) { if (cell->type == ID($alu)) {
int y_width = GetSize(cell->getPort(ID(Y))); int y_width = GetSize(cell->getPort(ID::Y));
module->connect(cell->getPort(ID(X)), RTLIL::Const(State::S0, y_width)); module->connect(cell->getPort(ID::X), RTLIL::Const(State::S0, y_width));
module->connect(cell->getPort(ID(CO)), RTLIL::Const(State::S0, y_width)); module->connect(cell->getPort(ID::CO), RTLIL::Const(State::S0, y_width));
cell->unsetPort(ID(BI)); cell->unsetPort(ID::BI);
cell->unsetPort(ID(CI)); cell->unsetPort(ID::CI);
cell->unsetPort(ID(X)); cell->unsetPort(ID::X);
cell->unsetPort(ID(CO)); cell->unsetPort(ID::CO);
} }
if (!identity_wrt_a) { if (!identity_wrt_a) {
cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::A, cell->getPort(ID::B));
cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH))); cell->setParam(ID::A_WIDTH, cell->getParam(ID::B_WIDTH));
cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED))); cell->setParam(ID::A_SIGNED, cell->getParam(ID::B_SIGNED));
} }
cell->type = arith_inverse ? ID($neg) : ID($pos); cell->type = arith_inverse ? ID($neg) : ID($pos);
cell->unsetPort(ID::B); cell->unsetPort(ID::B);
cell->parameters.erase(ID(B_WIDTH)); cell->parameters.erase(ID::B_WIDTH);
cell->parameters.erase(ID(B_SIGNED)); cell->parameters.erase(ID::B_SIGNED);
cell->check(); cell->check();
did_something = true; did_something = true;
@ -1167,7 +1167,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && if (mux_bool && cell->type.in(ID($mux), ID($_MUX_)) &&
cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) { cell->getPort(ID::A) == State::S0 && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str()); cover_list("opt.opt_expr.mux_bool", "$mux", "$_MUX_", cell->type.str());
replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID(S))); replace_cell(assign_map, module, cell, "mux_bool", ID::Y, cell->getPort(ID::S));
goto next_cell; goto next_cell;
} }
@ -1175,15 +1175,15 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) { cell->getPort(ID::A) == State::S1 && cell->getPort(ID::B) == State::S0) {
cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str()); cover_list("opt.opt_expr.mux_invert", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module)); log_debug("Replacing %s cell `%s' in module `%s' with inverter.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, cell->getPort(ID(S))); cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID::B); cell->unsetPort(ID::B);
cell->unsetPort(ID(S)); cell->unsetPort(ID::S);
if (cell->type == ID($mux)) { if (cell->type == ID($mux)) {
Const width = cell->parameters[ID(WIDTH)]; Const width = cell->parameters[ID::WIDTH];
cell->parameters[ID(A_WIDTH)] = width; cell->parameters[ID::A_WIDTH] = width;
cell->parameters[ID(Y_WIDTH)] = width; cell->parameters[ID::Y_WIDTH] = width;
cell->parameters[ID(A_SIGNED)] = 0; cell->parameters[ID::A_SIGNED] = 0;
cell->parameters.erase(ID(WIDTH)); cell->parameters.erase(ID::WIDTH);
cell->type = ID($not); cell->type = ID($not);
} else } else
cell->type = ID($_NOT_); cell->type = ID($_NOT_);
@ -1194,16 +1194,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) { if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::A) == State::S0) {
cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str()); cover_list("opt.opt_expr.mux_and", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); log_debug("Replacing %s cell `%s' in module `%s' with and-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, cell->getPort(ID(S))); cell->setPort(ID::A, cell->getPort(ID::S));
cell->unsetPort(ID(S)); cell->unsetPort(ID::S);
if (cell->type == ID($mux)) { if (cell->type == ID($mux)) {
Const width = cell->parameters[ID(WIDTH)]; Const width = cell->parameters[ID::WIDTH];
cell->parameters[ID(A_WIDTH)] = width; cell->parameters[ID::A_WIDTH] = width;
cell->parameters[ID(B_WIDTH)] = width; cell->parameters[ID::B_WIDTH] = width;
cell->parameters[ID(Y_WIDTH)] = width; cell->parameters[ID::Y_WIDTH] = width;
cell->parameters[ID(A_SIGNED)] = 0; cell->parameters[ID::A_SIGNED] = 0;
cell->parameters[ID(B_SIGNED)] = 0; cell->parameters[ID::B_SIGNED] = 0;
cell->parameters.erase(ID(WIDTH)); cell->parameters.erase(ID::WIDTH);
cell->type = ID($and); cell->type = ID($and);
} else } else
cell->type = ID($_AND_); cell->type = ID($_AND_);
@ -1214,16 +1214,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) { if (consume_x && mux_bool && cell->type.in(ID($mux), ID($_MUX_)) && cell->getPort(ID::B) == State::S1) {
cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str()); cover_list("opt.opt_expr.mux_or", "$mux", "$_MUX_", cell->type.str());
log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module)); log_debug("Replacing %s cell `%s' in module `%s' with or-gate.\n", log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::B, cell->getPort(ID(S))); cell->setPort(ID::B, cell->getPort(ID::S));
cell->unsetPort(ID(S)); cell->unsetPort(ID::S);
if (cell->type == ID($mux)) { if (cell->type == ID($mux)) {
Const width = cell->parameters[ID(WIDTH)]; Const width = cell->parameters[ID::WIDTH];
cell->parameters[ID(A_WIDTH)] = width; cell->parameters[ID::A_WIDTH] = width;
cell->parameters[ID(B_WIDTH)] = width; cell->parameters[ID::B_WIDTH] = width;
cell->parameters[ID(Y_WIDTH)] = width; cell->parameters[ID::Y_WIDTH] = width;
cell->parameters[ID(A_SIGNED)] = 0; cell->parameters[ID::A_SIGNED] = 0;
cell->parameters[ID(B_SIGNED)] = 0; cell->parameters[ID::B_SIGNED] = 0;
cell->parameters.erase(ID(WIDTH)); cell->parameters.erase(ID::WIDTH);
cell->type = ID($or); cell->type = ID($or);
} else } else
cell->type = ID($_OR_); cell->type = ID($_OR_);
@ -1235,14 +1235,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec new_a, new_b, new_s; RTLIL::SigSpec new_a, new_b, new_s;
int width = GetSize(cell->getPort(ID::A)); int width = GetSize(cell->getPort(ID::A));
if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) || if ((cell->getPort(ID::A).is_fully_undef() && cell->getPort(ID::B).is_fully_undef()) ||
cell->getPort(ID(S)).is_fully_undef()) { cell->getPort(ID::S).is_fully_undef()) {
cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str()); cover_list("opt.opt_expr.mux_undef", "$mux", "$pmux", cell->type.str());
replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A)); replace_cell(assign_map, module, cell, "mux_undef", ID::Y, cell->getPort(ID::A));
goto next_cell; goto next_cell;
} }
for (int i = 0; i < cell->getPort(ID(S)).size(); i++) { for (int i = 0; i < cell->getPort(ID::S).size(); i++) {
RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width); RTLIL::SigSpec old_b = cell->getPort(ID::B).extract(i*width, width);
RTLIL::SigSpec old_s = cell->getPort(ID(S)).extract(i, 1); RTLIL::SigSpec old_s = cell->getPort(ID::S).extract(i, 1);
if (old_b.is_fully_undef() || old_s.is_fully_undef()) if (old_b.is_fully_undef() || old_s.is_fully_undef())
continue; continue;
new_b.append(old_b); new_b.append(old_b);
@ -1264,48 +1264,48 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s); replace_cell(assign_map, module, cell, "mux_sel01", ID::Y, new_s);
goto next_cell; goto next_cell;
} }
if (cell->getPort(ID(S)).size() != new_s.size()) { if (cell->getPort(ID::S).size() != new_s.size()) {
cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str()); cover_list("opt.opt_expr.mux_reduce", "$mux", "$pmux", cell->type.str());
log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n", log_debug("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
GetSize(cell->getPort(ID(S))) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module)); GetSize(cell->getPort(ID::S)) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
cell->setPort(ID::A, new_a); cell->setPort(ID::A, new_a);
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
cell->setPort(ID(S), new_s); cell->setPort(ID::S, new_s);
if (new_s.size() > 1) { if (new_s.size() > 1) {
cell->type = ID($pmux); cell->type = ID($pmux);
cell->parameters[ID(S_WIDTH)] = new_s.size(); cell->parameters[ID::S_WIDTH] = new_s.size();
} else { } else {
cell->type = ID($mux); cell->type = ID($mux);
cell->parameters.erase(ID(S_WIDTH)); cell->parameters.erase(ID::S_WIDTH);
} }
did_something = true; did_something = true;
} }
} }
#define FOLD_1ARG_CELL(_t) \ #define FOLD_1ARG_CELL(_t) \
if (cell->type == "$" #_t) { \ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \ RTLIL::SigSpec a = cell->getPort(ID::A); \
assign_map.apply(a); \ assign_map.apply(a); \
if (a.is_fully_const()) { \ if (a.is_fully_const()) { \
RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \ RTLIL::Const dummy_arg(RTLIL::State::S0, 1); \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), dummy_arg, \
cell->parameters[ID(A_SIGNED)].as_bool(), false, \ cell->parameters[ID::A_SIGNED].as_bool(), false, \
cell->parameters[ID(Y_WIDTH)].as_int())); \ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \ cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \ replace_cell(assign_map, module, cell, stringf("%s", log_signal(a)), ID::Y, y); \
goto next_cell; \ goto next_cell; \
} \ } \
} }
#define FOLD_2ARG_CELL(_t) \ #define FOLD_2ARG_CELL(_t) \
if (cell->type == "$" #_t) { \ if (cell->type == ID($##_t)) { \
RTLIL::SigSpec a = cell->getPort(ID::A); \ RTLIL::SigSpec a = cell->getPort(ID::A); \
RTLIL::SigSpec b = cell->getPort(ID::B); \ RTLIL::SigSpec b = cell->getPort(ID::B); \
assign_map.apply(a), assign_map.apply(b); \ assign_map.apply(a), assign_map.apply(b); \
if (a.is_fully_const() && b.is_fully_const()) { \ if (a.is_fully_const() && b.is_fully_const()) { \
RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \ RTLIL::SigSpec y(RTLIL::const_ ## _t(a.as_const(), b.as_const(), \
cell->parameters[ID(A_SIGNED)].as_bool(), \ cell->parameters[ID::A_SIGNED].as_bool(), \
cell->parameters[ID(B_SIGNED)].as_bool(), \ cell->parameters[ID::B_SIGNED].as_bool(), \
cell->parameters[ID(Y_WIDTH)].as_int())); \ cell->parameters[ID::Y_WIDTH].as_int())); \
cover("opt.opt_expr.const.$" #_t); \ cover("opt.opt_expr.const.$" #_t); \
replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \ replace_cell(assign_map, module, cell, stringf("%s, %s", log_signal(a), log_signal(b)), ID::Y, y); \
goto next_cell; \ goto next_cell; \
@ -1354,7 +1354,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
// be very conservative with optimizing $mux cells as we do not want to break mux trees // be very conservative with optimizing $mux cells as we do not want to break mux trees
if (cell->type == ID($mux)) { if (cell->type == ID($mux)) {
RTLIL::SigSpec input = assign_map(cell->getPort(ID(S))); RTLIL::SigSpec input = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec inA = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec inB = assign_map(cell->getPort(ID::B));
if (input.is_fully_const()) if (input.is_fully_const())
@ -1365,8 +1365,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!keepdc && cell->type == ID($mul)) if (!keepdc && cell->type == ID($mul))
{ {
bool a_signed = cell->parameters[ID(A_SIGNED)].as_bool(); bool a_signed = cell->parameters[ID::A_SIGNED].as_bool();
bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool(); bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
bool swapped_ab = false; bool swapped_ab = false;
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
@ -1407,8 +1407,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!swapped_ab) { if (!swapped_ab) {
cell->setPort(ID::A, cell->getPort(ID::B)); cell->setPort(ID::A, cell->getPort(ID::B));
cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH)); cell->parameters.at(ID::A_WIDTH) = cell->parameters.at(ID::B_WIDTH);
cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED)); cell->parameters.at(ID::A_SIGNED) = cell->parameters.at(ID::B_SIGNED);
} }
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6); std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
@ -1417,8 +1417,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.pop_back(); new_b.pop_back();
cell->type = ID($shl); cell->type = ID($shl);
cell->parameters[ID(B_WIDTH)] = GetSize(new_b); cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->parameters[ID(B_SIGNED)] = false; cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
cell->check(); cell->check();
@ -1430,7 +1430,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!keepdc && cell->type.in(ID($div), ID($mod))) if (!keepdc && cell->type.in(ID($div), ID($mod)))
{ {
bool b_signed = cell->parameters[ID(B_SIGNED)].as_bool(); bool b_signed = cell->parameters[ID::B_SIGNED].as_bool();
SigSpec sig_b = assign_map(cell->getPort(ID::B)); SigSpec sig_b = assign_map(cell->getPort(ID::B));
SigSpec sig_y = assign_map(cell->getPort(ID::Y)); SigSpec sig_y = assign_map(cell->getPort(ID::Y));
@ -1468,8 +1468,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.pop_back(); new_b.pop_back();
cell->type = ID($shr); cell->type = ID($shr);
cell->parameters[ID(B_WIDTH)] = GetSize(new_b); cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->parameters[ID(B_SIGNED)] = false; cell->parameters[ID::B_SIGNED] = false;
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
cell->check(); cell->check();
} }
@ -1486,7 +1486,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
new_b.push_back(State::S0); new_b.push_back(State::S0);
cell->type = ID($and); cell->type = ID($and);
cell->parameters[ID(B_WIDTH)] = GetSize(new_b); cell->parameters[ID::B_WIDTH] = GetSize(new_b);
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
cell->check(); cell->check();
} }
@ -1507,10 +1507,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
contradiction_cache.promote(State::S0); contradiction_cache.promote(State::S0);
contradiction_cache.promote(State::S1); contradiction_cache.promote(State::S1);
int a_width = cell->getParam(ID(A_WIDTH)).as_int(); int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID(B_WIDTH)).as_int(); int b_width = cell->getParam(ID::B_WIDTH).as_int();
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width); int width = is_signed ? std::min(a_width, b_width) : std::max(a_width, b_width);
SigSpec sig_a = cell->getPort(ID::A); SigSpec sig_a = cell->getPort(ID::A);
@ -1564,8 +1564,8 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
cell->setPort(ID::A, sig_a); cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b); cell->setPort(ID::B, sig_b);
cell->setParam(ID(A_WIDTH), GetSize(sig_a)); cell->setParam(ID::A_WIDTH, GetSize(sig_a));
cell->setParam(ID(B_WIDTH), GetSize(sig_b)); cell->setParam(ID::B_WIDTH, GetSize(sig_b));
did_something = true; did_something = true;
goto next_cell; goto next_cell;
@ -1578,9 +1578,9 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
IdString cmp_type = cell->type; IdString cmp_type = cell->type;
SigSpec var_sig = cell->getPort(ID::A); SigSpec var_sig = cell->getPort(ID::A);
SigSpec const_sig = cell->getPort(ID::B); SigSpec const_sig = cell->getPort(ID::B);
int var_width = cell->parameters[ID(A_WIDTH)].as_int(); int var_width = cell->parameters[ID::A_WIDTH].as_int();
int const_width = cell->parameters[ID(B_WIDTH)].as_int(); int const_width = cell->parameters[ID::B_WIDTH].as_int();
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool(); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
if (!const_sig.is_fully_const()) if (!const_sig.is_fully_const())
{ {

22
passes/opt/opt_lut.cc
View file

@ -41,8 +41,8 @@ struct OptLutWorker
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs) bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{ {
SigSpec lut_input = sigmap(lut->getPort(ID::A)); SigSpec lut_input = sigmap(lut->getPort(ID::A));
int lut_width = lut->getParam(ID(WIDTH)).as_int(); int lut_width = lut->getParam(ID::WIDTH).as_int();
Const lut_table = lut->getParam(ID(LUT)); Const lut_table = lut->getParam(ID::LUT);
int lut_index = 0; int lut_index = 0;
for (int i = 0; i < lut_width; i++) for (int i = 0; i < lut_width; i++)
@ -107,7 +107,7 @@ struct OptLutWorker
if (lut_output.wire->get_bool_attribute(ID::keep)) if (lut_output.wire->get_bool_attribute(ID::keep))
continue; continue;
int lut_width = cell->getParam(ID(WIDTH)).as_int(); int lut_width = cell->getParam(ID::WIDTH).as_int();
SigSpec lut_input = cell->getPort(ID::A); SigSpec lut_input = cell->getPort(ID::A);
int lut_arity = 0; int lut_arity = 0;
@ -305,7 +305,7 @@ struct OptLutWorker
auto lutA = worklist.pop(); auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A)); SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]); SigSpec lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
int lutA_width = lutA->getParam(ID(WIDTH)).as_int(); int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA]; int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA]; pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
@ -323,7 +323,7 @@ struct OptLutWorker
auto lutB = port.cell; auto lutB = port.cell;
SigSpec lutB_input = sigmap(lutB->getPort(ID::A)); SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]); SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
int lutB_width = lutB->getParam(ID(WIDTH)).as_int(); int lutB_width = lutB->getParam(ID::WIDTH).as_int();
int lutB_arity = luts_arity[lutB]; int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB]; pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
@ -372,7 +372,7 @@ struct OptLutWorker
log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n"); log_debug(" Not combining LUTs into cell A (combined LUT wider than cell A).\n");
else if (lutB_dlogic_inputs.size() > 0) else if (lutB_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n"); log_debug(" Not combining LUTs into cell A (cell B is connected to dedicated logic).\n");
else if (lutB->get_bool_attribute(ID(lut_keep))) else if (lutB->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n"); log_debug(" Not combining LUTs into cell A (cell B has attribute \\lut_keep).\n");
else else
combine_mask |= COMBINE_A; combine_mask |= COMBINE_A;
@ -380,7 +380,7 @@ struct OptLutWorker
log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n"); log_debug(" Not combining LUTs into cell B (combined LUT wider than cell B).\n");
else if (lutA_dlogic_inputs.size() > 0) else if (lutA_dlogic_inputs.size() > 0)
log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n"); log_debug(" Not combining LUTs into cell B (cell A is connected to dedicated logic).\n");
else if (lutA->get_bool_attribute(ID(lut_keep))) else if (lutA->get_bool_attribute(ID::lut_keep))
log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n"); log_debug(" Not combining LUTs into cell B (cell A has attribute \\lut_keep).\n");
else else
combine_mask |= COMBINE_B; combine_mask |= COMBINE_B;
@ -440,7 +440,7 @@ struct OptLutWorker
lutR_unique.insert(bit); lutR_unique.insert(bit);
} }
int lutM_width = lutM->getParam(ID(WIDTH)).as_int(); int lutM_width = lutM->getParam(ID::WIDTH).as_int();
SigSpec lutM_input = sigmap(lutM->getPort(ID::A)); SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
std::vector<SigBit> lutM_new_inputs; std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++) for (int i = 0; i < lutM_width; i++)
@ -482,11 +482,11 @@ struct OptLutWorker
lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs); lutM_new_table[eval] = (RTLIL::State) evaluate_lut(lutB, eval_inputs);
} }
log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID(LUT)).as_string().c_str()); log_debug(" Cell A truth table: %s.\n", lutA->getParam(ID::LUT).as_string().c_str());
log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID(LUT)).as_string().c_str()); log_debug(" Cell B truth table: %s.\n", lutB->getParam(ID::LUT).as_string().c_str());
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str()); log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string().c_str());
lutM->setParam(ID(LUT), lutM_new_table); lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs); lutM->setPort(ID::A, lutM_new_inputs);
lutM->setPort(ID::Y, lutB_output); lutM->setPort(ID::Y, lutB_output);

26
passes/opt/opt_lut_ins.cc
View file

@ -80,7 +80,7 @@ struct OptLutInsPass : public Pass {
continue; continue;
inputs = cell->getPort(ID::A).bits(); inputs = cell->getPort(ID::A).bits();
output = cell->getPort(ID::Y); output = cell->getPort(ID::Y);
lut = cell->getParam(ID(LUT)); lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin") { } else if (techname == "xilinx" || techname == "gowin") {
if (cell->type == ID(LUT1)) { if (cell->type == ID(LUT1)) {
inputs = { inputs = {
@ -125,20 +125,20 @@ struct OptLutInsPass : public Pass {
// Not a LUT. // Not a LUT.
continue; continue;
} }
lut = cell->getParam(ID(INIT)); lut = cell->getParam(ID::INIT);
if (techname == "xilinx") if (techname == "xilinx")
output = cell->getPort(ID(O)); output = cell->getPort(ID::O);
else else
output = cell->getPort(ID(F)); output = cell->getPort(ID::F);
} else if (techname == "ecp5") { } else if (techname == "ecp5") {
if (cell->type == ID(LUT4)) { if (cell->type == ID(LUT4)) {
inputs = { inputs = {
cell->getPort(ID::A), cell->getPort(ID::A),
cell->getPort(ID::B), cell->getPort(ID::B),
cell->getPort(ID(C)), cell->getPort(ID::C),
cell->getPort(ID(D)), cell->getPort(ID::D),
}; };
lut = cell->getParam(ID(INIT)); lut = cell->getParam(ID::INIT);
output = cell->getPort(ID(Z)); output = cell->getPort(ID(Z));
ignore_const = true; ignore_const = true;
} else { } else {
@ -217,19 +217,19 @@ struct OptLutInsPass : public Pass {
module->connect(output, new_lut[0]); module->connect(output, new_lut[0]);
} else { } else {
if (techname == "") { if (techname == "") {
cell->setParam(ID(LUT), new_lut); cell->setParam(ID::LUT, new_lut);
cell->setParam(ID(WIDTH), GetSize(new_inputs)); cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs); cell->setPort(ID::A, new_inputs);
} else if (techname == "ecp5") { } else if (techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4); log_assert(GetSize(new_inputs) == 4);
cell->setParam(ID(INIT), new_lut); cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]); cell->setPort(ID::A, new_inputs[0]);
cell->setPort(ID::B, new_inputs[1]); cell->setPort(ID::B, new_inputs[1]);
cell->setPort(ID(C), new_inputs[2]); cell->setPort(ID::C, new_inputs[2]);
cell->setPort(ID(D), new_inputs[3]); cell->setPort(ID::D, new_inputs[3]);
} else { } else {
// xilinx, gowin // xilinx, gowin
cell->setParam(ID(INIT), new_lut); cell->setParam(ID::INIT, new_lut);
if (techname == "xilinx") if (techname == "xilinx")
log_assert(GetSize(new_inputs) <= 6); log_assert(GetSize(new_inputs) <= 6);
else else

6
passes/opt/opt_mem.cc
View file

@ -45,17 +45,17 @@ struct OptMemWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type == ID($memrd)) { if (cell->type == ID($memrd)) {
IdString id = cell->getParam(ID(MEMID)).decode_string(); IdString id = cell->getParam(ID::MEMID).decode_string();
memrd.at(id).push_back(cell->name); memrd.at(id).push_back(cell->name);
} }
if (cell->type == ID($memwr)) { if (cell->type == ID($memwr)) {
IdString id = cell->getParam(ID(MEMID)).decode_string(); IdString id = cell->getParam(ID::MEMID).decode_string();
memwr.at(id).push_back(cell->name); memwr.at(id).push_back(cell->name);
} }
if (cell->type == ID($meminit)) { if (cell->type == ID($meminit)) {
IdString id = cell->getParam(ID(MEMID)).decode_string(); IdString id = cell->getParam(ID::MEMID).decode_string();
meminit.at(id).push_back(cell->name); meminit.at(id).push_back(cell->name);
} }
} }

26
passes/opt/opt_merge.cc
View file

@ -44,7 +44,7 @@ struct OptMergeWorker
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn) static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
{ {
SigSpec sig_s = conn.at(ID(S)); SigSpec sig_s = conn.at(ID::S);
SigSpec sig_b = conn.at(ID::B); SigSpec sig_b = conn.at(ID::B);
int s_width = GetSize(sig_s); int s_width = GetSize(sig_s);
@ -56,11 +56,11 @@ struct OptMergeWorker
std::sort(sb_pairs.begin(), sb_pairs.end()); std::sort(sb_pairs.begin(), sb_pairs.end());
conn[ID(S)] = SigSpec(); conn[ID::S] = SigSpec();
conn[ID::B] = SigSpec(); conn[ID::B] = SigSpec();
for (auto &it : sb_pairs) { for (auto &it : sb_pairs) {
conn[ID(S)].append(it.first); conn[ID::S].append(it.first);
conn[ID::B].append(it.second); conn[ID::B].append(it.second);
} }
} }
@ -110,7 +110,7 @@ struct OptMergeWorker
alt_conn = *conn; alt_conn = *conn;
assign_map.apply(alt_conn.at(ID::A)); assign_map.apply(alt_conn.at(ID::A));
assign_map.apply(alt_conn.at(ID::B)); assign_map.apply(alt_conn.at(ID::B));
assign_map.apply(alt_conn.at(ID(S))); assign_map.apply(alt_conn.at(ID::S));
sort_pmux_conn(alt_conn); sort_pmux_conn(alt_conn);
conn = &alt_conn; conn = &alt_conn;
} }
@ -118,9 +118,9 @@ struct OptMergeWorker
for (auto &it : *conn) { for (auto &it : *conn) {
RTLIL::SigSpec sig; RTLIL::SigSpec sig;
if (cell->output(it.first)) { if (cell->output(it.first)) {
if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) { cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
// For the 'Q' output of state elements, // For the 'Q' output of state elements,
// use its (* init *) attribute value // use its (* init *) attribute value
for (const auto &b : dff_init_map(it.second)) for (const auto &b : dff_init_map(it.second))
@ -175,9 +175,9 @@ struct OptMergeWorker
for (const auto &it : cell1->connections_) { for (const auto &it : cell1->connections_) {
if (cell1->output(it.first)) { if (cell1->output(it.first)) {
if (it.first == ID(Q) && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") || if (it.first == ID::Q && (cell1->type.begins_with("$dff") || cell1->type.begins_with("$dlatch") ||
cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") || cell1->type.begins_with("$_DFF") || cell1->type.begins_with("$_DLATCH") || cell1->type.begins_with("$_SR_") ||
cell1->type.in("$adff", "$sr", "$ff", "$_FF_"))) { cell1->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
// For the 'Q' output of state elements, // For the 'Q' output of state elements,
// use the (* init *) attribute value // use the (* init *) attribute value
auto &sig1 = conn1[it.first]; auto &sig1 = conn1[it.first];
@ -253,8 +253,8 @@ struct OptMergeWorker
dff_init_map.set(module); dff_init_map.set(module);
for (auto &it : module->wires_) for (auto &it : module->wires_)
if (it.second->attributes.count(ID(init)) != 0) { if (it.second->attributes.count(ID::init) != 0) {
Const initval = it.second->attributes.at(ID(init)); Const initval = it.second->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(it.second); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(it.second, i), initval[i]); dff_init_map.add(SigBit(it.second, i), initval[i]);
@ -300,11 +300,11 @@ struct OptMergeWorker
module->connect(RTLIL::SigSig(it.second, other_sig)); module->connect(RTLIL::SigSig(it.second, other_sig));
assign_map.add(it.second, other_sig); assign_map.add(it.second, other_sig);
if (it.first == ID(Q) && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") || if (it.first == ID::Q && (cell->type.begins_with("$dff") || cell->type.begins_with("$dlatch") ||
cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") || cell->type.begins_with("$_DFF") || cell->type.begins_with("$_DLATCH") || cell->type.begins_with("$_SR_") ||
cell->type.in("$adff", "$sr", "$ff", "$_FF_"))) { cell->type.in(ID($adff), ID($sr), ID($ff), ID($_FF_)))) {
for (auto c : it.second.chunks()) { for (auto c : it.second.chunks()) {
auto jt = c.wire->attributes.find(ID(init)); auto jt = c.wire->attributes.find(ID::init);
if (jt == c.wire->attributes.end()) if (jt == c.wire->attributes.end())
continue; continue;
for (int i = c.offset; i < c.offset + c.width; i++) for (int i = c.offset; i < c.offset + c.width; i++)

12
passes/opt/opt_muxtree.cc
View file

@ -88,7 +88,7 @@ struct OptMuxtreeWorker
{ {
RTLIL::SigSpec sig_a = cell->getPort(ID::A); RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B); RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID(S)); RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y); RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
muxinfo_t muxinfo; muxinfo_t muxinfo;
@ -229,7 +229,7 @@ struct OptMuxtreeWorker
RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A); RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B); RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B);
RTLIL::SigSpec sig_s = mi.cell->getPort(ID(S)); RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y); RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y);
RTLIL::SigSpec sig_ports = sig_b; RTLIL::SigSpec sig_ports = sig_b;
@ -257,12 +257,12 @@ struct OptMuxtreeWorker
mi.cell->setPort(ID::A, new_sig_a); mi.cell->setPort(ID::A, new_sig_a);
mi.cell->setPort(ID::B, new_sig_b); mi.cell->setPort(ID::B, new_sig_b);
mi.cell->setPort(ID(S), new_sig_s); mi.cell->setPort(ID::S, new_sig_s);
if (GetSize(new_sig_s) == 1) { if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux); mi.cell->type = ID($mux);
mi.cell->parameters.erase(ID(S_WIDTH)); mi.cell->parameters.erase(ID::S_WIDTH);
} else { } else {
mi.cell->parameters[ID(S_WIDTH)] = RTLIL::Const(GetSize(new_sig_s)); mi.cell->parameters[ID::S_WIDTH] = RTLIL::Const(GetSize(new_sig_s));
} }
} }
} }
@ -366,7 +366,7 @@ struct OptMuxtreeWorker
idict<int> ctrl_bits; idict<int> ctrl_bits;
if (portname == ID::B) if (portname == ID::B)
width = GetSize(muxinfo.cell->getPort(ID::A)); width = GetSize(muxinfo.cell->getPort(ID::A));
for (int bit : sig2bits(muxinfo.cell->getPort(ID(S)), false)) for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false))
ctrl_bits(bit); ctrl_bits(bit);
int port_idx = 0, port_off = 0; int port_idx = 0, port_off = 0;

28
passes/opt/opt_reduce.cc
View file

@ -96,7 +96,7 @@ struct OptReduceWorker
} }
cell->setPort(ID::A, new_sig_a); cell->setPort(ID::A, new_sig_a);
cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return; return;
} }
@ -104,7 +104,7 @@ struct OptReduceWorker
{ {
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A)); RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B)); RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S))); RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec new_sig_b, new_sig_s; RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig; pool<RTLIL::SigSpec> handled_sig;
@ -127,9 +127,9 @@ struct OptReduceWorker
{ {
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or)); RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s); reduce_or_cell->setPort(ID::A, this_s);
reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0); reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size()); reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1); reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID); RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire); this_s = RTLIL::SigSpec(reduce_or_wire);
@ -156,12 +156,12 @@ struct OptReduceWorker
else else
{ {
cell->setPort(ID::B, new_sig_b); cell->setPort(ID::B, new_sig_b);
cell->setPort(ID(S), new_sig_s); cell->setPort(ID::S, new_sig_s);
if (new_sig_s.size() > 1) { if (new_sig_s.size() > 1) {
cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size()); cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else { } else {
cell->type = ID($mux); cell->type = ID($mux);
cell->parameters.erase(ID(S_WIDTH)); cell->parameters.erase(ID::S_WIDTH);
} }
} }
} }
@ -222,14 +222,14 @@ struct OptReduceWorker
} }
cell->setPort(ID::B, RTLIL::SigSpec()); cell->setPort(ID::B, RTLIL::SigSpec());
for (int i = 1; i <= cell->getPort(ID(S)).size(); i++) for (int i = 1; i <= cell->getPort(ID::S).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) { for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_b = cell->getPort(ID::B); RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.append(in_tuple.at(i)); new_b.append(in_tuple.at(i));
cell->setPort(ID::B, new_b); cell->setPort(ID::B, new_b);
} }
cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size());
cell->setPort(ID::Y, new_sig_y); cell->setPort(ID::Y, new_sig_y);
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)), log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
@ -255,14 +255,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) { for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second; RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mem)) if (cell->type == ID($mem))
mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN)))); mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
if (cell->type == ID($memwr)) if (cell->type == ID($memwr))
mem_wren_sigs.add(assign_map(cell->getPort(ID(EN)))); mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
} }
for (auto &cell_it : module->cells_) { for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second; RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q))))) if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(ID(D)))); mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
} }
bool keep_expanding_mem_wren_sigs = true; bool keep_expanding_mem_wren_sigs = true;

176
passes/opt/opt_rmdff.cc
View file

@ -41,7 +41,7 @@ void remove_init_attr(SigSpec sig)
for (auto bit : assign_map(sig)) for (auto bit : assign_map(sig))
if (init_attributes.count(bit)) if (init_attributes.count(bit))
for (auto wbit : init_attributes.at(bit)) for (auto wbit : init_attributes.at(bit))
wbit.wire->attributes.at(ID(init))[wbit.offset] = State::Sx; wbit.wire->attributes.at(ID::init)[wbit.offset] = State::Sx;
} }
bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell) bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
@ -49,17 +49,17 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
SigSpec sig_set, sig_clr; SigSpec sig_set, sig_clr;
State pol_set, pol_clr; State pol_set, pol_clr;
if (cell->hasPort(ID(S))) if (cell->hasPort(ID::S))
sig_set = cell->getPort(ID(S)); sig_set = cell->getPort(ID::S);
if (cell->hasPort(ID(R))) if (cell->hasPort(ID::R))
sig_clr = cell->getPort(ID(R)); sig_clr = cell->getPort(ID::R);
if (cell->hasPort(ID(SET))) if (cell->hasPort(ID::SET))
sig_set = cell->getPort(ID(SET)); sig_set = cell->getPort(ID::SET);
if (cell->hasPort(ID(CLR))) if (cell->hasPort(ID::CLR))
sig_clr = cell->getPort(ID(CLR)); sig_clr = cell->getPort(ID::CLR);
log_assert(GetSize(sig_set) == GetSize(sig_clr)); log_assert(GetSize(sig_set) == GetSize(sig_clr));
@ -72,16 +72,16 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else } else
if (cell->type.in(ID($dffsr), ID($dlatchsr))) { if (cell->type.in(ID($dffsr), ID($dlatchsr))) {
pol_set = cell->parameters[ID(SET_POLARITY)].as_bool() ? State::S1 : State::S0; pol_set = cell->parameters[ID::SET_POLARITY].as_bool() ? State::S1 : State::S0;
pol_clr = cell->parameters[ID(CLR_POLARITY)].as_bool() ? State::S1 : State::S0; pol_clr = cell->parameters[ID::CLR_POLARITY].as_bool() ? State::S1 : State::S0;
} else } else
log_abort(); log_abort();
State npol_set = pol_set == State::S0 ? State::S1 : State::S0; State npol_set = pol_set == State::S0 ? State::S1 : State::S0;
State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0; State npol_clr = pol_clr == State::S0 ? State::S1 : State::S0;
SigSpec sig_d = cell->getPort(ID(D)); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort(ID(Q)); SigSpec sig_q = cell->getPort(ID::Q);
bool did_something = false; bool did_something = false;
bool proper_sr = false; bool proper_sr = false;
@ -139,18 +139,18 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
if (cell->type.in(ID($dffsr), ID($dlatchsr))) if (cell->type.in(ID($dffsr), ID($dlatchsr)))
{ {
cell->setParam(ID(WIDTH), GetSize(sig_d)); cell->setParam(ID::WIDTH, GetSize(sig_d));
cell->setPort(ID(SET), sig_set); cell->setPort(ID::SET, sig_set);
cell->setPort(ID(CLR), sig_clr); cell->setPort(ID::CLR, sig_clr);
cell->setPort(ID(D), sig_d); cell->setPort(ID::D, sig_d);
cell->setPort(ID(Q), sig_q); cell->setPort(ID::Q, sig_q);
} }
else else
{ {
cell->setPort(ID(S), sig_set); cell->setPort(ID::S, sig_set);
cell->setPort(ID(R), sig_clr); cell->setPort(ID::R, sig_clr);
cell->setPort(ID(D), sig_d); cell->setPort(ID::D, sig_d);
cell->setPort(ID(Q), sig_q); cell->setPort(ID::Q, sig_q);
} }
if (proper_sr) if (proper_sr)
@ -171,24 +171,24 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod)); log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$adff", log_id(mod));
cell->type = ID($adff); cell->type = ID($adff);
cell->setParam(ID(ARST_POLARITY), unified_pol); cell->setParam(ID::ARST_POLARITY, unified_pol);
cell->setParam(ID(ARST_VALUE), reset_val); cell->setParam(ID::ARST_VALUE, reset_val);
cell->setPort(ID(ARST), sig_reset); cell->setPort(ID::ARST, sig_reset);
cell->unsetParam(ID(SET_POLARITY)); cell->unsetParam(ID::SET_POLARITY);
cell->unsetParam(ID(CLR_POLARITY)); cell->unsetParam(ID::CLR_POLARITY);
cell->unsetPort(ID(SET)); cell->unsetPort(ID::SET);
cell->unsetPort(ID(CLR)); cell->unsetPort(ID::CLR);
} }
else else
{ {
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod)); log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), "$dff", log_id(mod));
cell->type = ID($dff); cell->type = ID($dff);
cell->unsetParam(ID(SET_POLARITY)); cell->unsetParam(ID::SET_POLARITY);
cell->unsetParam(ID(CLR_POLARITY)); cell->unsetParam(ID::CLR_POLARITY);
cell->unsetPort(ID(SET)); cell->unsetPort(ID::SET);
cell->unsetPort(ID(CLR)); cell->unsetPort(ID::CLR);
} }
return true; return true;
@ -208,8 +208,8 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod)); log("Converting %s (%s) to %s in module %s.\n", log_id(cell), log_id(cell->type), log_id(new_type), log_id(mod));
cell->type = new_type; cell->type = new_type;
cell->unsetPort(ID(S)); cell->unsetPort(ID::S);
cell->unsetPort(ID(R)); cell->unsetPort(ID::R);
return true; return true;
} }
@ -223,17 +223,17 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
State on_state, off_state; State on_state, off_state;
if (dlatch->type == ID($dlatch)) { if (dlatch->type == ID($dlatch)) {
sig_e = assign_map(dlatch->getPort(ID(EN))); sig_e = assign_map(dlatch->getPort(ID::EN));
on_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S1 : State::S0; on_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S1 : State::S0;
off_state = dlatch->getParam(ID(EN_POLARITY)).as_bool() ? State::S0 : State::S1; off_state = dlatch->getParam(ID::EN_POLARITY).as_bool() ? State::S0 : State::S1;
} else } else
if (dlatch->type == ID($_DLATCH_P_)) { if (dlatch->type == ID($_DLATCH_P_)) {
sig_e = assign_map(dlatch->getPort(ID(E))); sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S1; on_state = State::S1;
off_state = State::S0; off_state = State::S0;
} else } else
if (dlatch->type == ID($_DLATCH_N_)) { if (dlatch->type == ID($_DLATCH_N_)) {
sig_e = assign_map(dlatch->getPort(ID(E))); sig_e = assign_map(dlatch->getPort(ID::E));
on_state = State::S0; on_state = State::S0;
off_state = State::S1; off_state = State::S1;
} else } else
@ -242,15 +242,15 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
if (sig_e == off_state) if (sig_e == off_state)
{ {
RTLIL::Const val_init; RTLIL::Const val_init;
for (auto bit : dff_init_map(dlatch->getPort(ID(Q)))) for (auto bit : dff_init_map(dlatch->getPort(ID::Q)))
val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx); val_init.bits.push_back(bit.wire == NULL ? bit.data : State::Sx);
mod->connect(dlatch->getPort(ID(Q)), val_init); mod->connect(dlatch->getPort(ID::Q), val_init);
goto delete_dlatch; goto delete_dlatch;
} }
if (sig_e == on_state) if (sig_e == on_state)
{ {
mod->connect(dlatch->getPort(ID(Q)), dlatch->getPort(ID(D))); mod->connect(dlatch->getPort(ID::Q), dlatch->getPort(ID::D));
goto delete_dlatch; goto delete_dlatch;
} }
@ -258,7 +258,7 @@ bool handle_dlatch(RTLIL::Module *mod, RTLIL::Cell *dlatch)
delete_dlatch: delete_dlatch:
log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod)); log("Removing %s (%s) from module %s.\n", log_id(dlatch), log_id(dlatch->type), log_id(mod));
remove_init_attr(dlatch->getPort(ID(Q))); remove_init_attr(dlatch->getPort(ID::Q));
mod->remove(dlatch); mod->remove(dlatch);
return true; return true;
} }
@ -269,23 +269,23 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
RTLIL::Const val_cp, val_rp, val_rv, val_ep; RTLIL::Const val_cp, val_rp, val_rv, val_ep;
if (dff->type == ID($_FF_)) { if (dff->type == ID($_FF_)) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
} }
else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) { else if (dff->type == ID($_DFF_N_) || dff->type == ID($_DFF_P_)) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(C)); sig_c = dff->getPort(ID::C);
val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1); val_cp = RTLIL::Const(dff->type == ID($_DFF_P_), 1);
} }
else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 && else if (dff->type.begins_with("$_DFF_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) { (dff->type[8] == '0' || dff->type[8] == '1')) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(C)); sig_c = dff->getPort(ID::C);
sig_r = dff->getPort(ID(R)); sig_r = dff->getPort(ID::R);
val_cp = RTLIL::Const(dff->type[6] == 'P', 1); val_cp = RTLIL::Const(dff->type[6] == 'P', 1);
val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1);
@ -293,39 +293,39 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 && else if (dff->type.begins_with("$_DFFE_") && dff->type.compare(9, 1, "_") == 0 &&
(dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == 'N' || dff->type[8] == 'P')) { (dff->type[8] == 'N' || dff->type[8] == 'P')) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(C)); sig_c = dff->getPort(ID::C);
sig_e = dff->getPort(ID(E)); sig_e = dff->getPort(ID::E);
val_cp = RTLIL::Const(dff->type[7] == 'P', 1); val_cp = RTLIL::Const(dff->type[7] == 'P', 1);
val_ep = RTLIL::Const(dff->type[8] == 'P', 1); val_ep = RTLIL::Const(dff->type[8] == 'P', 1);
} }
else if (dff->type == ID($ff)) { else if (dff->type == ID($ff)) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
} }
else if (dff->type == ID($dff)) { else if (dff->type == ID($dff)) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(CLK)); sig_c = dff->getPort(ID::CLK);
val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
} }
else if (dff->type == ID($dffe)) { else if (dff->type == ID($dffe)) {
sig_e = dff->getPort(ID(EN)); sig_e = dff->getPort(ID::EN);
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(CLK)); sig_c = dff->getPort(ID::CLK);
val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
val_ep = RTLIL::Const(dff->parameters[ID(EN_POLARITY)].as_bool(), 1); val_ep = RTLIL::Const(dff->parameters[ID::EN_POLARITY].as_bool(), 1);
} }
else if (dff->type == ID($adff)) { else if (dff->type == ID($adff)) {
sig_d = dff->getPort(ID(D)); sig_d = dff->getPort(ID::D);
sig_q = dff->getPort(ID(Q)); sig_q = dff->getPort(ID::Q);
sig_c = dff->getPort(ID(CLK)); sig_c = dff->getPort(ID::CLK);
sig_r = dff->getPort(ID(ARST)); sig_r = dff->getPort(ID::ARST);
val_cp = RTLIL::Const(dff->parameters[ID(CLK_POLARITY)].as_bool(), 1); val_cp = RTLIL::Const(dff->parameters[ID::CLK_POLARITY].as_bool(), 1);
val_rp = RTLIL::Const(dff->parameters[ID(ARST_POLARITY)].as_bool(), 1); val_rp = RTLIL::Const(dff->parameters[ID::ARST_POLARITY].as_bool(), 1);
val_rv = dff->parameters[ID(ARST_VALUE)]; val_rv = dff->parameters[ID::ARST_VALUE];
} }
else else
log_abort(); log_abort();
@ -422,15 +422,15 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
if (dff->type == ID($adff)) { if (dff->type == ID($adff)) {
dff->type = ID($dff); dff->type = ID($dff);
dff->unsetPort(ID(ARST)); dff->unsetPort(ID::ARST);
dff->unsetParam(ID(ARST_POLARITY)); dff->unsetParam(ID::ARST_POLARITY);
dff->unsetParam(ID(ARST_VALUE)); dff->unsetParam(ID::ARST_VALUE);
return true; return true;
} }
log_assert(dff->type.begins_with("$_DFF_")); log_assert(dff->type.begins_with("$_DFF_"));
dff->type = stringf("$_DFF_%c_", + dff->type[6]); dff->type = stringf("$_DFF_%c_", + dff->type[6]);
dff->unsetPort(ID(R)); dff->unsetPort(ID::R);
} }
// If enable signal is present, and is fully constant // If enable signal is present, and is fully constant
@ -447,14 +447,14 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
if (dff->type == ID($dffe)) { if (dff->type == ID($dffe)) {
dff->type = ID($dff); dff->type = ID($dff);
dff->unsetPort(ID(EN)); dff->unsetPort(ID::EN);
dff->unsetParam(ID(EN_POLARITY)); dff->unsetParam(ID::EN_POLARITY);
return true; return true;
} }
log_assert(dff->type.begins_with("$_DFFE_")); log_assert(dff->type.begins_with("$_DFFE_"));
dff->type = stringf("$_DFF_%c_", + dff->type[7]); dff->type = stringf("$_DFF_%c_", + dff->type[7]);
dff->unsetPort(ID(E)); dff->unsetPort(ID::E);
} }
if (sat && has_init && (!sig_r.size() || val_init == val_rv)) if (sat && has_init && (!sig_r.size() || val_init == val_rv))
@ -509,9 +509,9 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0, log("Setting constant %d-bit at position %d on %s (%s) from module %s.\n", sigbit_init_val ? 1 : 0,
position, log_id(dff), log_id(dff->type), log_id(mod)); position, log_id(dff), log_id(dff->type), log_id(mod));
SigSpec tmp = dff->getPort(ID(D)); SigSpec tmp = dff->getPort(ID::D);
tmp[position] = sigbit_init_val; tmp[position] = sigbit_init_val;
dff->setPort(ID(D), tmp); dff->setPort(ID::D, tmp);
removed_sigbits = true; removed_sigbits = true;
} }
@ -528,7 +528,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
delete_dff: delete_dff:
log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod)); log("Removing %s (%s) from module %s.\n", log_id(dff), log_id(dff->type), log_id(mod));
remove_init_attr(dff->getPort(ID(Q))); remove_init_attr(dff->getPort(ID::Q));
mod->remove(dff); mod->remove(dff);
for (auto &entry : bit2driver) for (auto &entry : bit2driver)
@ -588,8 +588,8 @@ struct OptRmdffPass : public Pass {
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
if (wire->attributes.count(ID(init)) != 0) { if (wire->attributes.count(ID::init) != 0) {
Const initval = wire->attributes.at(ID(init)); Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1) if (initval[i] == State::S0 || initval[i] == State::S1)
dff_init_map.add(SigBit(wire, i), initval[i]); dff_init_map.add(SigBit(wire, i), initval[i]);

32
passes/opt/opt_share.cc
View file

@ -98,8 +98,8 @@ struct ExtSigSpec {
bool cell_supported(RTLIL::Cell *cell) bool cell_supported(RTLIL::Cell *cell)
{ {
if (cell->type.in(ID($alu))) { if (cell->type.in(ID($alu))) {
RTLIL::SigSpec sig_bi = cell->getPort(ID(BI)); RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(ID(CI)); RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci) if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true; return true;
@ -139,7 +139,7 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) { RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
if (cell->type == ID($alu) && port_name == ID::B) if (cell->type == ID($alu) && port_name == ID::B)
return cell->getPort(ID(BI)); return cell->getPort(ID::BI);
else if (cell->type == ID($sub) && port_name == ID::B) else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1); return RTLIL::Const(1, 1);
@ -190,7 +190,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto shared_op = ports[0].op; auto shared_op = ports[0].op;
if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; })) if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int()); max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
for (auto &operand : muxed_operands) for (auto &operand : muxed_operands)
@ -210,7 +210,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec mux_y = mux->getPort(ID::Y); RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
RTLIL::SigSpec mux_a = mux->getPort(ID::A); RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B); RTLIL::SigSpec mux_b = mux->getPort(ID::B);
RTLIL::SigSpec mux_s = mux->getPort(ID(S)); RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width); RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
RTLIL::SigSpec shared_pmux_b; RTLIL::SigSpec shared_pmux_b;
@ -237,7 +237,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
mux->setPort(ID::A, mux_a); mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b); mux->setPort(ID::B, mux_b);
mux->setPort(ID::Y, mux_y); mux->setPort(ID::Y, mux_y);
mux->setPort(ID(S), mux_s); mux->setPort(ID::S, mux_s);
for (const auto &op : muxed_operands) for (const auto &op : muxed_operands)
shared_pmux_b.append(op.sig); shared_pmux_b.append(op.sig);
@ -245,26 +245,26 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s); auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
if (shared_op->type.in(ID($alu))) { if (shared_op->type.in(ID($alu))) {
RTLIL::SigSpec alu_x = shared_op->getPort(ID(X)); RTLIL::SigSpec alu_x = shared_op->getPort(ID::X);
RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO)); RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO);
shared_op->setPort(ID(X), alu_x.extract(0, conn_width)); shared_op->setPort(ID::X, alu_x.extract(0, conn_width));
shared_op->setPort(ID(CO), alu_co.extract(0, conn_width)); shared_op->setPort(ID::CO, alu_co.extract(0, conn_width));
} }
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS); bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
if (!is_fine) if (!is_fine)
shared_op->setParam(ID(Y_WIDTH), conn_width); shared_op->setParam(ID::Y_WIDTH, conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) { if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper); shared_op->setPort(ID::B, mux_to_oper);
if (!is_fine) if (!is_fine)
shared_op->setParam(ID(B_WIDTH), max_width); shared_op->setParam(ID::B_WIDTH, max_width);
} else { } else {
shared_op->setPort(ID::A, mux_to_oper); shared_op->setPort(ID::A, mux_to_oper);
if (!is_fine) if (!is_fine)
shared_op->setParam(ID(A_WIDTH), max_width); shared_op->setParam(ID::A_WIDTH, max_width);
} }
} }
@ -452,7 +452,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) { if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
remove_connected_ops(cell->getPort(ID(S))); remove_connected_ops(cell->getPort(ID::S));
find_op_mux_conns(cell); find_op_mux_conns(cell);
} else { } else {
for (auto &conn : cell->connections()) for (auto &conn : cell->connections())
@ -510,7 +510,7 @@ struct OptSharePass : public Pass {
continue; continue;
if (cell->type == ID($alu)) { if (cell->type == ID($alu)) {
for (RTLIL::IdString port_name : {ID(X), ID(CO)}) { for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
auto mux_insig = assign_map(cell->getPort(port_name)); auto mux_insig = assign_map(cell->getPort(port_name));
outsig_to_operator[mux_insig] = cell; outsig_to_operator[mux_insig] = cell;
for (auto outbit : mux_insig) for (auto outbit : mux_insig)
@ -552,7 +552,7 @@ struct OptSharePass : public Pass {
if (p.mux->type.in(ID($mux), ID($_MUX_))) if (p.mux->type.in(ID($mux), ID($_MUX_)))
mux_port_num = 2; mux_port_num = 2;
else else
mux_port_num = p.mux->getPort(ID(S)).size(); mux_port_num = p.mux->getPort(ID::S).size();
mux_port_conns.resize(mux_port_num); mux_port_conns.resize(mux_port_num);
} }

34
passes/opt/pmux2shiftx.cc
View file

@ -46,7 +46,7 @@ struct OnehotDatabase
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
auto it = wire->attributes.find(ID(init)); auto it = wire->attributes.find(ID::init);
if (it == wire->attributes.end()) if (it == wire->attributes.end())
continue; continue;
@ -65,10 +65,10 @@ struct OnehotDatabase
if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff))) if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
{ {
output = cell->getPort(ID(Q)); output = cell->getPort(ID::Q);
if (cell->type == ID($adff)) if (cell->type == ID($adff))
inputs.push_back(cell->getParam(ID(ARST_VALUE))); inputs.push_back(cell->getParam(ID::ARST_VALUE));
inputs.push_back(cell->getPort(ID(D))); inputs.push_back(cell->getPort(ID::D));
} }
if (cell->type.in(ID($mux), ID($pmux))) if (cell->type.in(ID($mux), ID($pmux)))
@ -299,16 +299,16 @@ struct Pmux2ShiftxPass : public Pass {
SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B)); SigSpec B = sigmap(cell->getPort(ID::B));
int a_width = cell->getParam(ID(A_WIDTH)).as_int(); int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID(B_WIDTH)).as_int(); int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) { if (a_width < b_width) {
bool a_signed = cell->getParam(ID(A_SIGNED)).as_int(); bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed); A.extend_u0(b_width, a_signed);
} }
if (b_width < a_width) { if (b_width < a_width) {
bool b_signed = cell->getParam(ID(B_SIGNED)).as_int(); bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed); B.extend_u0(a_width, b_signed);
} }
@ -368,7 +368,7 @@ struct Pmux2ShiftxPass : public Pass {
continue; continue;
string src = cell->get_src_attribute(); string src = cell->get_src_attribute();
int width = cell->getParam(ID(WIDTH)).as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int width_bits = ceil_log2(width); int width_bits = ceil_log2(width);
int extwidth = width; int extwidth = width;
@ -379,7 +379,7 @@ struct Pmux2ShiftxPass : public Pass {
SigSpec A = cell->getPort(ID::A); SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B); SigSpec B = cell->getPort(ID::B);
SigSpec S = sigmap(cell->getPort(ID(S))); SigSpec S = sigmap(cell->getPort(ID::S));
for (int i = 0; i < GetSize(S); i++) for (int i = 0; i < GetSize(S); i++)
{ {
if (!eqdb.count(S[i])) if (!eqdb.count(S[i]))
@ -400,7 +400,7 @@ struct Pmux2ShiftxPass : public Pass {
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits); log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
} }
SigSpec updated_S = cell->getPort(ID(S)); SigSpec updated_S = cell->getPort(ID::S);
SigSpec updated_B = cell->getPort(ID::B); SigSpec updated_B = cell->getPort(ID::B);
while (!seldb.empty()) while (!seldb.empty())
@ -727,9 +727,9 @@ struct Pmux2ShiftxPass : public Pass {
} }
// update $pmux cell // update $pmux cell
cell->setPort(ID(S), updated_S); cell->setPort(ID::S, updated_S);
cell->setPort(ID::B, updated_B); cell->setPort(ID::B, updated_B);
cell->setParam(ID(S_WIDTH), GetSize(updated_S)); cell->setParam(ID::S_WIDTH, GetSize(updated_S));
} }
} }
} }
@ -785,16 +785,16 @@ struct OnehotPass : public Pass {
SigSpec A = sigmap(cell->getPort(ID::A)); SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B)); SigSpec B = sigmap(cell->getPort(ID::B));
int a_width = cell->getParam(ID(A_WIDTH)).as_int(); int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID(B_WIDTH)).as_int(); int b_width = cell->getParam(ID::B_WIDTH).as_int();
if (a_width < b_width) { if (a_width < b_width) {
bool a_signed = cell->getParam(ID(A_SIGNED)).as_int(); bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
A.extend_u0(b_width, a_signed); A.extend_u0(b_width, a_signed);
} }
if (b_width < a_width) { if (b_width < a_width) {
bool b_signed = cell->getParam(ID(B_SIGNED)).as_int(); bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
B.extend_u0(a_width, b_signed); B.extend_u0(a_width, b_signed);
} }

152
passes/opt/share.cc
View file

@ -90,7 +90,7 @@ struct ShareWorker
for (auto &pbit : portbits) { for (auto &pbit : portbits) {
if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) { if (pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) {
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID(S))).to_sigbit_pool(); pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end()); terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end()); queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell); visited_cells.insert(pbit.cell);
@ -331,7 +331,7 @@ struct ShareWorker
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y))); supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y))); supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
supercell->setParam(ID(Y_WIDTH), width); supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y); supercell->setPort(ID::Y, sig_y);
supermacc.optimize(width); supermacc.optimize(width);
@ -369,21 +369,21 @@ struct ShareWorker
} }
if (cell->type == ID($memrd)) { if (cell->type == ID($memrd)) {
if (cell->parameters.at(ID(CLK_ENABLE)).as_bool()) if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue; continue;
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID(ADDR))).is_fully_const()) if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
shareable_cells.insert(cell); shareable_cells.insert(cell);
continue; continue;
} }
if (cell->type.in(ID($mul), ID($div), ID($mod))) { if (cell->type.in(ID($mul), ID($div), ID($mod))) {
if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 4) if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 4)
shareable_cells.insert(cell); shareable_cells.insert(cell);
continue; continue;
} }
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) { if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr))) {
if (config.opt_aggressive || cell->parameters.at(ID(Y_WIDTH)).as_int() >= 8) if (config.opt_aggressive || cell->parameters.at(ID::Y_WIDTH).as_int() >= 8)
shareable_cells.insert(cell); shareable_cells.insert(cell);
continue; continue;
} }
@ -403,7 +403,7 @@ struct ShareWorker
if (c1->type == ID($memrd)) if (c1->type == ID($memrd))
{ {
if (c1->parameters.at(ID(MEMID)).decode_string() != c2->parameters.at(ID(MEMID)).decode_string()) if (c1->parameters.at(ID::MEMID).decode_string() != c2->parameters.at(ID::MEMID).decode_string())
return false; return false;
return true; return true;
@ -413,11 +413,11 @@ struct ShareWorker
{ {
if (!config.opt_aggressive) if (!config.opt_aggressive)
{ {
int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false; if (max(y1_width, y2_width) > 2 * min(y1_width, y2_width)) return false;
@ -430,13 +430,13 @@ struct ShareWorker
{ {
if (!config.opt_aggressive) if (!config.opt_aggressive)
{ {
int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int(); int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int(); int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false; if (max(a1_width, a2_width) > 2 * min(a1_width, a2_width)) return false;
if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false; if (max(b1_width, b2_width) > 2 * min(b1_width, b2_width)) return false;
@ -450,13 +450,13 @@ struct ShareWorker
{ {
if (!config.opt_aggressive) if (!config.opt_aggressive)
{ {
int a1_width = c1->parameters.at(ID(A_WIDTH)).as_int(); int a1_width = c1->parameters.at(ID::A_WIDTH).as_int();
int b1_width = c1->parameters.at(ID(B_WIDTH)).as_int(); int b1_width = c1->parameters.at(ID::B_WIDTH).as_int();
int y1_width = c1->parameters.at(ID(Y_WIDTH)).as_int(); int y1_width = c1->parameters.at(ID::Y_WIDTH).as_int();
int a2_width = c2->parameters.at(ID(A_WIDTH)).as_int(); int a2_width = c2->parameters.at(ID::A_WIDTH).as_int();
int b2_width = c2->parameters.at(ID(B_WIDTH)).as_int(); int b2_width = c2->parameters.at(ID::B_WIDTH).as_int();
int y2_width = c2->parameters.at(ID(Y_WIDTH)).as_int(); int y2_width = c2->parameters.at(ID::Y_WIDTH).as_int();
int min1_width = min(a1_width, b1_width); int min1_width = min(a1_width, b1_width);
int max1_width = max(a1_width, b1_width); int max1_width = max(a1_width, b1_width);
@ -510,21 +510,21 @@ struct ShareWorker
if (config.generic_uni_ops.count(c1->type)) if (config.generic_uni_ops.count(c1->type))
{ {
if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool()) if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{ {
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1; RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
new_a.append(RTLIL::State::S0); new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a); unsigned_cell->setPort(ID::A, new_a);
} }
unsigned_cell->parameters.at(ID(A_SIGNED)) = true; unsigned_cell->parameters.at(ID::A_SIGNED) = true;
unsigned_cell->check(); unsigned_cell->check();
} }
bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool(); bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool()); log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
RTLIL::SigSpec a1 = c1->getPort(ID::A); RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec y1 = c1->getPort(ID::Y); RTLIL::SigSpec y1 = c1->getPort(ID::Y);
@ -544,9 +544,9 @@ struct ShareWorker
RTLIL::Wire *y = module->addWire(NEW_ID, y_width); RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell->parameters[ID(A_SIGNED)] = a_signed; supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID(A_WIDTH)] = a_width; supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID(Y_WIDTH)] = y_width; supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a); supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y); supercell->setPort(ID::Y, y);
@ -563,11 +563,11 @@ struct ShareWorker
if (config.generic_cbin_ops.count(c1->type)) if (config.generic_cbin_ops.count(c1->type))
{ {
int score_unflipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()) + int score_unflipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int()) +
max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()); max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int());
int score_flipped = max(c1->parameters.at(ID(A_WIDTH)).as_int(), c2->parameters.at(ID(B_WIDTH)).as_int()) + int score_flipped = max(c1->parameters.at(ID::A_WIDTH).as_int(), c2->parameters.at(ID::B_WIDTH).as_int()) +
max(c1->parameters.at(ID(B_WIDTH)).as_int(), c2->parameters.at(ID(A_WIDTH)).as_int()); max(c1->parameters.at(ID::B_WIDTH).as_int(), c2->parameters.at(ID::A_WIDTH).as_int());
if (score_flipped < score_unflipped) if (score_flipped < score_unflipped)
{ {
@ -575,36 +575,36 @@ struct ShareWorker
c2->setPort(ID::A, c2->getPort(ID::B)); c2->setPort(ID::A, c2->getPort(ID::B));
c2->setPort(ID::B, tmp); c2->setPort(ID::B, tmp);
std::swap(c2->parameters.at(ID(A_WIDTH)), c2->parameters.at(ID(B_WIDTH))); std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH));
std::swap(c2->parameters.at(ID(A_SIGNED)), c2->parameters.at(ID(B_SIGNED))); std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED));
modified_src_cells = true; modified_src_cells = true;
} }
} }
if (c1->parameters.at(ID(A_SIGNED)).as_bool() != c2->parameters.at(ID(A_SIGNED)).as_bool()) if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{ {
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(A_SIGNED)).as_bool() ? c2 : c1; RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) { if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(A_WIDTH)) = unsigned_cell->parameters.at(ID(A_WIDTH)).as_int() + 1; unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A); RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
new_a.append(RTLIL::State::S0); new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a); unsigned_cell->setPort(ID::A, new_a);
} }
unsigned_cell->parameters.at(ID(A_SIGNED)) = true; unsigned_cell->parameters.at(ID::A_SIGNED) = true;
modified_src_cells = true; modified_src_cells = true;
} }
if (c1->parameters.at(ID(B_SIGNED)).as_bool() != c2->parameters.at(ID(B_SIGNED)).as_bool()) if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool())
{ {
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID(B_SIGNED)).as_bool() ? c2 : c1; RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) { if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID(B_WIDTH)) = unsigned_cell->parameters.at(ID(B_WIDTH)).as_int() + 1; unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B); RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
new_b.append(RTLIL::State::S0); new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b); unsigned_cell->setPort(ID::B, new_b);
} }
unsigned_cell->parameters.at(ID(B_SIGNED)) = true; unsigned_cell->parameters.at(ID::B_SIGNED) = true;
modified_src_cells = true; modified_src_cells = true;
} }
@ -613,11 +613,11 @@ struct ShareWorker
c2->check(); c2->check();
} }
bool a_signed = c1->parameters.at(ID(A_SIGNED)).as_bool(); bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
bool b_signed = c1->parameters.at(ID(B_SIGNED)).as_bool(); bool b_signed = c1->parameters.at(ID::B_SIGNED).as_bool();
log_assert(a_signed == c2->parameters.at(ID(A_SIGNED)).as_bool()); log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
log_assert(b_signed == c2->parameters.at(ID(B_SIGNED)).as_bool()); log_assert(b_signed == c2->parameters.at(ID::B_SIGNED).as_bool());
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr)) if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false; b_signed = false;
@ -664,32 +664,32 @@ struct ShareWorker
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr; RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
supercell->parameters[ID(A_SIGNED)] = a_signed; supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID(B_SIGNED)] = b_signed; supercell->parameters[ID::B_SIGNED] = b_signed;
supercell->parameters[ID(A_WIDTH)] = a_width; supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID(B_WIDTH)] = b_width; supercell->parameters[ID::B_WIDTH] = b_width;
supercell->parameters[ID(Y_WIDTH)] = y_width; supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a); supercell->setPort(ID::A, a);
supercell->setPort(ID::B, b); supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y); supercell->setPort(ID::Y, y);
if (c1->type == ID($alu)) { if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID); RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(CI)), c1->getPort(ID(CI)), act, ci)); supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID(BI)), c1->getPort(ID(BI)), act, bi)); supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
supercell->setPort(ID(CI), ci); supercell->setPort(ID::CI, ci);
supercell->setPort(ID(BI), bi); supercell->setPort(ID::BI, bi);
supercell->setPort(ID(CO), co); supercell->setPort(ID::CO, co);
supercell->setPort(ID(X), x); supercell->setPort(ID::X, x);
} }
supercell->check(); supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1)); supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2)); supercell_aux.insert(module->addPos(NEW_ID, y, y2));
if (c1->type == ID($alu)) { if (c1->type == ID($alu)) {
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID(CO)))); supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID(CO)))); supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID(X)))); supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID(X)))); supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
} }
supercell_aux.insert(supercell); supercell_aux.insert(supercell);
@ -708,15 +708,15 @@ struct ShareWorker
if (c1->type == ID($memrd)) if (c1->type == ID($memrd))
{ {
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1); RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID(ADDR)); RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(ID(ADDR)); RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
if (GetSize(addr1) < GetSize(addr2)) if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2)); addr1.extend_u0(GetSize(addr2));
else else
addr2.extend_u0(GetSize(addr1)); addr2.extend_u0(GetSize(addr1));
supercell->setPort(ID(ADDR), addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1); supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->parameters[ID(ABITS)] = RTLIL::Const(GetSize(addr1)); supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID(DATA)), c2->getPort(ID(DATA)))); supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(supercell); supercell_aux.insert(supercell);
return supercell; return supercell;
} }
@ -747,8 +747,8 @@ struct ShareWorker
modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]); modwalker.get_consumers(pbits, modwalker.cell_outputs[cell]);
for (auto &bit : pbits) { for (auto &bit : pbits) {
if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID(S)) if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S)
forbidden_controls_cache[cell].insert(bit.cell->getPort(ID(S)).extract(bit.offset, 1)); forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1));
consumer_cells.insert(bit.cell); consumer_cells.insert(bit.cell);
} }
@ -890,10 +890,10 @@ struct ShareWorker
bool used_in_a = false; bool used_in_a = false;
std::set<int> used_in_b_parts; std::set<int> used_in_b_parts;
int width = c->parameters.at(ID(WIDTH)).as_int(); int width = c->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A)); std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B)); std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID(S))); std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S));
for (auto &bit : sig_a) for (auto &bit : sig_a)
if (cell_out_bits.count(bit)) if (cell_out_bits.count(bit))
@ -1171,8 +1171,8 @@ struct ShareWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
if (cell->type == ID($pmux)) if (cell->type == ID($pmux))
for (auto bit : cell->getPort(ID(S))) for (auto bit : cell->getPort(ID::S))
for (auto other_bit : cell->getPort(ID(S))) for (auto other_bit : cell->getPort(ID::S))
if (bit < other_bit) if (bit < other_bit)
exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit)); exclusive_ctrls.push_back(std::pair<RTLIL::SigBit, RTLIL::SigBit>(bit, other_bit));

58
passes/opt/wreduce.cc
View file

@ -65,7 +65,7 @@ struct WreduceWorker
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)); SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_b = mi.sigmap(cell->getPort(ID::B)); SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_s = mi.sigmap(cell->getPort(ID(S))); SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y)); SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
std::vector<SigBit> bits_removed; std::vector<SigBit> bits_removed;
@ -141,8 +141,8 @@ struct WreduceWorker
{ {
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used // Reduce size of FF if inputs are just sign/zero extended or output bit is not used
SigSpec sig_d = mi.sigmap(cell->getPort(ID(D))); SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q))); SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
bool is_adff = (cell->type == ID($adff)); bool is_adff = (cell->type == ID($adff));
Const initval, arst_value; Const initval, arst_value;
@ -151,8 +151,8 @@ struct WreduceWorker
if (width_before == 0) if (width_before == 0)
return; return;
if (cell->parameters.count(ID(ARST_VALUE))) { if (cell->parameters.count(ID::ARST_VALUE)) {
arst_value = cell->parameters[ID(ARST_VALUE)]; arst_value = cell->parameters[ID::ARST_VALUE];
} }
bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
@ -220,13 +220,13 @@ struct WreduceWorker
work_queue_bits.insert(bit); work_queue_bits.insert(bit);
// Narrow ARST_VALUE parameter to new size. // Narrow ARST_VALUE parameter to new size.
if (cell->parameters.count(ID(ARST_VALUE))) { if (cell->parameters.count(ID::ARST_VALUE)) {
arst_value.bits.resize(GetSize(sig_q)); arst_value.bits.resize(GetSize(sig_q));
cell->setParam(ID(ARST_VALUE), arst_value); cell->setParam(ID::ARST_VALUE, arst_value);
} }
cell->setPort(ID(D), sig_d); cell->setPort(ID::D, sig_d);
cell->setPort(ID(Q), sig_q); cell->setPort(ID::Q, sig_q);
cell->fixup_parameters(); cell->fixup_parameters();
} }
@ -306,8 +306,8 @@ struct WreduceWorker
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n", log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type)); log_id(module), log_id(cell), log_id(cell->type));
cell->setParam(ID(A_SIGNED), 0); cell->setParam(ID::A_SIGNED, 0);
cell->setParam(ID(B_SIGNED), 0); cell->setParam(ID::B_SIGNED, 0);
port_a_signed = false; port_a_signed = false;
port_b_signed = false; port_b_signed = false;
did_something = true; did_something = true;
@ -319,7 +319,7 @@ struct WreduceWorker
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n", log("Converting cell %s.%s (%s) from signed to unsigned.\n",
log_id(module), log_id(cell), log_id(cell->type)); log_id(module), log_id(cell), log_id(cell->type));
cell->setParam(ID(A_SIGNED), 0); cell->setParam(ID::A_SIGNED, 0);
port_a_signed = false; port_a_signed = false;
did_something = true; did_something = true;
} }
@ -349,7 +349,7 @@ struct WreduceWorker
if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub))) if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
{ {
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub); bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0; int a_size = 0, b_size = 0;
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A)); if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
@ -392,8 +392,8 @@ struct WreduceWorker
static int count_nontrivial_wire_attrs(RTLIL::Wire *w) static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
{ {
int count = w->attributes.size(); int count = w->attributes.size();
count -= w->attributes.count(ID(src)); count -= w->attributes.count(ID::src);
count -= w->attributes.count(ID(unused_bits)); count -= w->attributes.count(ID::unused_bits);
return count; return count;
} }
@ -406,8 +406,8 @@ struct WreduceWorker
if (w->get_bool_attribute(ID::keep)) if (w->get_bool_attribute(ID::keep))
for (auto bit : mi.sigmap(w)) for (auto bit : mi.sigmap(w))
keep_bits.insert(bit); keep_bits.insert(bit);
if (w->attributes.count(ID(init))) { if (w->attributes.count(ID::init)) {
Const initval = w->attributes.at(ID(init)); Const initval = w->attributes.at(ID::init);
SigSpec initsig = init_attr_sigmap(w); SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig)); int width = std::min(GetSize(initval), GetSize(initsig));
for (int i = 0; i < width; i++) for (int i = 0; i < width; i++)
@ -464,8 +464,8 @@ struct WreduceWorker
if (!remove_init_bits.empty()) { if (!remove_init_bits.empty()) {
for (auto w : module->wires()) { for (auto w : module->wires()) {
if (w->attributes.count(ID(init))) { if (w->attributes.count(ID::init)) {
Const initval = w->attributes.at(ID(init)); Const initval = w->attributes.at(ID::init);
Const new_initval(State::Sx, GetSize(w)); Const new_initval(State::Sx, GetSize(w));
SigSpec initsig = init_attr_sigmap(w); SigSpec initsig = init_attr_sigmap(w);
int width = std::min(GetSize(initval), GetSize(initsig)); int width = std::min(GetSize(initval), GetSize(initsig));
@ -473,7 +473,7 @@ struct WreduceWorker
if (!remove_init_bits.count(initsig[i])) if (!remove_init_bits.count(initsig[i]))
new_initval[i] = initval[i]; new_initval[i] = initval[i];
} }
w->attributes.at(ID(init)) = new_initval; w->attributes.at(ID::init) = new_initval;
} }
} }
} }
@ -539,7 +539,7 @@ struct WreducePass : public Pass {
SigSpec sig = c->getPort(ID::Y); SigSpec sig = c->getPort(ID::Y);
if (!sig.has_const()) { if (!sig.has_const()) {
c->setPort(ID::Y, sig[0]); c->setPort(ID::Y, sig[0]);
c->setParam(ID(Y_WIDTH), 1); c->setParam(ID::Y_WIDTH, 1);
sig.remove(0); sig.remove(0);
module->connect(sig, Const(0, GetSize(sig))); module->connect(sig, Const(0, GetSize(sig)));
} }
@ -549,7 +549,7 @@ struct WreducePass : public Pass {
{ {
SigSpec A = c->getPort(ID::A); SigSpec A = c->getPort(ID::A);
int original_a_width = GetSize(A); int original_a_width = GetSize(A);
if (c->getParam(ID(A_SIGNED)).as_bool()) { if (c->getParam(ID::A_SIGNED).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0) while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
A.remove(GetSize(A)-1, 1); A.remove(GetSize(A)-1, 1);
} else { } else {
@ -560,12 +560,12 @@ struct WreducePass : public Pass {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n", log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type)); original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::A, A); c->setPort(ID::A, A);
c->setParam(ID(A_WIDTH), GetSize(A)); c->setParam(ID::A_WIDTH, GetSize(A));
} }
SigSpec B = c->getPort(ID::B); SigSpec B = c->getPort(ID::B);
int original_b_width = GetSize(B); int original_b_width = GetSize(B);
if (c->getParam(ID(B_SIGNED)).as_bool()) { if (c->getParam(ID::B_SIGNED).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0) while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
B.remove(GetSize(B)-1, 1); B.remove(GetSize(B)-1, 1);
} else { } else {
@ -576,23 +576,23 @@ struct WreducePass : public Pass {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n", log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type)); original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
c->setPort(ID::B, B); c->setPort(ID::B, B);
c->setParam(ID(B_WIDTH), GetSize(B)); c->setParam(ID::B_WIDTH, GetSize(B));
} }
} }
if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) { if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam(ID(MEMID)).decode_string(); IdString memid = c->getParam(ID::MEMID).decode_string();
RTLIL::Memory *mem = module->memories.at(memid); RTLIL::Memory *mem = module->memories.at(memid);
if (mem->start_offset >= 0) { if (mem->start_offset >= 0) {
int cur_addrbits = c->getParam(ID(ABITS)).as_int(); int cur_addrbits = c->getParam(ID::ABITS).as_int();
int max_addrbits = ceil_log2(mem->start_offset + mem->size); int max_addrbits = ceil_log2(mem->start_offset + mem->size);
if (cur_addrbits > max_addrbits) { if (cur_addrbits > max_addrbits) {
log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n", log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
cur_addrbits-max_addrbits, cur_addrbits, cur_addrbits-max_addrbits, cur_addrbits,
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init", c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
log_id(module), log_id(c), log_id(memid)); log_id(module), log_id(c), log_id(memid));
c->setParam(ID(ABITS), max_addrbits); c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits)); c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
} }
} }
} }

46
passes/pmgen/ice40_dsp.cc
View file

@ -73,11 +73,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Input Interface // SB_MAC16 Input Interface
SigSpec A = st.sigA; SigSpec A = st.sigA;
A.extend_u0(16, st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool()); A.extend_u0(16, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
log_assert(GetSize(A) == 16); log_assert(GetSize(A) == 16);
SigSpec B = st.sigB; SigSpec B = st.sigB;
B.extend_u0(16, st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool()); B.extend_u0(16, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
log_assert(GetSize(B) == 16); log_assert(GetSize(B) == 16);
SigSpec CD = st.sigCD; SigSpec CD = st.sigCD;
@ -88,8 +88,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort(ID::A, A); cell->setPort(ID::A, A);
cell->setPort(ID::B, B); cell->setPort(ID::B, B);
cell->setPort(ID(C), CD.extract(16, 16)); cell->setPort(ID::C, CD.extract(16, 16));
cell->setPort(ID(D), CD.extract(0, 16)); cell->setPort(ID::D, CD.extract(0, 16));
cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0); cell->setParam(ID(A_REG), st.ffA ? State::S1 : State::S0);
cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0); cell->setParam(ID(B_REG), st.ffB ? State::S1 : State::S0);
@ -98,15 +98,15 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec AHOLD, BHOLD, CDHOLD; SigSpec AHOLD, BHOLD, CDHOLD;
if (st.ffAholdmux) if (st.ffAholdmux)
AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID(S))); AHOLD = st.ffAholdpol ? st.ffAholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffAholdmux->getPort(ID::S));
else else
AHOLD = State::S0; AHOLD = State::S0;
if (st.ffBholdmux) if (st.ffBholdmux)
BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID(S))); BHOLD = st.ffBholdpol ? st.ffBholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBholdmux->getPort(ID::S));
else else
BHOLD = State::S0; BHOLD = State::S0;
if (st.ffCDholdmux) if (st.ffCDholdmux)
CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID(S))); CDHOLD = st.ffCDholdpol ? st.ffCDholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffCDholdmux->getPort(ID::S));
else else
CDHOLD = State::S0; CDHOLD = State::S0;
cell->setPort(ID(AHOLD), AHOLD); cell->setPort(ID(AHOLD), AHOLD);
@ -116,11 +116,11 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec IRSTTOP, IRSTBOT; SigSpec IRSTTOP, IRSTBOT;
if (st.ffArstmux) if (st.ffArstmux)
IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID(S))); IRSTTOP = st.ffArstpol ? st.ffArstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffArstmux->getPort(ID::S));
else else
IRSTTOP = State::S0; IRSTTOP = State::S0;
if (st.ffBrstmux) if (st.ffBrstmux)
IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID(S))); IRSTBOT = st.ffBrstpol ? st.ffBrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffBrstmux->getPort(ID::S));
else else
IRSTBOT = State::S0; IRSTBOT = State::S0;
cell->setPort(ID(IRSTTOP), IRSTTOP); cell->setPort(ID(IRSTTOP), IRSTTOP);
@ -128,7 +128,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (st.clock != SigBit()) if (st.clock != SigBit())
{ {
cell->setPort(ID(CLK), st.clock); cell->setPort(ID::CLK, st.clock);
cell->setPort(ID(CE), State::S1); cell->setPort(ID(CE), State::S1);
cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1); cell->setParam(ID(NEG_TRIGGER), st.clock_pol ? State::S0 : State::S1);
@ -156,7 +156,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
} }
else else
{ {
cell->setPort(ID(CLK), State::S0); cell->setPort(ID::CLK, State::S0);
cell->setPort(ID(CE), State::S0); cell->setPort(ID(CE), State::S0);
cell->setParam(ID(NEG_TRIGGER), State::S0); cell->setParam(ID(NEG_TRIGGER), State::S0);
} }
@ -166,7 +166,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setPort(ID(SIGNEXTIN), State::Sx); cell->setPort(ID(SIGNEXTIN), State::Sx);
cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID)); cell->setPort(ID(SIGNEXTOUT), pm.module->addWire(NEW_ID));
cell->setPort(ID(CI), State::Sx); cell->setPort(ID::CI, State::Sx);
cell->setPort(ID(ACCUMCI), State::Sx); cell->setPort(ID(ACCUMCI), State::Sx);
cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID)); cell->setPort(ID(ACCUMCO), pm.module->addWire(NEW_ID));
@ -178,19 +178,19 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
if (O_width == 33) { if (O_width == 33) {
log_assert(st.add); log_assert(st.add);
// If we have a signed multiply-add, then perform sign extension // If we have a signed multiply-add, then perform sign extension
if (st.add->getParam(ID(A_SIGNED)).as_bool() && st.add->getParam(ID(B_SIGNED)).as_bool()) if (st.add->getParam(ID::A_SIGNED).as_bool() && st.add->getParam(ID::B_SIGNED).as_bool())
pm.module->connect(O[32], O[31]); pm.module->connect(O[32], O[31]);
else else
cell->setPort(ID(CO), O[32]); cell->setPort(ID::CO, O[32]);
O.remove(O_width-1); O.remove(O_width-1);
} }
else else
cell->setPort(ID(CO), pm.module->addWire(NEW_ID)); cell->setPort(ID::CO, pm.module->addWire(NEW_ID));
log_assert(GetSize(O) <= 32); log_assert(GetSize(O) <= 32);
if (GetSize(O) < 32) if (GetSize(O) < 32)
O.append(pm.module->addWire(NEW_ID, 32-GetSize(O))); O.append(pm.module->addWire(NEW_ID, 32-GetSize(O)));
cell->setPort(ID(O), O); cell->setPort(ID::O, O);
bool accum = false; bool accum = false;
if (st.add) { if (st.add) {
@ -208,7 +208,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec OHOLD; SigSpec OHOLD;
if (st.ffOholdmux) if (st.ffOholdmux)
OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID(S))); OHOLD = st.ffOholdpol ? st.ffOholdmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOholdmux->getPort(ID::S));
else else
OHOLD = State::S0; OHOLD = State::S0;
cell->setPort(ID(OHOLDTOP), OHOLD); cell->setPort(ID(OHOLDTOP), OHOLD);
@ -216,7 +216,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec ORST; SigSpec ORST;
if (st.ffOrstmux) if (st.ffOrstmux)
ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID(S)) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID(S))); ORST = st.ffOrstpol ? st.ffOrstmux->getPort(ID::S) : pm.module->Not(NEW_ID, st.ffOrstmux->getPort(ID::S));
else else
ORST = State::S0; ORST = State::S0;
cell->setPort(ID(ORSTTOP), ORST); cell->setPort(ID(ORSTTOP), ORST);
@ -225,9 +225,9 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec acc_reset = State::S0; SigSpec acc_reset = State::S0;
if (st.mux) { if (st.mux) {
if (st.muxAB == ID::A) if (st.muxAB == ID::A)
acc_reset = st.mux->getPort(ID(S)); acc_reset = st.mux->getPort(ID::S);
else else
acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID(S))); acc_reset = pm.module->Not(NEW_ID, st.mux->getPort(ID::S));
} }
cell->setPort(ID(OLOADTOP), acc_reset); cell->setPort(ID(OLOADTOP), acc_reset);
cell->setPort(ID(OLOADBOT), acc_reset); cell->setPort(ID(OLOADBOT), acc_reset);
@ -248,8 +248,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2)); cell->setParam(ID(BOTADDSUB_CARRYSELECT), Const(0, 2));
cell->setParam(ID(MODE_8x8), State::S0); cell->setParam(ID(MODE_8x8), State::S0);
cell->setParam(ID(A_SIGNED), st.mul->parameters.at(ID(A_SIGNED), State::S0).as_bool()); cell->setParam(ID::A_SIGNED, st.mul->parameters.at(ID::A_SIGNED, State::S0).as_bool());
cell->setParam(ID(B_SIGNED), st.mul->parameters.at(ID(B_SIGNED), State::S0).as_bool()); cell->setParam(ID::B_SIGNED, st.mul->parameters.at(ID::B_SIGNED, State::S0).as_bool());
if (st.ffO) { if (st.ffO) {
if (st.o_lo) if (st.o_lo)
@ -257,7 +257,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
else else
cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2)); cell->setParam(ID(TOPOUTPUT_SELECT), Const(1, 2));
st.ffO->connections_.at(ID(Q)).replace(O, pm.module->addWire(NEW_ID, GetSize(O))); st.ffO->connections_.at(ID::Q).replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2)); cell->setParam(ID(BOTOUTPUT_SELECT), Const(1, 2));
} }
else { else {

52
passes/pmgen/ice40_wrapcarry.cc
View file

@ -37,26 +37,26 @@ void create_ice40_wrapcarry(ice40_wrapcarry_pm &pm)
log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n"); log(" replacing SB_LUT + SB_CARRY with $__ICE40_CARRY_WRAPPER cell.\n");
Cell *cell = pm.module->addCell(NEW_ID, "$__ICE40_CARRY_WRAPPER"); Cell *cell = pm.module->addCell(NEW_ID, ID($__ICE40_CARRY_WRAPPER));
pm.module->swap_names(cell, st.carry); pm.module->swap_names(cell, st.carry);
cell->setPort(ID::A, st.carry->getPort("\\I0")); cell->setPort(ID::A, st.carry->getPort(ID(I0)));
cell->setPort(ID::B, st.carry->getPort("\\I1")); cell->setPort(ID::B, st.carry->getPort(ID(I1)));
auto CI = st.carry->getPort("\\CI"); auto CI = st.carry->getPort(ID::CI);
cell->setPort("\\CI", CI); cell->setPort(ID::CI, CI);
cell->setPort("\\CO", st.carry->getPort("\\CO")); cell->setPort(ID::CO, st.carry->getPort(ID::CO));
cell->setPort("\\I0", st.lut->getPort("\\I0")); cell->setPort(ID(I0), st.lut->getPort(ID(I0)));
auto I3 = st.lut->getPort("\\I3"); auto I3 = st.lut->getPort(ID(I3));
if (pm.sigmap(CI) == pm.sigmap(I3)) { if (pm.sigmap(CI) == pm.sigmap(I3)) {
cell->setParam("\\I3_IS_CI", State::S1); cell->setParam(ID(I3_IS_CI), State::S1);
I3 = State::Sx; I3 = State::Sx;
} }
else else
cell->setParam("\\I3_IS_CI", State::S0); cell->setParam(ID(I3_IS_CI), State::S0);
cell->setPort("\\I3", I3); cell->setPort(ID(I3), I3);
cell->setPort("\\O", st.lut->getPort("\\O")); cell->setPort(ID::O, st.lut->getPort(ID::O));
cell->setParam("\\LUT", st.lut->getParam("\\LUT_INIT")); cell->setParam(ID::LUT, st.lut->getParam(ID(LUT_INIT)));
for (const auto &a : st.carry->attributes) for (const auto &a : st.carry->attributes)
cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second; cell->attributes[stringf("\\SB_CARRY.%s", a.first.c_str())] = a.second;
@ -117,18 +117,18 @@ struct Ice40WrapCarryPass : public Pass {
continue; continue;
auto carry = module->addCell(NEW_ID, ID(SB_CARRY)); auto carry = module->addCell(NEW_ID, ID(SB_CARRY));
carry->setPort(ID(I0), cell->getPort(ID(A))); carry->setPort(ID(I0), cell->getPort(ID::A));
carry->setPort(ID(I1), cell->getPort(ID(B))); carry->setPort(ID(I1), cell->getPort(ID::B));
carry->setPort(ID(CI), cell->getPort(ID(CI))); carry->setPort(ID::CI, cell->getPort(ID::CI));
carry->setPort(ID(CO), cell->getPort(ID(CO))); carry->setPort(ID::CO, cell->getPort(ID::CO));
module->swap_names(carry, cell); module->swap_names(carry, cell);
auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string(); auto lut_name = cell->attributes.at(ID(SB_LUT4.name), Const(NEW_ID.str())).decode_string();
auto lut = module->addCell(lut_name, ID($lut)); auto lut = module->addCell(lut_name, ID($lut));
lut->setParam(ID(WIDTH), 4); lut->setParam(ID::WIDTH, 4);
lut->setParam(ID(LUT), cell->getParam(ID(LUT))); lut->setParam(ID::LUT, cell->getParam(ID::LUT));
auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3));
lut->setPort(ID(A), { I3, cell->getPort(ID(B)), cell->getPort(ID(A)), cell->getPort(ID(I0)) }); lut->setPort(ID::A, { I3, cell->getPort(ID::B), cell->getPort(ID::A), cell->getPort(ID(I0)) });
lut->setPort(ID(Y), cell->getPort(ID(O))); lut->setPort(ID::Y, cell->getPort(ID::O));
Const src; Const src;
for (const auto &a : cell->attributes) for (const auto &a : cell->attributes)
@ -136,16 +136,16 @@ struct Ice40WrapCarryPass : public Pass {
carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second; carry->attributes[a.first.c_str() + strlen("\\SB_CARRY.")] = a.second;
else if (a.first.begins_with("\\SB_LUT4.\\")) else if (a.first.begins_with("\\SB_LUT4.\\"))
lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second; lut->attributes[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
else if (a.first == ID(src)) else if (a.first == ID::src)
src = a.second; src = a.second;
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived))) else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
continue; continue;
else else
log_abort(); log_abort();
if (!src.empty()) { if (!src.empty()) {
carry->attributes.insert(std::make_pair(ID(src), src)); carry->attributes.insert(std::make_pair(ID::src, src));
lut->attributes.insert(std::make_pair(ID(src), src)); lut->attributes.insert(std::make_pair(ID::src, src));
} }
module->remove(cell); module->remove(cell);

4
passes/pmgen/peepopt.cc
View file

@ -87,7 +87,7 @@ struct PeepoptPass : public Pass {
peepopt_pm pm(module); peepopt_pm pm(module);
for (auto w : module->wires()) { for (auto w : module->wires()) {
auto it = w->attributes.find(ID(init)); auto it = w->attributes.find(ID::init);
if (it != w->attributes.end()) { if (it != w->attributes.end()) {
SigSpec sig = pm.sigmap(w); SigSpec sig = pm.sigmap(w);
Const val = it->second; Const val = it->second;
@ -109,7 +109,7 @@ struct PeepoptPass : public Pass {
pm.run_dffmux(); pm.run_dffmux();
for (auto w : module->wires()) { for (auto w : module->wires()) {
auto it = w->attributes.find(ID(init)); auto it = w->attributes.find(ID::init);
if (it != w->attributes.end()) { if (it != w->attributes.end()) {
SigSpec sig = pm.sigmap(w); SigSpec sig = pm.sigmap(w);
Const &val = it->second; Const &val = it->second;

10
passes/pmgen/test_pmgen.cc
View file

@ -40,16 +40,16 @@ void reduce_chain(test_pmgen_pm &pm)
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type)); log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), log_id(st.first->type));
SigSpec A; SigSpec A;
SigSpec Y = ud.longest_chain.front().first->getPort(ID(Y)); SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
auto last_cell = ud.longest_chain.back().first; auto last_cell = ud.longest_chain.back().first;
for (auto it : ud.longest_chain) { for (auto it : ud.longest_chain) {
auto cell = it.first; auto cell = it.first;
if (cell == last_cell) { if (cell == last_cell) {
A.append(cell->getPort(ID(A))); A.append(cell->getPort(ID::A));
A.append(cell->getPort(ID(B))); A.append(cell->getPort(ID::B));
} else { } else {
A.append(cell->getPort(it.second == ID(A) ? ID(B) : ID(A))); A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
} }
log(" %s\n", log_id(cell)); log(" %s\n", log_id(cell));
pm.autoremove(cell); pm.autoremove(cell);
@ -78,7 +78,7 @@ void reduce_tree(test_pmgen_pm &pm)
return; return;
SigSpec A = ud.leaves; SigSpec A = ud.leaves;
SigSpec Y = st.first->getPort(ID(Y)); SigSpec Y = st.first->getPort(ID::Y);
pm.autoremove(st.first); pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type), log("Found %s tree with %d leaves for %s (%s).\n", log_id(st.first->type),

188
passes/pmgen/xilinx_dsp.cc
View file

@ -52,7 +52,7 @@ static Cell* addDsp(Module *module) {
cell->setParam(ID(USE_SIMD), Const("ONE48")); cell->setParam(ID(USE_SIMD), Const("ONE48"));
cell->setParam(ID(USE_DPORT), Const("FALSE")); cell->setParam(ID(USE_DPORT), Const("FALSE"));
cell->setPort(ID(D), Const(0, 25)); cell->setPort(ID::D, Const(0, 25));
cell->setPort(ID(INMODE), Const(0, 5)); cell->setPort(ID(INMODE), Const(0, 5));
cell->setPort(ID(ALUMODE), Const(0, 4)); cell->setPort(ID(ALUMODE), Const(0, 4));
cell->setPort(ID(OPMODE), Const(0, 7)); cell->setPort(ID(OPMODE), Const(0, 7));
@ -72,15 +72,15 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
for (auto cell : selected_cells) { for (auto cell : selected_cells) {
if (!cell->type.in(ID($add), ID($sub))) if (!cell->type.in(ID($add), ID($sub)))
continue; continue;
SigSpec Y = cell->getPort(ID(Y)); SigSpec Y = cell->getPort(ID::Y);
if (!Y.is_chunk()) if (!Y.is_chunk())
continue; continue;
if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd")) if (!Y.as_chunk().wire->get_strpool_attribute(ID(use_dsp)).count("simd"))
continue; continue;
if (GetSize(Y) > 25) if (GetSize(Y) > 25)
continue; continue;
SigSpec A = cell->getPort(ID(A)); SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID(B)); SigSpec B = cell->getPort(ID::B);
if (GetSize(Y) <= 13) { if (GetSize(Y) <= 13) {
if (GetSize(A) > 12) if (GetSize(A) > 12)
continue; continue;
@ -106,11 +106,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
} }
auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { auto f12 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
SigSpec A = lane->getPort(ID(A)); SigSpec A = lane->getPort(ID::A);
SigSpec B = lane->getPort(ID(B)); SigSpec B = lane->getPort(ID::B);
SigSpec Y = lane->getPort(ID(Y)); SigSpec Y = lane->getPort(ID::Y);
A.extend_u0(12, lane->getParam(ID(A_SIGNED)).as_bool()); A.extend_u0(12, lane->getParam(ID::A_SIGNED).as_bool());
B.extend_u0(12, lane->getParam(ID(B_SIGNED)).as_bool()); B.extend_u0(12, lane->getParam(ID::B_SIGNED).as_bool());
AB.append(A); AB.append(A);
C.append(B); C.append(B);
if (GetSize(Y) < 13) if (GetSize(Y) < 13)
@ -174,10 +174,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
log_assert(GetSize(C) == 48); log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48); log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4); log_assert(GetSize(CARRYOUT) == 4);
cell->setPort(ID(A), AB.extract(18, 30)); cell->setPort(ID::A, AB.extract(18, 30));
cell->setPort(ID(B), AB.extract(0, 18)); cell->setPort(ID::B, AB.extract(0, 18));
cell->setPort(ID(C), C); cell->setPort(ID::C, C);
cell->setPort(ID(P), P); cell->setPort(ID::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT); cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub)) if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011")); cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@ -194,11 +194,11 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
g12(simd12_sub); g12(simd12_sub);
auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) { auto f24 = [module](SigSpec &AB, SigSpec &C, SigSpec &P, SigSpec &CARRYOUT, Cell *lane) {
SigSpec A = lane->getPort(ID(A)); SigSpec A = lane->getPort(ID::A);
SigSpec B = lane->getPort(ID(B)); SigSpec B = lane->getPort(ID::B);
SigSpec Y = lane->getPort(ID(Y)); SigSpec Y = lane->getPort(ID::Y);
A.extend_u0(24, lane->getParam(ID(A_SIGNED)).as_bool()); A.extend_u0(24, lane->getParam(ID::A_SIGNED).as_bool());
B.extend_u0(24, lane->getParam(ID(B_SIGNED)).as_bool()); B.extend_u0(24, lane->getParam(ID::B_SIGNED).as_bool());
C.append(A); C.append(A);
AB.append(B); AB.append(B);
if (GetSize(Y) < 25) if (GetSize(Y) < 25)
@ -238,10 +238,10 @@ void xilinx_simd_pack(Module *module, const std::vector<Cell*> &selected_cells)
log_assert(GetSize(C) == 48); log_assert(GetSize(C) == 48);
log_assert(GetSize(P) == 48); log_assert(GetSize(P) == 48);
log_assert(GetSize(CARRYOUT) == 4); log_assert(GetSize(CARRYOUT) == 4);
cell->setPort(ID(A), AB.extract(18, 30)); cell->setPort(ID::A, AB.extract(18, 30));
cell->setPort(ID(B), AB.extract(0, 18)); cell->setPort(ID::B, AB.extract(0, 18));
cell->setPort(ID(C), C); cell->setPort(ID::C, C);
cell->setPort(ID(P), P); cell->setPort(ID::P, P);
cell->setPort(ID(CARRYOUT), CARRYOUT); cell->setPort(ID(CARRYOUT), CARRYOUT);
if (lane1->type == ID($sub)) if (lane1->type == ID($sub))
cell->setPort(ID(ALUMODE), Const::from_string("0011")); cell->setPort(ID(ALUMODE), Const::from_string("0011"));
@ -280,19 +280,19 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.preAdd) { if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
bool A_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool(); bool A_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool D_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool(); bool D_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
if (st.sigA == st.preAdd->getPort(ID(B))) if (st.sigA == st.preAdd->getPort(ID::B))
std::swap(A_SIGNED, D_SIGNED); std::swap(A_SIGNED, D_SIGNED);
st.sigA.extend_u0(30, A_SIGNED); st.sigA.extend_u0(30, A_SIGNED);
st.sigD.extend_u0(25, D_SIGNED); st.sigD.extend_u0(25, D_SIGNED);
cell->setPort(ID(A), st.sigA); cell->setPort(ID::A, st.sigA);
cell->setPort(ID(D), st.sigD); cell->setPort(ID::D, st.sigD);
cell->setPort(ID(INMODE), Const::from_string("00100")); cell->setPort(ID(INMODE), Const::from_string("00100"));
if (st.ffAD) { if (st.ffAD) {
if (st.ffADcemux) { if (st.ffADcemux) {
SigSpec S = st.ffADcemux->getPort(ID(S)); SigSpec S = st.ffADcemux->getPort(ID::S);
cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(ID(CEAD), st.ffADcepol ? S : pm.module->Not(NEW_ID, S));
} }
else else
@ -310,7 +310,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec &opmode = cell->connections_.at(ID(OPMODE)); SigSpec &opmode = cell->connections_.at(ID(OPMODE));
if (st.postAddMux) { if (st.postAddMux) {
log_assert(st.ffP); log_assert(st.ffP);
opmode[4] = st.postAddMux->getPort(ID(S)); opmode[4] = st.postAddMux->getPort(ID::S);
pm.autoremove(st.postAddMux); pm.autoremove(st.postAddMux);
} }
else if (st.ffP && st.sigC == st.sigP) else if (st.ffP && st.sigC == st.sigP)
@ -321,11 +321,11 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
opmode[5] = State::S1; opmode[5] = State::S1;
if (opmode[4] != State::S0) { if (opmode[4] != State::S0) {
if (st.postAddMuxAB == ID(A)) if (st.postAddMuxAB == ID::A)
st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool()); st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else else
st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool()); st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID(C), st.sigC); cell->setPort(ID::C, st.sigC);
} }
pm.autoremove(st.postAdd); pm.autoremove(st.postAdd);
@ -337,7 +337,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(SEL_MASK), Const("MASK")); cell->setParam(ID(SEL_MASK), Const("MASK"));
if (st.overflow->type == ID($ge)) { if (st.overflow->type == ID($ge)) {
Const B = st.overflow->getPort(ID(B)).as_const(); Const B = st.overflow->getPort(ID::B).as_const();
log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1); log_assert(std::count(B.bits.begin(), B.bits.end(), State::S1) == 1);
// Since B is an exact power of 2, subtract 1 // Since B is an exact power of 2, subtract 1
// by inverting all bits up until hitting // by inverting all bits up until hitting
@ -352,7 +352,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(MASK), B); cell->setParam(ID(MASK), B);
cell->setParam(ID(PATTERN), Const(0, 48)); cell->setParam(ID(PATTERN), Const(0, 48));
cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID(Y))); cell->setPort(ID(OVERFLOW), st.overflow->getPort(ID::Y));
} }
else log_abort(); else log_abort();
@ -361,29 +361,29 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
if (st.clock != SigBit()) if (st.clock != SigBit())
{ {
cell->setPort(ID(CLK), st.clock); cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
SigSpec D = ff->getPort(ID(D)); SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty()) if (!A.empty())
A.replace(Q, D); A.replace(Q, D);
if (rstmux) { if (rstmux) {
SigSpec Y = rstmux->getPort(ID(Y)); SigSpec Y = rstmux->getPort(ID::Y);
SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty()) if (!A.empty())
A.replace(Y, AB); A.replace(Y, AB);
if (rstport != IdString()) { if (rstport != IdString()) {
SigSpec S = rstmux->getPort(ID(S)); SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
} }
} }
else if (rstport != IdString()) else if (rstport != IdString())
cell->setPort(rstport, State::S0); cell->setPort(rstport, State::S0);
if (cemux) { if (cemux) {
SigSpec Y = cemux->getPort(ID(Y)); SigSpec Y = cemux->getPort(ID::Y);
SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
SigSpec S = cemux->getPort(ID(S)); SigSpec S = cemux->getPort(ID::S);
if (!A.empty()) if (!A.empty())
A.replace(Y, BA); A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@ -392,7 +392,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setPort(ceport, State::S1); cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) { for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find(ID(init)); auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end()) if (it == c.wire->attributes.end())
continue; continue;
for (int i = c.offset; i < c.offset+c.width; i++) { for (int i = c.offset; i < c.offset+c.width; i++) {
@ -403,7 +403,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
}; };
if (st.ffA2) { if (st.ffA2) {
SigSpec A = cell->getPort(ID(A)); SigSpec A = cell->getPort(ID::A);
f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA)); f(A, st.ffA2, st.ffA2cemux, st.ffA2cepol, ID(CEA2), st.ffA2rstmux, st.ffArstpol, ID(RSTA));
if (st.ffA1) { if (st.ffA1) {
f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString()); f(A, st.ffA1, st.ffA1cemux, st.ffA1cepol, ID(CEA1), st.ffA1rstmux, st.ffArstpol, IdString());
@ -415,10 +415,10 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(ACASCREG), 1); cell->setParam(ID(ACASCREG), 1);
} }
pm.add_siguser(A, cell); pm.add_siguser(A, cell);
cell->setPort(ID(A), A); cell->setPort(ID::A, A);
} }
if (st.ffB2) { if (st.ffB2) {
SigSpec B = cell->getPort(ID(B)); SigSpec B = cell->getPort(ID::B);
f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB)); f(B, st.ffB2, st.ffB2cemux, st.ffB2cepol, ID(CEB2), st.ffB2rstmux, st.ffBrstpol, ID(RSTB));
if (st.ffB1) { if (st.ffB1) {
f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString()); f(B, st.ffB1, st.ffB1cemux, st.ffB1cepol, ID(CEB1), st.ffB1rstmux, st.ffBrstpol, IdString());
@ -430,25 +430,25 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
cell->setParam(ID(BCASCREG), 1); cell->setParam(ID(BCASCREG), 1);
} }
pm.add_siguser(B, cell); pm.add_siguser(B, cell);
cell->setPort(ID(B), B); cell->setPort(ID::B, B);
} }
if (st.ffD) { if (st.ffD) {
SigSpec D = cell->getPort(ID(D)); SigSpec D = cell->getPort(ID::D);
f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD)); f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
pm.add_siguser(D, cell); pm.add_siguser(D, cell);
cell->setPort(ID(D), D); cell->setPort(ID::D, D);
cell->setParam(ID(DREG), 1); cell->setParam(ID(DREG), 1);
} }
if (st.ffM) { if (st.ffM) {
SigSpec M; // unused SigSpec M; // unused
f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM)); f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1); cell->setParam(ID(MREG), State::S1);
} }
if (st.ffP) { if (st.ffP) {
SigSpec P; // unused SigSpec P; // unused
f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP)); f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1); cell->setParam(ID(PREG), State::S1);
} }
@ -483,7 +483,7 @@ void xilinx_dsp_pack(xilinx_dsp_pm &pm)
SigSpec P = st.sigP; SigSpec P = st.sigP;
if (GetSize(P) < 48) if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
cell->setPort(ID(P), P); cell->setPort(ID::P, P);
pm.blacklist(cell); pm.blacklist(cell);
} }
@ -511,12 +511,12 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.preAdd) { if (st.preAdd) {
log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type)); log(" preadder %s (%s)\n", log_id(st.preAdd), log_id(st.preAdd->type));
bool D_SIGNED = st.preAdd->getParam(ID(A_SIGNED)).as_bool(); bool D_SIGNED = st.preAdd->getParam(ID::A_SIGNED).as_bool();
bool B_SIGNED = st.preAdd->getParam(ID(B_SIGNED)).as_bool(); bool B_SIGNED = st.preAdd->getParam(ID::B_SIGNED).as_bool();
st.sigB.extend_u0(18, B_SIGNED); st.sigB.extend_u0(18, B_SIGNED);
st.sigD.extend_u0(18, D_SIGNED); st.sigD.extend_u0(18, D_SIGNED);
cell->setPort(ID(B), st.sigB); cell->setPort(ID::B, st.sigB);
cell->setPort(ID(D), st.sigD); cell->setPort(ID::D, st.sigD);
opmode[4] = State::S1; opmode[4] = State::S1;
if (st.preAdd->type == ID($add)) if (st.preAdd->type == ID($add))
opmode[6] = State::S0; opmode[6] = State::S0;
@ -532,7 +532,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.postAddMux) { if (st.postAddMux) {
log_assert(st.ffP); log_assert(st.ffP);
opmode[2] = st.postAddMux->getPort(ID(S)); opmode[2] = st.postAddMux->getPort(ID::S);
pm.autoremove(st.postAddMux); pm.autoremove(st.postAddMux);
} }
else if (st.ffP && st.sigC == st.sigP) else if (st.ffP && st.sigC == st.sigP)
@ -542,11 +542,11 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
opmode[3] = State::S1; opmode[3] = State::S1;
if (opmode[2] != State::S0) { if (opmode[2] != State::S0) {
if (st.postAddMuxAB == ID(A)) if (st.postAddMuxAB == ID::A)
st.sigC.extend_u0(48, st.postAdd->getParam(ID(B_SIGNED)).as_bool()); st.sigC.extend_u0(48, st.postAdd->getParam(ID::B_SIGNED).as_bool());
else else
st.sigC.extend_u0(48, st.postAdd->getParam(ID(A_SIGNED)).as_bool()); st.sigC.extend_u0(48, st.postAdd->getParam(ID::A_SIGNED).as_bool());
cell->setPort(ID(C), st.sigC); cell->setPort(ID::C, st.sigC);
} }
pm.autoremove(st.postAdd); pm.autoremove(st.postAdd);
@ -554,29 +554,29 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
if (st.clock != SigBit()) if (st.clock != SigBit())
{ {
cell->setPort(ID(CLK), st.clock); cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
SigSpec D = ff->getPort(ID(D)); SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty()) if (!A.empty())
A.replace(Q, D); A.replace(Q, D);
if (rstmux) { if (rstmux) {
SigSpec Y = rstmux->getPort(ID(Y)); SigSpec Y = rstmux->getPort(ID::Y);
SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty()) if (!A.empty())
A.replace(Y, AB); A.replace(Y, AB);
if (rstport != IdString()) { if (rstport != IdString()) {
SigSpec S = rstmux->getPort(ID(S)); SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
} }
} }
else if (rstport != IdString()) else if (rstport != IdString())
cell->setPort(rstport, State::S0); cell->setPort(rstport, State::S0);
if (cemux) { if (cemux) {
SigSpec Y = cemux->getPort(ID(Y)); SigSpec Y = cemux->getPort(ID::Y);
SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
SigSpec S = cemux->getPort(ID(S)); SigSpec S = cemux->getPort(ID::S);
if (!A.empty()) if (!A.empty())
A.replace(Y, BA); A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@ -585,7 +585,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setPort(ceport, State::S1); cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) { for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find(ID(init)); auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end()) if (it == c.wire->attributes.end())
continue; continue;
for (int i = c.offset; i < c.offset+c.width; i++) { for (int i = c.offset; i < c.offset+c.width; i++) {
@ -596,7 +596,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
}; };
if (st.ffA0 || st.ffA1) { if (st.ffA0 || st.ffA1) {
SigSpec A = cell->getPort(ID(A)); SigSpec A = cell->getPort(ID::A);
if (st.ffA1) { if (st.ffA1) {
f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA)); f(A, st.ffA1, st.ffA1cemux, st.ffAcepol, ID(CEA), st.ffA1rstmux, st.ffArstpol, ID(RSTA));
cell->setParam(ID(A1REG), 1); cell->setParam(ID(A1REG), 1);
@ -606,10 +606,10 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setParam(ID(A0REG), 1); cell->setParam(ID(A0REG), 1);
} }
pm.add_siguser(A, cell); pm.add_siguser(A, cell);
cell->setPort(ID(A), A); cell->setPort(ID::A, A);
} }
if (st.ffB0 || st.ffB1) { if (st.ffB0 || st.ffB1) {
SigSpec B = cell->getPort(ID(B)); SigSpec B = cell->getPort(ID::B);
if (st.ffB1) { if (st.ffB1) {
f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB)); f(B, st.ffB1, st.ffB1cemux, st.ffBcepol, ID(CEB), st.ffB1rstmux, st.ffBrstpol, ID(RSTB));
cell->setParam(ID(B1REG), 1); cell->setParam(ID(B1REG), 1);
@ -619,25 +619,25 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
cell->setParam(ID(B0REG), 1); cell->setParam(ID(B0REG), 1);
} }
pm.add_siguser(B, cell); pm.add_siguser(B, cell);
cell->setPort(ID(B), B); cell->setPort(ID::B, B);
} }
if (st.ffD) { if (st.ffD) {
SigSpec D = cell->getPort(ID(D)); SigSpec D = cell->getPort(ID::D);
f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD)); f(D, st.ffD, st.ffDcemux, st.ffDcepol, ID(CED), st.ffDrstmux, st.ffDrstpol, ID(RSTD));
pm.add_siguser(D, cell); pm.add_siguser(D, cell);
cell->setPort(ID(D), D); cell->setPort(ID::D, D);
cell->setParam(ID(DREG), 1); cell->setParam(ID(DREG), 1);
} }
if (st.ffM) { if (st.ffM) {
SigSpec M; // unused SigSpec M; // unused
f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM)); f(M, st.ffM, st.ffMcemux, st.ffMcepol, ID(CEM), st.ffMrstmux, st.ffMrstpol, ID(RSTM));
st.ffM->connections_.at(ID(Q)).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM))); st.ffM->connections_.at(ID::Q).replace(st.sigM, pm.module->addWire(NEW_ID, GetSize(st.sigM)));
cell->setParam(ID(MREG), State::S1); cell->setParam(ID(MREG), State::S1);
} }
if (st.ffP) { if (st.ffP) {
SigSpec P; // unused SigSpec P; // unused
f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP)); f(P, st.ffP, st.ffPcemux, st.ffPcepol, ID(CEP), st.ffPrstmux, st.ffPrstpol, ID(RSTP));
st.ffP->connections_.at(ID(Q)).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP))); st.ffP->connections_.at(ID::Q).replace(st.sigP, pm.module->addWire(NEW_ID, GetSize(st.sigP)));
cell->setParam(ID(PREG), State::S1); cell->setParam(ID(PREG), State::S1);
} }
@ -667,7 +667,7 @@ void xilinx_dsp48a_pack(xilinx_dsp48a_pm &pm)
SigSpec P = st.sigP; SigSpec P = st.sigP;
if (GetSize(P) < 48) if (GetSize(P) < 48)
P.append(pm.module->addWire(NEW_ID, 48-GetSize(P))); P.append(pm.module->addWire(NEW_ID, 48-GetSize(P)));
cell->setPort(ID(P), P); cell->setPort(ID::P, P);
pm.blacklist(cell); pm.blacklist(cell);
} }
@ -683,29 +683,29 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
if (st.clock != SigBit()) if (st.clock != SigBit())
{ {
cell->setPort(ID(CLK), st.clock); cell->setPort(ID::CLK, st.clock);
auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) { auto f = [&pm,cell](SigSpec &A, Cell* ff, Cell* cemux, bool cepol, IdString ceport, Cell* rstmux, bool rstpol, IdString rstport) {
SigSpec D = ff->getPort(ID(D)); SigSpec D = ff->getPort(ID::D);
SigSpec Q = pm.sigmap(ff->getPort(ID(Q))); SigSpec Q = pm.sigmap(ff->getPort(ID::Q));
if (!A.empty()) if (!A.empty())
A.replace(Q, D); A.replace(Q, D);
if (rstmux) { if (rstmux) {
SigSpec Y = rstmux->getPort(ID(Y)); SigSpec Y = rstmux->getPort(ID::Y);
SigSpec AB = rstmux->getPort(rstpol ? ID(A) : ID(B)); SigSpec AB = rstmux->getPort(rstpol ? ID::A : ID::B);
if (!A.empty()) if (!A.empty())
A.replace(Y, AB); A.replace(Y, AB);
if (rstport != IdString()) { if (rstport != IdString()) {
SigSpec S = rstmux->getPort(ID(S)); SigSpec S = rstmux->getPort(ID::S);
cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(rstport, rstpol ? S : pm.module->Not(NEW_ID, S));
} }
} }
else if (rstport != IdString()) else if (rstport != IdString())
cell->setPort(rstport, State::S0); cell->setPort(rstport, State::S0);
if (cemux) { if (cemux) {
SigSpec Y = cemux->getPort(ID(Y)); SigSpec Y = cemux->getPort(ID::Y);
SigSpec BA = cemux->getPort(cepol ? ID(B) : ID(A)); SigSpec BA = cemux->getPort(cepol ? ID::B : ID::A);
SigSpec S = cemux->getPort(ID(S)); SigSpec S = cemux->getPort(ID::S);
if (!A.empty()) if (!A.empty())
A.replace(Y, BA); A.replace(Y, BA);
cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S)); cell->setPort(ceport, cepol ? S : pm.module->Not(NEW_ID, S));
@ -714,7 +714,7 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
cell->setPort(ceport, State::S1); cell->setPort(ceport, State::S1);
for (auto c : Q.chunks()) { for (auto c : Q.chunks()) {
auto it = c.wire->attributes.find(ID(init)); auto it = c.wire->attributes.find(ID::init);
if (it == c.wire->attributes.end()) if (it == c.wire->attributes.end())
continue; continue;
for (int i = c.offset; i < c.offset+c.width; i++) { for (int i = c.offset; i < c.offset+c.width; i++) {
@ -725,10 +725,10 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm)
}; };
if (st.ffC) { if (st.ffC) {
SigSpec C = cell->getPort(ID(C)); SigSpec C = cell->getPort(ID::C);
f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC)); f(C, st.ffC, st.ffCcemux, st.ffCcepol, ID(CEC), st.ffCrstmux, st.ffCrstpol, ID(RSTC));
pm.add_siguser(C, cell); pm.add_siguser(C, cell);
cell->setPort(ID(C), C); cell->setPort(ID::C, C);
cell->setParam(ID(CREG), 1); cell->setParam(ID(CREG), 1);
} }

56
passes/pmgen/xilinx_srl.cc
View file

@ -36,9 +36,9 @@ void run_fixed(xilinx_srl_pm &pm)
for (auto cell : ud.longest_chain) { for (auto cell : ud.longest_chain) {
log_debug(" %s\n", log_id(cell)); log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) { if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) {
SigBit Q = cell->getPort(ID(Q)); SigBit Q = cell->getPort(ID::Q);
log_assert(Q.wire); log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID(init)); auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) { if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset]; auto &i = it->second[Q.offset];
initval.append(i); initval.append(i);
@ -48,7 +48,7 @@ void run_fixed(xilinx_srl_pm &pm)
initval.append(State::Sx); initval.append(State::Sx);
} }
else if (cell->type.in(ID(FDRE), ID(FDRE_1))) { else if (cell->type.in(ID(FDRE), ID(FDRE_1))) {
if (cell->parameters.at(ID(INIT), State::S0).as_bool()) if (cell->parameters.at(ID::INIT, State::S0).as_bool())
initval.append(State::S1); initval.append(State::S1);
else else
initval.append(State::S0); initval.append(State::S0);
@ -64,11 +64,11 @@ void run_fixed(xilinx_srl_pm &pm)
pm.module->swap_names(c, first_cell); pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) { if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID(FDRE), ID(FDRE_1))) {
c->setParam(ID(DEPTH), GetSize(ud.longest_chain)); c->setParam(ID::DEPTH, GetSize(ud.longest_chain));
c->setParam(ID(INIT), initval.as_const()); c->setParam(ID::INIT, initval.as_const());
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setParam(ID(CLKPOL), 1); c->setParam(ID(CLKPOL), 1);
else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1))) else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID(FDRE_1)))
c->setParam(ID(CLKPOL), 0); c->setParam(ID(CLKPOL), 0);
else if (first_cell->type.in(ID(FDRE))) { else if (first_cell->type.in(ID(FDRE))) {
if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool()) if (!first_cell->parameters.at(ID(IS_C_INVERTED), State::S0).as_bool())
@ -85,16 +85,16 @@ void run_fixed(xilinx_srl_pm &pm)
else else
c->setParam(ID(ENPOL), 2); c->setParam(ID(ENPOL), 2);
c->setPort(ID(C), first_cell->getPort(ID(C))); c->setPort(ID::C, first_cell->getPort(ID::C));
c->setPort(ID(D), first_cell->getPort(ID(D))); c->setPort(ID::D, first_cell->getPort(ID::D));
c->setPort(ID(Q), last_cell->getPort(ID(Q))); c->setPort(ID::Q, last_cell->getPort(ID::Q));
c->setPort(ID(L), GetSize(ud.longest_chain)-1); c->setPort(ID::L, GetSize(ud.longest_chain)-1);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
c->setPort(ID(E), State::S1); c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID(E), first_cell->getPort(ID(E))); c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID(FDRE), ID(FDRE_1))) else if (first_cell->type.in(ID(FDRE), ID(FDRE_1)))
c->setPort(ID(E), first_cell->getPort(ID(CE))); c->setPort(ID::E, first_cell->getPort(ID(CE)));
else else
log_abort(); log_abort();
} }
@ -117,9 +117,9 @@ void run_variable(xilinx_srl_pm &pm)
auto slice = i.second; auto slice = i.second;
log_debug(" %s\n", log_id(cell)); log_debug(" %s\n", log_id(cell));
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
SigBit Q = cell->getPort(ID(Q))[slice]; SigBit Q = cell->getPort(ID::Q)[slice];
log_assert(Q.wire); log_assert(Q.wire);
auto it = Q.wire->attributes.find(ID(init)); auto it = Q.wire->attributes.find(ID::init);
if (it != Q.wire->attributes.end()) { if (it != Q.wire->attributes.end()) {
auto &i = it->second[Q.offset]; auto &i = it->second[Q.offset];
initval.append(i); initval.append(i);
@ -140,15 +140,15 @@ void run_variable(xilinx_srl_pm &pm)
pm.module->swap_names(c, first_cell); pm.module->swap_names(c, first_cell);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) { if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_), ID($dff), ID($dffe))) {
c->setParam(ID(DEPTH), GetSize(ud.chain)); c->setParam(ID::DEPTH, GetSize(ud.chain));
c->setParam(ID(INIT), initval.as_const()); c->setParam(ID::INIT, initval.as_const());
Const clkpol, enpol; Const clkpol, enpol;
if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_))) if (first_cell->type.in(ID($_DFF_P_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
clkpol = 1; clkpol = 1;
else if (first_cell->type.in(ID($_DFF_N_), ID($DFFE_NN_), ID($_DFFE_NP_))) else if (first_cell->type.in(ID($_DFF_N_), ID($_DFFE_NN_), ID($_DFFE_NP_)))
clkpol = 0; clkpol = 0;
else if (first_cell->type.in(ID($dff), ID($dffe))) else if (first_cell->type.in(ID($dff), ID($dffe)))
clkpol = first_cell->getParam(ID(CLK_POLARITY)); clkpol = first_cell->getParam(ID::CLK_POLARITY);
else else
log_abort(); log_abort();
if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_))) if (first_cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
@ -156,27 +156,27 @@ void run_variable(xilinx_srl_pm &pm)
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_))) else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_PN_)))
enpol = 0; enpol = 0;
else if (first_cell->type.in(ID($dffe))) else if (first_cell->type.in(ID($dffe)))
enpol = first_cell->getParam(ID(EN_POLARITY)); enpol = first_cell->getParam(ID::EN_POLARITY);
else else
enpol = 2; enpol = 2;
c->setParam(ID(CLKPOL), clkpol); c->setParam(ID(CLKPOL), clkpol);
c->setParam(ID(ENPOL), enpol); c->setParam(ID(ENPOL), enpol);
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID(C), first_cell->getPort(ID(C))); c->setPort(ID::C, first_cell->getPort(ID::C));
else if (first_cell->type.in(ID($dff), ID($dffe))) else if (first_cell->type.in(ID($dff), ID($dffe)))
c->setPort(ID(C), first_cell->getPort(ID(CLK))); c->setPort(ID::C, first_cell->getPort(ID::CLK));
else else
log_abort(); log_abort();
c->setPort(ID(D), first_cell->getPort(ID(D))[first_slice]); c->setPort(ID::D, first_cell->getPort(ID::D)[first_slice]);
c->setPort(ID(Q), st.shiftx->getPort(ID(Y))); c->setPort(ID::Q, st.shiftx->getPort(ID::Y));
c->setPort(ID(L), st.shiftx->getPort(ID(B))); c->setPort(ID::L, st.shiftx->getPort(ID::B));
if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff))) if (first_cell->type.in(ID($_DFF_N_), ID($_DFF_P_), ID($dff)))
c->setPort(ID(E), State::S1); c->setPort(ID::E, State::S1);
else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_))) else if (first_cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
c->setPort(ID(E), first_cell->getPort(ID(E))); c->setPort(ID::E, first_cell->getPort(ID::E));
else if (first_cell->type.in(ID($dffe))) else if (first_cell->type.in(ID($dffe)))
c->setPort(ID(E), first_cell->getPort(ID(EN))); c->setPort(ID::E, first_cell->getPort(ID::EN));
else else
log_abort(); log_abort();
} }

18
passes/proc/proc_arst.cc
View file

@ -39,23 +39,23 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells()) for (auto cell : mod->cells())
{ {
if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal) if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity); return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal) if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity); return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) { if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity; polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity); return check_signal(mod, cell->getPort(ID::A), ref, polarity);
} }
if (cell->type == "$not" && cell->getPort(ID::Y) == signal) { if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity; polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity); return check_signal(mod, cell->getPort(ID::A), ref, polarity);
} }
if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) { if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) { if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool()) if (!cell->getPort(ID::A).as_bool())
polarity = !polarity; polarity = !polarity;
@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
} }
} }
if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) { if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) { if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool()) if (cell->getPort(ID::A).as_bool())
polarity = !polarity; polarity = !polarity;
@ -261,8 +261,8 @@ struct ProcArstPass : public Pass {
for (auto &act : sync->actions) { for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val; RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks()) for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count("\\init")) { if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
RTLIL::SigSpec value = chunk.wire->attributes.at("\\init"); RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false); value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk); arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width)); arst_val.append(value.extract(chunk.offset, chunk.width));
@ -285,7 +285,7 @@ struct ProcArstPass : public Pass {
} }
for (auto wire : delete_initattr_wires) for (auto wire : delete_initattr_wires)
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
} }
} ProcArstPass; } ProcArstPass;

126
passes/proc/proc_dff.cc
View file

@ -75,49 +75,49 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
log_abort(); log_abort();
if (sync_low_signals.size() > 1) { if (sync_low_signals.size() > 1) {
RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_low_signals); cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID)); cell->setPort(ID::Y, sync_low_signals = mod->addWire(NEW_ID));
} }
if (sync_low_signals.size() > 0) { if (sync_low_signals.size() > 0) {
RTLIL::Cell *cell = mod->addCell(NEW_ID, "$not"); RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($not));
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_low_signals.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_low_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_low_signals); cell->setPort(ID::A, sync_low_signals);
cell->setPort(ID::Y, mod->addWire(NEW_ID)); cell->setPort(ID::Y, mod->addWire(NEW_ID));
sync_high_signals.append(cell->getPort(ID::Y)); sync_high_signals.append(cell->getPort(ID::Y));
} }
if (sync_high_signals.size() > 1) { if (sync_high_signals.size() > 1) {
RTLIL::Cell *cell = mod->addCell(NEW_ID, "$reduce_or"); RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($reduce_or));
cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(sync_high_signals.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(sync_high_signals.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, sync_high_signals); cell->setPort(ID::A, sync_high_signals);
cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID)); cell->setPort(ID::Y, sync_high_signals = mod->addWire(NEW_ID));
} }
RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, "$not"); RTLIL::Cell *inv_cell = mod->addCell(NEW_ID, ID($not));
inv_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
inv_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_d.size());
inv_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_d.size()); inv_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_d.size());
inv_cell->setPort(ID::A, sync_value); inv_cell->setPort(ID::A, sync_value);
inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size())); inv_cell->setPort(ID::Y, sync_value_inv = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, "$mux"); RTLIL::Cell *mux_set_cell = mod->addCell(NEW_ID, ID($mux));
mux_set_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_set_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
mux_set_cell->setPort(ID::A, sig_sr_set); mux_set_cell->setPort(ID::A, sig_sr_set);
mux_set_cell->setPort(ID::B, sync_value); mux_set_cell->setPort(ID::B, sync_value);
mux_set_cell->setPort(ID::S, sync_high_signals); mux_set_cell->setPort(ID::S, sync_high_signals);
mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size())); mux_set_cell->setPort(ID::Y, sig_sr_set = mod->addWire(NEW_ID, sig_d.size()));
RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, "$mux"); RTLIL::Cell *mux_clr_cell = mod->addCell(NEW_ID, ID($mux));
mux_clr_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); mux_clr_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
mux_clr_cell->setPort(ID::A, sig_sr_clr); mux_clr_cell->setPort(ID::A, sig_sr_clr);
mux_clr_cell->setPort(ID::B, sync_value_inv); mux_clr_cell->setPort(ID::B, sync_value_inv);
mux_clr_cell->setPort(ID::S, sync_high_signals); mux_clr_cell->setPort(ID::S, sync_high_signals);
@ -127,17 +127,17 @@ void gen_dffsr_complex(RTLIL::Module *mod, RTLIL::SigSpec sig_d, RTLIL::SigSpec
std::stringstream sstr; std::stringstream sstr;
sstr << "$procdff$" << (autoidx++); sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes; cell->attributes = proc->attributes;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_d.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(sig_d.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
cell->setPort("\\D", sig_d); cell->setPort(ID::D, sig_d);
cell->setPort("\\Q", sig_q); cell->setPort(ID::Q, sig_q);
cell->setPort("\\CLK", clk); cell->setPort(ID::CLK, clk);
cell->setPort("\\SET", sig_sr_set); cell->setPort(ID::SET, sig_sr_set);
cell->setPort("\\CLR", sig_sr_clr); cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n", log(" created %s cell `%s' with %s edge clock and multiple level-sensitive resets.\n",
cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@ -153,38 +153,38 @@ void gen_dffsr(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_set = mod->addWire(NEW_ID, sig_in.size());
RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size()); RTLIL::SigSpec sig_sr_clr = mod->addWire(NEW_ID, sig_in.size());
RTLIL::Cell *inv_set = mod->addCell(NEW_ID, "$not"); RTLIL::Cell *inv_set = mod->addCell(NEW_ID, ID($not));
inv_set->parameters["\\A_SIGNED"] = RTLIL::Const(0); inv_set->parameters[ID::A_SIGNED] = RTLIL::Const(0);
inv_set->parameters["\\A_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters[ID::A_WIDTH] = RTLIL::Const(sig_in.size());
inv_set->parameters["\\Y_WIDTH"] = RTLIL::Const(sig_in.size()); inv_set->parameters[ID::Y_WIDTH] = RTLIL::Const(sig_in.size());
inv_set->setPort(ID::A, sig_set); inv_set->setPort(ID::A, sig_set);
inv_set->setPort(ID::Y, sig_set_inv); inv_set->setPort(ID::Y, sig_set_inv);
RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, "$mux"); RTLIL::Cell *mux_sr_set = mod->addCell(NEW_ID, ID($mux));
mux_sr_set->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_set->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); mux_sr_set->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set); mux_sr_set->setPort(set_polarity ? ID::B : ID::A, sig_set);
mux_sr_set->setPort(ID::Y, sig_sr_set); mux_sr_set->setPort(ID::Y, sig_sr_set);
mux_sr_set->setPort(ID::S, set); mux_sr_set->setPort(ID::S, set);
RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, "$mux"); RTLIL::Cell *mux_sr_clr = mod->addCell(NEW_ID, ID($mux));
mux_sr_clr->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); mux_sr_clr->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size())); mux_sr_clr->setPort(set_polarity ? ID::A : ID::B, RTLIL::Const(0, sig_in.size()));
mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv); mux_sr_clr->setPort(set_polarity ? ID::B : ID::A, sig_set_inv);
mux_sr_clr->setPort(ID::Y, sig_sr_clr); mux_sr_clr->setPort(ID::Y, sig_sr_clr);
mux_sr_clr->setPort(ID::S, set); mux_sr_clr->setPort(ID::S, set);
RTLIL::Cell *cell = mod->addCell(sstr.str(), "$dffsr"); RTLIL::Cell *cell = mod->addCell(sstr.str(), ID($dffsr));
cell->attributes = proc->attributes; cell->attributes = proc->attributes;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
cell->parameters["\\SET_POLARITY"] = RTLIL::Const(true, 1); cell->parameters[ID::SET_POLARITY] = RTLIL::Const(true, 1);
cell->parameters["\\CLR_POLARITY"] = RTLIL::Const(true, 1); cell->parameters[ID::CLR_POLARITY] = RTLIL::Const(true, 1);
cell->setPort("\\D", sig_in); cell->setPort(ID::D, sig_in);
cell->setPort("\\Q", sig_out); cell->setPort(ID::Q, sig_out);
cell->setPort("\\CLK", clk); cell->setPort(ID::CLK, clk);
cell->setPort("\\SET", sig_sr_set); cell->setPort(ID::SET, sig_sr_set);
cell->setPort("\\CLR", sig_sr_clr); cell->setPort(ID::CLR, sig_sr_clr);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(), log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type.c_str(), cell->name.c_str(),
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative"); clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@ -196,24 +196,24 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
std::stringstream sstr; std::stringstream sstr;
sstr << "$procdff$" << (autoidx++); sstr << "$procdff$" << (autoidx++);
RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? "$ff" : arst ? "$adff" : "$dff"); RTLIL::Cell *cell = mod->addCell(sstr.str(), clk.empty() ? ID($ff) : arst ? ID($adff) : ID($dff));
cell->attributes = proc->attributes; cell->attributes = proc->attributes;
cell->parameters["\\WIDTH"] = RTLIL::Const(sig_in.size()); cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
if (arst) { if (arst) {
cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity, 1); cell->parameters[ID::ARST_POLARITY] = RTLIL::Const(arst_polarity, 1);
cell->parameters["\\ARST_VALUE"] = val_rst; cell->parameters[ID::ARST_VALUE] = val_rst;
} }
if (!clk.empty()) { if (!clk.empty()) {
cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(clk_polarity, 1); cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
} }
cell->setPort("\\D", sig_in); cell->setPort(ID::D, sig_in);
cell->setPort("\\Q", sig_out); cell->setPort(ID::Q, sig_out);
if (arst) if (arst)
cell->setPort("\\ARST", *arst); cell->setPort(ID::ARST, *arst);
if (!clk.empty()) if (!clk.empty())
cell->setPort("\\CLK", clk); cell->setPort(ID::CLK, clk);
if (!clk.empty()) if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative"); log(" created %s cell `%s' with %s edge clock", cell->type.c_str(), cell->name.c_str(), clk_polarity ? "positive" : "negative");
@ -303,12 +303,12 @@ void proc_dff(RTLIL::Module *mod, RTLIL::Process *proc, ConstEval &ce)
} }
log_assert(inputs.size() == compare.size()); log_assert(inputs.size() == compare.size());
RTLIL::Cell *cell = mod->addCell(NEW_ID, "$ne"); RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($ne));
cell->parameters["\\A_SIGNED"] = RTLIL::Const(false, 1); cell->parameters[ID::A_SIGNED] = RTLIL::Const(false, 1);
cell->parameters["\\B_SIGNED"] = RTLIL::Const(false, 1); cell->parameters[ID::B_SIGNED] = RTLIL::Const(false, 1);
cell->parameters["\\A_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters[ID::A_WIDTH] = RTLIL::Const(inputs.size());
cell->parameters["\\B_WIDTH"] = RTLIL::Const(inputs.size()); cell->parameters[ID::B_WIDTH] = RTLIL::Const(inputs.size());
cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
cell->setPort(ID::A, inputs); cell->setPort(ID::A, inputs);
cell->setPort(ID::B, compare); cell->setPort(ID::B, compare);
cell->setPort(ID::Y, sync_level->signal); cell->setPort(ID::Y, sync_level->signal);

18
passes/proc/proc_dlatch.cc
View file

@ -42,7 +42,7 @@ struct proc_dlatch_db_t
{ {
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
auto sig_y = sigmap(cell->getPort(ID::Y)); auto sig_y = sigmap(cell->getPort(ID::Y));
for (int i = 0; i < GetSize(sig_y); i++) for (int i = 0; i < GetSize(sig_y); i++)
@ -281,11 +281,11 @@ struct proc_dlatch_db_t
cell->setPort(ID::A, sig_any_valid_b); cell->setPort(ID::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) { if (GetSize(sig_new_s) == 1) {
cell->type = "$mux"; cell->type = ID($mux);
cell->unsetParam("\\S_WIDTH"); cell->unsetParam(ID::S_WIDTH);
} else { } else {
cell->type = "$pmux"; cell->type = ID($pmux);
cell->setParam("\\S_WIDTH", GetSize(sig_new_s)); cell->setParam(ID::S_WIDTH, GetSize(sig_new_s));
} }
cell->setPort(ID::B, sig_new_b); cell->setPort(ID::B, sig_new_b);
@ -317,7 +317,7 @@ struct proc_dlatch_db_t
pool<Cell*> next_queue; pool<Cell*> next_queue;
for (auto cell : queue) { for (auto cell : queue) {
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
fixup_mux(cell); fixup_mux(cell);
for (auto bit : upstream_cell2net[cell]) for (auto bit : upstream_cell2net[cell])
for (auto cell : upstream_net2cell[bit]) for (auto cell : upstream_net2cell[bit])
@ -349,7 +349,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
continue; continue;
} }
if (proc->get_bool_attribute(ID(always_ff))) if (proc->get_bool_attribute(ID::always_ff))
log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n", log_error("Found non edge/level sensitive event in always_ff process `%s.%s'.\n",
db.module->name.c_str(), proc->name.c_str()); db.module->name.c_str(), proc->name.c_str());
@ -387,7 +387,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
int offset = 0; int offset = 0;
for (auto chunk : nolatches_bits.first.chunks()) { for (auto chunk : nolatches_bits.first.chunks()) {
SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width); SigSpec lhs = chunk, rhs = nolatches_bits.second.extract(offset, chunk.width);
if (proc->get_bool_attribute(ID(always_latch))) if (proc->get_bool_attribute(ID::always_latch))
log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n", log_error("No latch inferred for signal `%s.%s' from always_latch process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else else
@ -418,7 +418,7 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc)
cell->set_src_attribute(src); cell->set_src_attribute(src);
db.generated_dlatches.insert(cell); db.generated_dlatches.insert(cell);
if (proc->get_bool_attribute(ID(always_comb))) if (proc->get_bool_attribute(ID::always_comb))
log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n",
db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str());
else else

2
passes/proc/proc_init.cc
View file

@ -54,7 +54,7 @@ void proc_init(RTLIL::Module *mod, SigMap &sigmap, RTLIL::Process *proc)
log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig)); log_cmd_error("Non-const initialization value: %s = %s\n", log_signal(lhs_c), log_signal(valuesig));
Const value = valuesig.as_const(); Const value = valuesig.as_const();
Const &wireinit = lhs_c.wire->attributes["\\init"]; Const &wireinit = lhs_c.wire->attributes[ID::init];
while (GetSize(wireinit.bits) < lhs_c.wire->width) while (GetSize(wireinit.bits) < lhs_c.wire->width)
wireinit.bits.push_back(State::Sx); wireinit.bits.push_back(State::Sx);

28
passes/proc/proc_mux.cc
View file

@ -178,15 +178,15 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
else else
{ {
// create compare cell // create compare cell
RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? "$eqx" : "$eq"); RTLIL::Cell *eq_cell = mod->addCell(stringf("%s_CMP%d", sstr.str().c_str(), cmp_wire->width), ifxmode ? ID($eqx) : ID($eq));
apply_attrs(eq_cell, sw, cs); apply_attrs(eq_cell, sw, cs);
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(0); eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(0);
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig.size()); eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig.size());
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(comp.size()); eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
eq_cell->setPort(ID::A, sig); eq_cell->setPort(ID::A, sig);
eq_cell->setPort(ID::B, comp); eq_cell->setPort(ID::B, comp);
@ -204,12 +204,12 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
ctrl_wire = mod->addWire(sstr.str() + "_CTRL"); ctrl_wire = mod->addWire(sstr.str() + "_CTRL");
// reduce cmp vector to one logic signal // reduce cmp vector to one logic signal
RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", "$reduce_or"); RTLIL::Cell *any_cell = mod->addCell(sstr.str() + "_ANY", ID($reduce_or));
apply_attrs(any_cell, sw, cs); apply_attrs(any_cell, sw, cs);
any_cell->parameters["\\A_SIGNED"] = RTLIL::Const(0); any_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
any_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cmp_wire->width); any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
any_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1); any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
any_cell->setPort(ID::A, cmp_wire); any_cell->setPort(ID::A, cmp_wire);
any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire)); any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
@ -239,10 +239,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size()); RTLIL::Wire *result_wire = mod->addWire(sstr.str() + "_Y", when_signal.size());
// create the multiplexer itself // create the multiplexer itself
RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), "$mux"); RTLIL::Cell *mux_cell = mod->addCell(sstr.str(), ID($mux));
apply_attrs(mux_cell, sw, cs); apply_attrs(mux_cell, sw, cs);
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(when_signal.size()); mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
mux_cell->setPort(ID::A, else_signal); mux_cell->setPort(ID::A, else_signal);
mux_cell->setPort(ID::B, when_signal); mux_cell->setPort(ID::B, when_signal);
mux_cell->setPort(ID::S, ctrl_sig); mux_cell->setPort(ID::S, ctrl_sig);
@ -262,7 +262,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode); RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1); log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = "$pmux"; last_mux_cell->type = ID($pmux);
RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S); RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
new_s.append(ctrl_sig); new_s.append(ctrl_sig);
@ -272,7 +272,7 @@ void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::ve
new_b.append(when_signal); new_b.append(when_signal);
last_mux_cell->setPort(ID::B, new_b); last_mux_cell->setPort(ID::B, new_b);
last_mux_cell->parameters["\\S_WIDTH"] = last_mux_cell->getPort(ID::S).size(); last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
} }
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw) const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)

10
passes/sat/assertpmux.cc
View file

@ -52,10 +52,10 @@ struct AssertpmuxWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
if (cell->type.in("$mux", "$pmux")) if (cell->type.in(ID($mux), ID($pmux)))
{ {
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int numports = cell->type == "$mux" ? 2 : cell->getParam("\\S_WIDTH").as_int() + 1; int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
SigSpec sig_a = sigmap(cell->getPort(ID::A)); SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B)); SigSpec sig_b = sigmap(cell->getPort(ID::B));
@ -148,7 +148,7 @@ struct AssertpmuxWorker
{ {
log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux)); log("Adding assert for $pmux cell %s.%s.\n", log_id(module), log_id(pmux));
int swidth = pmux->getParam("\\S_WIDTH").as_int(); int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1); int cntbits = ceil_log2(swidth+1);
SigSpec sel = pmux->getPort(ID::S); SigSpec sel = pmux->getPort(ID::S);
@ -227,7 +227,7 @@ struct AssertpmuxPass : public Pass {
vector<Cell*> pmux_cells; vector<Cell*> pmux_cells;
for (auto cell : module->selected_cells()) for (auto cell : module->selected_cells())
if (cell->type == "$pmux") if (cell->type == ID($pmux))
pmux_cells.push_back(cell); pmux_cells.push_back(cell);
for (auto cell : pmux_cells) for (auto cell : pmux_cells)

98
passes/sat/async2sync.cc
View file

@ -66,9 +66,9 @@ struct Async2syncPass : public Pass {
pool<SigBit> del_initbits; pool<SigBit> del_initbits;
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init") > 0) if (wire->attributes.count(ID::init) > 0)
{ {
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@ -78,16 +78,16 @@ struct Async2syncPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells())) for (auto cell : vector<Cell*>(module->selected_cells()))
{ {
if (cell->type.in("$adff")) if (cell->type.in(ID($adff)))
{ {
// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool(); // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
bool arst_pol = cell->parameters["\\ARST_POLARITY"].as_bool(); bool arst_pol = cell->parameters[ID::ARST_POLARITY].as_bool();
Const arst_val = cell->parameters["\\ARST_VALUE"]; Const arst_val = cell->parameters[ID::ARST_VALUE];
// SigSpec sig_clk = cell->getPort("\\CLK"); // SigSpec sig_clk = cell->getPort(ID::CLK);
SigSpec sig_arst = cell->getPort("\\ARST"); SigSpec sig_arst = cell->getPort(ID::ARST);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): ARST=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
@ -102,7 +102,7 @@ struct Async2syncPass : public Pass {
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes["\\init"] = init_val; new_q->attributes[ID::init] = init_val;
if (arst_pol) { if (arst_pol) {
module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d); module->addMux(NEW_ID, sig_d, arst_val, sig_arst, new_d);
@ -112,26 +112,26 @@ struct Async2syncPass : public Pass {
module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q); module->addMux(NEW_ID, arst_val, new_q, sig_arst, sig_q);
} }
cell->setPort("\\D", new_d); cell->setPort(ID::D, new_d);
cell->setPort("\\Q", new_q); cell->setPort(ID::Q, new_q);
cell->unsetPort("\\ARST"); cell->unsetPort(ID::ARST);
cell->unsetParam("\\ARST_POLARITY"); cell->unsetParam(ID::ARST_POLARITY);
cell->unsetParam("\\ARST_VALUE"); cell->unsetParam(ID::ARST_VALUE);
cell->type = "$dff"; cell->type = ID($dff);
continue; continue;
} }
if (cell->type.in("$dffsr")) if (cell->type.in(ID($dffsr)))
{ {
// bool clk_pol = cell->parameters["\\CLK_POLARITY"].as_bool(); // bool clk_pol = cell->parameters[ID::CLK_POLARITY].as_bool();
bool set_pol = cell->parameters["\\SET_POLARITY"].as_bool(); bool set_pol = cell->parameters[ID::SET_POLARITY].as_bool();
bool clr_pol = cell->parameters["\\CLR_POLARITY"].as_bool(); bool clr_pol = cell->parameters[ID::CLR_POLARITY].as_bool();
// SigSpec sig_clk = cell->getPort("\\CLK"); // SigSpec sig_clk = cell->getPort(ID::CLK);
SigSpec sig_set = cell->getPort("\\SET"); SigSpec sig_set = cell->getPort(ID::SET);
SigSpec sig_clr = cell->getPort("\\CLR"); SigSpec sig_clr = cell->getPort(ID::CLR);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): SET=%s, CLR=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
@ -146,7 +146,7 @@ struct Async2syncPass : public Pass {
Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d)); Wire *new_d = module->addWire(NEW_ID, GetSize(sig_d));
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes["\\init"] = init_val; new_q->attributes[ID::init] = init_val;
if (!set_pol) if (!set_pol)
sig_set = module->Not(NEW_ID, sig_set); sig_set = module->Not(NEW_ID, sig_set);
@ -160,23 +160,23 @@ struct Async2syncPass : public Pass {
tmp = module->Or(NEW_ID, new_q, sig_set); tmp = module->Or(NEW_ID, new_q, sig_set);
module->addAnd(NEW_ID, tmp, sig_clr, sig_q); module->addAnd(NEW_ID, tmp, sig_clr, sig_q);
cell->setPort("\\D", new_d); cell->setPort(ID::D, new_d);
cell->setPort("\\Q", new_q); cell->setPort(ID::Q, new_q);
cell->unsetPort("\\SET"); cell->unsetPort(ID::SET);
cell->unsetPort("\\CLR"); cell->unsetPort(ID::CLR);
cell->unsetParam("\\SET_POLARITY"); cell->unsetParam(ID::SET_POLARITY);
cell->unsetParam("\\CLR_POLARITY"); cell->unsetParam(ID::CLR_POLARITY);
cell->type = "$dff"; cell->type = ID($dff);
continue; continue;
} }
if (cell->type.in("$dlatch")) if (cell->type.in(ID($dlatch)))
{ {
bool en_pol = cell->parameters["\\EN_POLARITY"].as_bool(); bool en_pol = cell->parameters[ID::EN_POLARITY].as_bool();
SigSpec sig_en = cell->getPort("\\EN"); SigSpec sig_en = cell->getPort(ID::EN);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
@ -190,7 +190,7 @@ struct Async2syncPass : public Pass {
} }
Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *new_q = module->addWire(NEW_ID, GetSize(sig_q));
new_q->attributes["\\init"] = init_val; new_q->attributes[ID::init] = init_val;
if (en_pol) { if (en_pol) {
module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q); module->addMux(NEW_ID, new_q, sig_d, sig_en, sig_q);
@ -198,20 +198,20 @@ struct Async2syncPass : public Pass {
module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q); module->addMux(NEW_ID, sig_d, new_q, sig_en, sig_q);
} }
cell->setPort("\\D", sig_q); cell->setPort(ID::D, sig_q);
cell->setPort("\\Q", new_q); cell->setPort(ID::Q, new_q);
cell->unsetPort("\\EN"); cell->unsetPort(ID::EN);
cell->unsetParam("\\EN_POLARITY"); cell->unsetParam(ID::EN_POLARITY);
cell->type = "$ff"; cell->type = ID($ff);
continue; continue;
} }
} }
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init") > 0) if (wire->attributes.count(ID::init) > 0)
{ {
bool delete_initattr = true; bool delete_initattr = true;
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@ -221,9 +221,9 @@ struct Async2syncPass : public Pass {
delete_initattr = false; delete_initattr = false;
if (delete_initattr) if (delete_initattr)
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
else else
wire->attributes.at("\\init") = initval; wire->attributes.at(ID::init) = initval;
} }
} }
} }

116
passes/sat/clk2fflogic.cc
View file

@ -60,9 +60,9 @@ struct Clk2fflogicPass : public Pass {
pool<SigBit> del_initbits; pool<SigBit> del_initbits;
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init") > 0) if (wire->attributes.count(ID::init) > 0)
{ {
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@ -72,26 +72,26 @@ struct Clk2fflogicPass : public Pass {
for (auto cell : vector<Cell*>(module->selected_cells())) for (auto cell : vector<Cell*>(module->selected_cells()))
{ {
if (cell->type.in("$mem")) if (cell->type.in(ID($mem)))
{ {
int abits = cell->getParam("\\ABITS").as_int(); int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam("\\WIDTH").as_int(); int width = cell->getParam(ID::WIDTH).as_int();
int rd_ports = cell->getParam("\\RD_PORTS").as_int(); int rd_ports = cell->getParam(ID::RD_PORTS).as_int();
int wr_ports = cell->getParam("\\WR_PORTS").as_int(); int wr_ports = cell->getParam(ID::WR_PORTS).as_int();
for (int i = 0; i < rd_ports; i++) { for (int i = 0; i < rd_ports; i++) {
if (cell->getParam("\\RD_CLK_ENABLE").extract(i).as_bool()) if (cell->getParam(ID::RD_CLK_ENABLE).extract(i).as_bool())
log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! " log_error("Read port %d of memory %s.%s is clocked. This is not supported by \"clk2fflogic\"! "
"Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module)); "Call \"memory\" with -nordff to avoid this error.\n", i, log_id(cell), log_id(module));
} }
Const wr_clk_en_param = cell->getParam("\\WR_CLK_ENABLE"); Const wr_clk_en_param = cell->getParam(ID::WR_CLK_ENABLE);
Const wr_clk_pol_param = cell->getParam("\\WR_CLK_POLARITY"); Const wr_clk_pol_param = cell->getParam(ID::WR_CLK_POLARITY);
SigSpec wr_clk_port = cell->getPort("\\WR_CLK"); SigSpec wr_clk_port = cell->getPort(ID::WR_CLK);
SigSpec wr_en_port = cell->getPort("\\WR_EN"); SigSpec wr_en_port = cell->getPort(ID::WR_EN);
SigSpec wr_addr_port = cell->getPort("\\WR_ADDR"); SigSpec wr_addr_port = cell->getPort(ID::WR_ADDR);
SigSpec wr_data_port = cell->getPort("\\WR_DATA"); SigSpec wr_data_port = cell->getPort(ID::WR_DATA);
for (int wport = 0; wport < wr_ports; wport++) for (int wport = 0; wport < wr_ports; wport++)
{ {
@ -111,7 +111,7 @@ struct Clk2fflogicPass : public Pass {
log_signal(addr), log_signal(data)); log_signal(addr), log_signal(data));
Wire *past_clk = module->addWire(NEW_ID); Wire *past_clk = module->addWire(NEW_ID);
past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0; past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
module->addFf(NEW_ID, clk, past_clk); module->addFf(NEW_ID, clk, past_clk);
SigSpec clock_edge_pattern; SigSpec clock_edge_pattern;
@ -144,22 +144,22 @@ struct Clk2fflogicPass : public Pass {
wr_clk_pol_param[wport] = State::S0; wr_clk_pol_param[wport] = State::S0;
} }
cell->setParam("\\WR_CLK_ENABLE", wr_clk_en_param); cell->setParam(ID::WR_CLK_ENABLE, wr_clk_en_param);
cell->setParam("\\WR_CLK_POLARITY", wr_clk_pol_param); cell->setParam(ID::WR_CLK_POLARITY, wr_clk_pol_param);
cell->setPort("\\WR_CLK", wr_clk_port); cell->setPort(ID::WR_CLK, wr_clk_port);
cell->setPort("\\WR_EN", wr_en_port); cell->setPort(ID::WR_EN, wr_en_port);
cell->setPort("\\WR_ADDR", wr_addr_port); cell->setPort(ID::WR_ADDR, wr_addr_port);
cell->setPort("\\WR_DATA", wr_data_port); cell->setPort(ID::WR_DATA, wr_data_port);
} }
if (cell->type.in("$dlatch", "$dlatchsr")) if (cell->type.in(ID($dlatch), ID($dlatchsr)))
{ {
bool enpol = cell->parameters["\\EN_POLARITY"].as_bool(); bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
SigSpec sig_en = cell->getPort("\\EN"); SigSpec sig_en = cell->getPort(ID::EN);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): EN=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
@ -168,7 +168,7 @@ struct Clk2fflogicPass : public Pass {
Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q)); Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
module->addFf(NEW_ID, sig_q, past_q); module->addFf(NEW_ID, sig_q, past_q);
if (cell->type == "$dlatch") if (cell->type == ID($dlatch))
{ {
if (enpol) if (enpol)
module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q); module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
@ -183,13 +183,13 @@ struct Clk2fflogicPass : public Pass {
else else
t = module->Mux(NEW_ID, sig_d, past_q, sig_en); t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
SigSpec s = cell->getPort("\\SET"); SigSpec s = cell->getPort(ID::SET);
if (!cell->parameters["\\SET_POLARITY"].as_bool()) if (!cell->parameters[ID::SET_POLARITY].as_bool())
s = module->Not(NEW_ID, s); s = module->Not(NEW_ID, s);
t = module->Or(NEW_ID, t, s); t = module->Or(NEW_ID, t, s);
SigSpec c = cell->getPort("\\CLR"); SigSpec c = cell->getPort(ID::CLR);
if (cell->parameters["\\CLR_POLARITY"].as_bool()) if (cell->parameters[ID::CLR_POLARITY].as_bool())
c = module->Not(NEW_ID, c); c = module->Not(NEW_ID, c);
module->addAnd(NEW_ID, t, c, sig_q); module->addAnd(NEW_ID, t, c, sig_q);
} }
@ -208,13 +208,13 @@ struct Clk2fflogicPass : public Pass {
} }
if (assign_initval) if (assign_initval)
past_q->attributes["\\init"] = initval; past_q->attributes[ID::init] = initval;
module->remove(cell); module->remove(cell);
continue; continue;
} }
bool word_dff = cell->type.in("$dff", "$adff", "$dffsr"); bool word_dff = cell->type.in(ID($dff), ID($adff), ID($dffsr));
if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_), if (word_dff || cell->type.in(ID($_DFF_N_), ID($_DFF_P_),
ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_),
@ -224,8 +224,8 @@ struct Clk2fflogicPass : public Pass {
bool clkpol; bool clkpol;
SigSpec clk; SigSpec clk;
if (word_dff) { if (word_dff) {
clkpol = cell->parameters["\\CLK_POLARITY"].as_bool(); clkpol = cell->parameters[ID::CLK_POLARITY].as_bool();
clk = cell->getPort("\\CLK"); clk = cell->getPort(ID::CLK);
} }
else { else {
if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_), if (cell->type.in(ID($_DFF_P_), ID($_DFF_N_),
@ -236,19 +236,19 @@ struct Clk2fflogicPass : public Pass {
ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_))) ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
clkpol = cell->type[8] == 'P'; clkpol = cell->type[8] == 'P';
else log_abort(); else log_abort();
clk = cell->getPort("\\C"); clk = cell->getPort(ID::C);
} }
Wire *past_clk = module->addWire(NEW_ID); Wire *past_clk = module->addWire(NEW_ID);
past_clk->attributes["\\init"] = clkpol ? State::S1 : State::S0; past_clk->attributes[ID::init] = clkpol ? State::S1 : State::S0;
if (word_dff) if (word_dff)
module->addFf(NEW_ID, clk, past_clk); module->addFf(NEW_ID, clk, past_clk);
else else
module->addFfGate(NEW_ID, clk, past_clk); module->addFfGate(NEW_ID, clk, past_clk);
SigSpec sig_d = cell->getPort("\\D"); SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort("\\Q"); SigSpec sig_q = cell->getPort(ID::Q);
log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n", log("Replacing %s.%s (%s): CLK=%s, D=%s, Q=%s\n",
log_id(module), log_id(cell), log_id(cell->type), log_id(module), log_id(cell), log_id(cell->type),
@ -277,20 +277,20 @@ struct Clk2fflogicPass : public Pass {
module->addFfGate(NEW_ID, sig_q, past_q); module->addFfGate(NEW_ID, sig_q, past_q);
} }
if (cell->type == "$adff") if (cell->type == ID($adff))
{ {
SigSpec arst = cell->getPort("\\ARST"); SigSpec arst = cell->getPort(ID::ARST);
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
Const rstval = cell->parameters["\\ARST_VALUE"]; Const rstval = cell->parameters[ID::ARST_VALUE];
Wire *past_arst = module->addWire(NEW_ID); Wire *past_arst = module->addWire(NEW_ID);
module->addFf(NEW_ID, arst, past_arst); module->addFf(NEW_ID, arst, past_arst);
if (cell->parameters["\\ARST_POLARITY"].as_bool()) if (cell->parameters[ID::ARST_POLARITY].as_bool())
arst = module->LogicOr(NEW_ID, arst, past_arst); arst = module->LogicOr(NEW_ID, arst, past_arst);
else else
arst = module->LogicAnd(NEW_ID, arst, past_arst); arst = module->LogicAnd(NEW_ID, arst, past_arst);
if (cell->parameters["\\ARST_POLARITY"].as_bool()) if (cell->parameters[ID::ARST_POLARITY].as_bool())
module->addMux(NEW_ID, qval, rstval, arst, sig_q); module->addMux(NEW_ID, qval, rstval, arst, sig_q);
else else
module->addMux(NEW_ID, rstval, qval, arst, sig_q); module->addMux(NEW_ID, rstval, qval, arst, sig_q);
@ -299,7 +299,7 @@ struct Clk2fflogicPass : public Pass {
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_), if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_))) ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
{ {
SigSpec arst = cell->getPort("\\R"); SigSpec arst = cell->getPort(ID::R);
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigBit rstval = (cell->type[8] == '1'); SigBit rstval = (cell->type[8] == '1');
@ -316,16 +316,16 @@ struct Clk2fflogicPass : public Pass {
module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q); module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
} }
else else
if (cell->type == "$dffsr") if (cell->type == ID($dffsr))
{ {
SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge); SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
SigSpec setval = cell->getPort("\\SET"); SigSpec setval = cell->getPort(ID::SET);
SigSpec clrval = cell->getPort("\\CLR"); SigSpec clrval = cell->getPort(ID::CLR);
if (!cell->parameters["\\SET_POLARITY"].as_bool()) if (!cell->parameters[ID::SET_POLARITY].as_bool())
setval = module->Not(NEW_ID, setval); setval = module->Not(NEW_ID, setval);
if (cell->parameters["\\CLR_POLARITY"].as_bool()) if (cell->parameters[ID::CLR_POLARITY].as_bool())
clrval = module->Not(NEW_ID, clrval); clrval = module->Not(NEW_ID, clrval);
qval = module->Or(NEW_ID, qval, setval); qval = module->Or(NEW_ID, qval, setval);
@ -337,7 +337,7 @@ struct Clk2fflogicPass : public Pass {
{ {
SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge); SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
SigSpec setval = cell->getPort(ID::S); SigSpec setval = cell->getPort(ID::S);
SigSpec clrval = cell->getPort("\\R"); SigSpec clrval = cell->getPort(ID::R);
if (cell->type[9] != 'P') if (cell->type[9] != 'P')
setval = module->Not(NEW_ID, setval); setval = module->Not(NEW_ID, setval);
@ -348,7 +348,7 @@ struct Clk2fflogicPass : public Pass {
qval = module->OrGate(NEW_ID, qval, setval); qval = module->OrGate(NEW_ID, qval, setval);
module->addAndGate(NEW_ID, qval, clrval, sig_q); module->addAndGate(NEW_ID, qval, clrval, sig_q);
} }
else if (cell->type == "$dff") else if (cell->type == ID($dff))
{ {
module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q); module->addMux(NEW_ID, past_q, past_d, clock_edge, sig_q);
} }
@ -371,8 +371,8 @@ struct Clk2fflogicPass : public Pass {
} }
if (assign_initval) { if (assign_initval) {
past_d->attributes["\\init"] = initval; past_d->attributes[ID::init] = initval;
past_q->attributes["\\init"] = initval; past_q->attributes[ID::init] = initval;
} }
module->remove(cell); module->remove(cell);
@ -381,10 +381,10 @@ struct Clk2fflogicPass : public Pass {
} }
for (auto wire : module->wires()) for (auto wire : module->wires())
if (wire->attributes.count("\\init") > 0) if (wire->attributes.count(ID::init) > 0)
{ {
bool delete_initattr = true; bool delete_initattr = true;
Const initval = wire->attributes.at("\\init"); Const initval = wire->attributes.at(ID::init);
SigSpec initsig = sigmap(wire); SigSpec initsig = sigmap(wire);
for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++) for (int i = 0; i < GetSize(initval) && i < GetSize(initsig); i++)
@ -394,9 +394,9 @@ struct Clk2fflogicPass : public Pass {
delete_initattr = false; delete_initattr = false;
if (delete_initattr) if (delete_initattr)
wire->attributes.erase("\\init"); wire->attributes.erase(ID::init);
else else
wire->attributes.at("\\init") = initval; wire->attributes.at(ID::init) = initval;
} }
} }

2
passes/sat/cutpoint.cc
View file

@ -75,7 +75,7 @@ struct CutpointPass : public Pass {
pool<SigBit> cutpoint_bits; pool<SigBit> cutpoint_bits;
for (auto cell : module->selected_cells()) { for (auto cell : module->selected_cells()) {
if (cell->type == "$anyseq") if (cell->type == ID($anyseq))
continue; continue;
log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell)); log("Removing cell %s.%s, making all cell outputs cutpoints.\n", log_id(module), log_id(cell));
for (auto &conn : cell->connections()) { for (auto &conn : cell->connections()) {

8
passes/sat/eval.cc
View file

@ -153,11 +153,11 @@ struct VlogHammerReporter
ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals)); ez->assume(satgen.signals_eq(recorded_set_vars, recorded_set_vals));
std::vector<int> y_vec = satgen.importDefSigSpec(module->wire("\\y")); std::vector<int> y_vec = satgen.importDefSigSpec(module->wire(ID(y)));
std::vector<bool> y_values; std::vector<bool> y_values;
if (model_undef) { if (model_undef) {
std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire("\\y")); std::vector<int> y_undef_vec = satgen.importUndefSigSpec(module->wire(ID(y)));
y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end()); y_vec.insert(y_vec.end(), y_undef_vec.begin(), y_undef_vec.end());
} }
@ -268,10 +268,10 @@ struct VlogHammerReporter
} }
} }
if (module->wire("\\y") == nullptr) if (module->wire(ID(y)) == nullptr)
log_error("No output wire (y) found in module %s!\n", log_id(module->name)); log_error("No output wire (y) found in module %s!\n", log_id(module->name));
RTLIL::SigSpec sig(module->wire("\\y")); RTLIL::SigSpec sig(module->wire(ID(y)));
RTLIL::SigSpec undef; RTLIL::SigSpec undef;
while (!ce.eval(sig, undef)) { while (!ce.eval(sig, undef)) {

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