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kernel: big fat patch to use more ID::*, otherwise ID(*)
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parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -49,10 +49,10 @@ struct Ice40FfssrPass : public Pass {
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extra_args(args, argidx, design);
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pool<IdString> sb_dff_types;
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sb_dff_types.insert("\\SB_DFF");
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sb_dff_types.insert("\\SB_DFFE");
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sb_dff_types.insert("\\SB_DFFN");
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sb_dff_types.insert("\\SB_DFFNE");
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sb_dff_types.insert(ID(SB_DFF));
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sb_dff_types.insert(ID(SB_DFFE));
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sb_dff_types.insert(ID(SB_DFFN));
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sb_dff_types.insert(ID(SB_DFFNE));
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for (auto module : design->selected_modules())
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{
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@ -69,7 +69,7 @@ struct Ice40FfssrPass : public Pass {
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continue;
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}
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if (cell->type != "$_MUX_")
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if (cell->type != ID($_MUX_))
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continue;
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SigBit bit_a = sigmap(cell->getPort(ID::A));
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@ -81,10 +81,10 @@ struct Ice40FfssrPass : public Pass {
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for (auto cell : ff_cells)
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{
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if (cell->get_bool_attribute("\\dont_touch"))
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if (cell->get_bool_attribute(ID(dont_touch)))
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continue;
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SigSpec sig_d = cell->getPort("\\D");
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SigSpec sig_d = cell->getPort(ID::D);
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if (GetSize(sig_d) < 1)
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continue;
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@ -117,11 +117,11 @@ struct Ice40FfssrPass : public Pass {
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if (sr_val == State::S1) {
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cell->type = cell->type.str() + "SS";
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cell->setPort(ID::S, sr_sig);
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cell->setPort("\\D", bit_d);
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cell->setPort(ID::D, bit_d);
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} else {
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cell->type = cell->type.str() + "SR";
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cell->setPort("\\R", sr_sig);
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cell->setPort("\\D", bit_d);
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cell->setPort(ID::R, sr_sig);
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cell->setPort(ID::D, bit_d);
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}
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}
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}
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