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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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14
techlibs/ice40/ice40_braminit.cc
View file

@ -33,15 +33,15 @@ static void run_ice40_braminit(Module *module)
uint16_t mem[256];
/* Only consider cells we're interested in */
if (cell->type != "\\SB_RAM40_4K" &&
cell->type != "\\SB_RAM40_4KNR" &&
cell->type != "\\SB_RAM40_4KNW" &&
cell->type != "\\SB_RAM40_4KNRNW")
if (cell->type != ID(SB_RAM40_4K) &&
cell->type != ID(SB_RAM40_4KNR) &&
cell->type != ID(SB_RAM40_4KNW) &&
cell->type != ID(SB_RAM40_4KNRNW))
continue;
if (!cell->hasParam("\\INIT_FILE"))
if (!cell->hasParam(ID(INIT_FILE)))
continue;
std::string init_file = cell->getParam("\\INIT_FILE").decode_string();
cell->unsetParam("\\INIT_FILE");
std::string init_file = cell->getParam(ID(INIT_FILE)).decode_string();
cell->unsetParam(ID(INIT_FILE));
if (init_file == "")
continue;

30
techlibs/ice40/ice40_ffinit.cc
View file

@ -62,11 +62,11 @@ struct Ice40FfinitPass : public Pass {
for (auto wire : module->selected_wires())
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at("\\init");
Const initval = wire->attributes.at(ID::init);
init_wires.insert(wire);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
@ -93,9 +93,9 @@ struct Ice40FfinitPass : public Pass {
}
pool<IdString> sb_dff_types = {
"\\SB_DFF", "\\SB_DFFE", "\\SB_DFFSR", "\\SB_DFFR", "\\SB_DFFSS", "\\SB_DFFS", "\\SB_DFFESR",
"\\SB_DFFER", "\\SB_DFFESS", "\\SB_DFFES", "\\SB_DFFN", "\\SB_DFFNE", "\\SB_DFFNSR", "\\SB_DFFNR",
"\\SB_DFFNSS", "\\SB_DFFNS", "\\SB_DFFNESR", "\\SB_DFFNER", "\\SB_DFFNESS", "\\SB_DFFNES"
ID(SB_DFF), ID(SB_DFFE), ID(SB_DFFSR), ID(SB_DFFR), ID(SB_DFFSS), ID(SB_DFFS), ID(SB_DFFESR),
ID(SB_DFFER), ID(SB_DFFESS), ID(SB_DFFES), ID(SB_DFFN), ID(SB_DFFNE), ID(SB_DFFNSR), ID(SB_DFFNR),
ID(SB_DFFNSS), ID(SB_DFFNS), ID(SB_DFFNESR), ID(SB_DFFNER), ID(SB_DFFNESS), ID(SB_DFFNES)
};
for (auto cell : module->selected_cells())
@ -103,8 +103,8 @@ struct Ice40FfinitPass : public Pass {
if (!sb_dff_types.count(cell->type))
continue;
SigSpec sig_d = cell->getPort("\\D");
SigSpec sig_q = cell->getPort("\\Q");
SigSpec sig_d = cell->getPort(ID::D);
SigSpec sig_q = cell->getPort(ID::Q);
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@ -133,14 +133,14 @@ struct Ice40FfinitPass : public Pass {
if (type_str.back() == 'S') {
type_str.back() = 'R';
cell->type = type_str;
cell->setPort("\\R", cell->getPort(ID::S));
cell->setPort(ID::R, cell->getPort(ID::S));
cell->unsetPort(ID::S);
} else
if (type_str.back() == 'R') {
type_str.back() = 'S';
cell->type = type_str;
cell->setPort(ID::S, cell->getPort("\\R"));
cell->unsetPort("\\R");
cell->setPort(ID::S, cell->getPort(ID::R));
cell->unsetPort(ID::R);
}
Wire *new_bit_d = module->addWire(NEW_ID);
@ -149,17 +149,17 @@ struct Ice40FfinitPass : public Pass {
module->addNotGate(NEW_ID, bit_d, new_bit_d);
module->addNotGate(NEW_ID, new_bit_q, bit_q);
cell->setPort("\\D", new_bit_d);
cell->setPort("\\Q", new_bit_q);
cell->setPort(ID::D, new_bit_d);
cell->setPort(ID::Q, new_bit_q);
}
for (auto wire : init_wires)
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const &initval = wire->attributes.at("\\init");
Const &initval = wire->attributes.at(ID::init);
bool remove_attribute = true;
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
@ -170,7 +170,7 @@ struct Ice40FfinitPass : public Pass {
}
if (remove_attribute)
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
}
}

20
techlibs/ice40/ice40_ffssr.cc
View file

@ -49,10 +49,10 @@ struct Ice40FfssrPass : public Pass {
extra_args(args, argidx, design);
pool<IdString> sb_dff_types;
sb_dff_types.insert("\\SB_DFF");
sb_dff_types.insert("\\SB_DFFE");
sb_dff_types.insert("\\SB_DFFN");
sb_dff_types.insert("\\SB_DFFNE");
sb_dff_types.insert(ID(SB_DFF));
sb_dff_types.insert(ID(SB_DFFE));
sb_dff_types.insert(ID(SB_DFFN));
sb_dff_types.insert(ID(SB_DFFNE));
for (auto module : design->selected_modules())
{
@ -69,7 +69,7 @@ struct Ice40FfssrPass : public Pass {
continue;
}
if (cell->type != "$_MUX_")
if (cell->type != ID($_MUX_))
continue;
SigBit bit_a = sigmap(cell->getPort(ID::A));
@ -81,10 +81,10 @@ struct Ice40FfssrPass : public Pass {
for (auto cell : ff_cells)
{
if (cell->get_bool_attribute("\\dont_touch"))
if (cell->get_bool_attribute(ID(dont_touch)))
continue;
SigSpec sig_d = cell->getPort("\\D");
SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
@ -117,11 +117,11 @@ struct Ice40FfssrPass : public Pass {
if (sr_val == State::S1) {
cell->type = cell->type.str() + "SS";
cell->setPort(ID::S, sr_sig);
cell->setPort("\\D", bit_d);
cell->setPort(ID::D, bit_d);
} else {
cell->type = cell->type.str() + "SR";
cell->setPort("\\R", sr_sig);
cell->setPort("\\D", bit_d);
cell->setPort(ID::R, sr_sig);
cell->setPort(ID::D, bit_d);
}
}
}

86
techlibs/ice40/ice40_opt.cc
View file

@ -41,26 +41,26 @@ static void run_ice40_opts(Module *module)
for (auto cell : module->selected_cells())
{
if (!cell->type.in("\\SB_LUT4", "\\SB_CARRY", "$__ICE40_CARRY_WRAPPER"))
if (!cell->type.in(ID(SB_LUT4), ID(SB_CARRY), ID($__ICE40_CARRY_WRAPPER)))
continue;
if (cell->has_keep_attr())
continue;
if (cell->type == "\\SB_LUT4")
if (cell->type == ID(SB_LUT4))
{
sb_lut_cells.push_back(cell);
continue;
}
if (cell->type == "\\SB_CARRY")
if (cell->type == ID(SB_CARRY))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
SigBit inbit[3] = {
get_bit_or_zero(cell->getPort("\\I0")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\CI"))
get_bit_or_zero(cell->getPort(ID(I0))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(ID::CI))
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
@ -79,8 +79,8 @@ static void run_ice40_opts(Module *module)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
module->connect(cell->getPort("\\CO")[0], replacement_output);
optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized away SB_CARRY cell %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
@ -89,7 +89,7 @@ static void run_ice40_opts(Module *module)
continue;
}
if (cell->type == "$__ICE40_CARRY_WRAPPER")
if (cell->type == ID($__ICE40_CARRY_WRAPPER))
{
SigSpec non_const_inputs, replacement_output;
int count_zeros = 0, count_ones = 0;
@ -97,7 +97,7 @@ static void run_ice40_opts(Module *module)
SigBit inbit[3] = {
cell->getPort(ID::A),
cell->getPort(ID::B),
cell->getPort("\\CI")
cell->getPort(ID::CI)
};
for (int i = 0; i < 3; i++)
if (inbit[i].wire == nullptr) {
@ -116,7 +116,7 @@ static void run_ice40_opts(Module *module)
replacement_output = non_const_inputs;
if (GetSize(replacement_output)) {
optimized_co.insert(sigmap(cell->getPort("\\CO")[0]));
optimized_co.insert(sigmap(cell->getPort(ID::CO)[0]));
auto it = cell->attributes.find(ID(SB_LUT4.name));
if (it != cell->attributes.end()) {
module->rename(cell, it->second.decode_string());
@ -124,9 +124,9 @@ static void run_ice40_opts(Module *module)
for (const auto &a : cell->attributes)
if (a.first.begins_with("\\SB_LUT4.\\"))
new_attr[a.first.c_str() + strlen("\\SB_LUT4.")] = a.second;
else if (a.first == ID(src))
else if (a.first == ID::src)
new_attr.insert(std::make_pair(a.first, a.second));
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID(module_not_derived)))
else if (a.first.in(ID(SB_LUT4.name), ID::keep, ID::module_not_derived))
continue;
else if (a.first.begins_with("\\SB_CARRY.\\"))
continue;
@ -134,22 +134,22 @@ static void run_ice40_opts(Module *module)
log_abort();
cell->attributes = std::move(new_attr);
}
module->connect(cell->getPort("\\CO")[0], replacement_output);
module->connect(cell->getPort(ID::CO)[0], replacement_output);
module->design->scratchpad_set_bool("opt.did_something", true);
log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n",
log_id(module), log_id(cell), log_signal(replacement_output));
cell->type = "$lut";
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort("\\I0")) });
cell->setPort(ID::Y, cell->getPort("\\O"));
cell->type = ID($lut);
auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID::CI : ID(I3)));
cell->setPort(ID::A, { I3, inbit[1], inbit[0], get_bit_or_zero(cell->getPort(ID(I0))) });
cell->setPort(ID::Y, cell->getPort(ID::O));
cell->unsetPort(ID::B);
cell->unsetPort("\\CI");
cell->unsetPort("\\I0");
cell->unsetPort("\\I3");
cell->unsetPort("\\CO");
cell->unsetPort("\\O");
cell->setParam("\\WIDTH", 4);
cell->unsetParam("\\I3_IS_CI");
cell->unsetPort(ID::CI);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I3));
cell->unsetPort(ID::CO);
cell->unsetPort(ID::O);
cell->setParam(ID::WIDTH, 4);
cell->unsetParam(ID(I3_IS_CI));
}
continue;
}
@ -159,10 +159,10 @@ static void run_ice40_opts(Module *module)
{
SigSpec inbits;
inbits.append(get_bit_or_zero(cell->getPort("\\I0")));
inbits.append(get_bit_or_zero(cell->getPort("\\I1")));
inbits.append(get_bit_or_zero(cell->getPort("\\I2")));
inbits.append(get_bit_or_zero(cell->getPort("\\I3")));
inbits.append(get_bit_or_zero(cell->getPort(ID(I0))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I1))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I2))));
inbits.append(get_bit_or_zero(cell->getPort(ID(I3))));
sigmap.apply(inbits);
if (optimized_co.count(inbits[0])) goto remap_lut;
@ -177,23 +177,23 @@ static void run_ice40_opts(Module *module)
module->design->scratchpad_set_bool("opt.did_something", true);
log("Mapping SB_LUT4 cell %s.%s back to logic.\n", log_id(module), log_id(cell));
cell->type ="$lut";
cell->setParam("\\WIDTH", 4);
cell->setParam("\\LUT", cell->getParam("\\LUT_INIT"));
cell->unsetParam("\\LUT_INIT");
cell->type = ID($lut);
cell->setParam(ID::WIDTH, 4);
cell->setParam(ID::LUT, cell->getParam(ID(LUT_INIT)));
cell->unsetParam(ID(LUT_INIT));
cell->setPort(ID::A, SigSpec({
get_bit_or_zero(cell->getPort("\\I3")),
get_bit_or_zero(cell->getPort("\\I2")),
get_bit_or_zero(cell->getPort("\\I1")),
get_bit_or_zero(cell->getPort("\\I0"))
get_bit_or_zero(cell->getPort(ID(I3))),
get_bit_or_zero(cell->getPort(ID(I2))),
get_bit_or_zero(cell->getPort(ID(I1))),
get_bit_or_zero(cell->getPort(ID(I0)))
}));
cell->setPort(ID::Y, cell->getPort("\\O")[0]);
cell->unsetPort("\\I0");
cell->unsetPort("\\I1");
cell->unsetPort("\\I2");
cell->unsetPort("\\I3");
cell->unsetPort("\\O");
cell->setPort(ID::Y, cell->getPort(ID::O)[0]);
cell->unsetPort(ID(I0));
cell->unsetPort(ID(I1));
cell->unsetPort(ID(I2));
cell->unsetPort(ID(I3));
cell->unsetPort(ID::O);
cell->check();
simplemap_lut(module, cell);