mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-24 14:53:42 +00:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
|
@ -63,11 +63,11 @@ struct Ecp5FfinitPass : public Pass {
|
|||
|
||||
for (auto wire : module->selected_wires())
|
||||
{
|
||||
if (wire->attributes.count("\\init") == 0)
|
||||
if (wire->attributes.count(ID::init) == 0)
|
||||
continue;
|
||||
|
||||
SigSpec wirebits = sigmap(wire);
|
||||
Const initval = wire->attributes.at("\\init");
|
||||
Const initval = wire->attributes.at(ID::init);
|
||||
init_wires.insert(wire);
|
||||
|
||||
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
|
||||
|
@ -94,11 +94,11 @@ struct Ecp5FfinitPass : public Pass {
|
|||
}
|
||||
for (auto cell : module->selected_cells())
|
||||
{
|
||||
if (cell->type != "\\TRELLIS_FF")
|
||||
if (cell->type != ID(TRELLIS_FF))
|
||||
continue;
|
||||
SigSpec sig_d = cell->getPort("\\DI");
|
||||
SigSpec sig_q = cell->getPort("\\Q");
|
||||
SigSpec sig_lsr = cell->getPort("\\LSR");
|
||||
SigSpec sig_d = cell->getPort(ID(DI));
|
||||
SigSpec sig_q = cell->getPort(ID::Q);
|
||||
SigSpec sig_lsr = cell->getPort(ID(LSR));
|
||||
|
||||
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
|
||||
continue;
|
||||
|
@ -107,8 +107,8 @@ struct Ecp5FfinitPass : public Pass {
|
|||
SigBit bit_q = sigmap(sig_q[0]);
|
||||
|
||||
std::string regset = "RESET";
|
||||
if (cell->hasParam("\\REGSET"))
|
||||
regset = cell->getParam("\\REGSET").decode_string();
|
||||
if (cell->hasParam(ID(REGSET)))
|
||||
regset = cell->getParam(ID(REGSET)).decode_string();
|
||||
State resetState;
|
||||
if (regset == "SET")
|
||||
resetState = State::S1;
|
||||
|
@ -136,8 +136,8 @@ struct Ecp5FfinitPass : public Pass {
|
|||
|
||||
if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) {
|
||||
std::string srmode = "LSR_OVER_CE";
|
||||
if (cell->hasParam("\\SRMODE"))
|
||||
srmode = cell->getParam("\\SRMODE").decode_string();
|
||||
if (cell->hasParam(ID(SRMODE)))
|
||||
srmode = cell->getParam(ID(SRMODE)).decode_string();
|
||||
if (srmode == "ASYNC") {
|
||||
log("Async reset value %c for FF cell %s inconsistent with init value %c.\n",
|
||||
resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0');
|
||||
|
@ -150,14 +150,14 @@ struct Ecp5FfinitPass : public Pass {
|
|||
module->addOrGate(NEW_ID, bit_d, bit_lsr, new_bit_d);
|
||||
}
|
||||
|
||||
cell->setPort("\\DI", new_bit_d);
|
||||
cell->setPort("\\LSR", State::S0);
|
||||
cell->setPort(ID(DI), new_bit_d);
|
||||
cell->setPort(ID(LSR), State::S0);
|
||||
|
||||
if(cell->hasPort("\\CE")) {
|
||||
if(cell->hasPort(ID(CE))) {
|
||||
std::string cemux = "CE";
|
||||
if (cell->hasParam("\\CEMUX"))
|
||||
cemux = cell->getParam("\\CEMUX").decode_string();
|
||||
SigSpec sig_ce = cell->getPort("\\CE");
|
||||
if (cell->hasParam(ID(CEMUX)))
|
||||
cemux = cell->getParam(ID(CEMUX)).decode_string();
|
||||
SigSpec sig_ce = cell->getPort(ID(CE));
|
||||
if (GetSize(sig_ce) >= 1) {
|
||||
SigBit bit_ce = sigmap(sig_ce[0]);
|
||||
Wire *new_bit_ce = module->addWire(NEW_ID);
|
||||
|
@ -165,25 +165,25 @@ struct Ecp5FfinitPass : public Pass {
|
|||
module->addAndnotGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
|
||||
else
|
||||
module->addOrGate(NEW_ID, bit_ce, bit_lsr, new_bit_ce);
|
||||
cell->setPort("\\CE", new_bit_ce);
|
||||
cell->setPort(ID(CE), new_bit_ce);
|
||||
}
|
||||
}
|
||||
cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
|
||||
cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
|
||||
handled_initbits.insert(bit_q);
|
||||
}
|
||||
} else {
|
||||
cell->setParam("\\REGSET", val != State::S0 ? Const("SET") : Const("RESET"));
|
||||
cell->setParam(ID(REGSET), val != State::S0 ? Const("SET") : Const("RESET"));
|
||||
handled_initbits.insert(bit_q);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto wire : init_wires)
|
||||
{
|
||||
if (wire->attributes.count("\\init") == 0)
|
||||
if (wire->attributes.count(ID::init) == 0)
|
||||
continue;
|
||||
|
||||
SigSpec wirebits = sigmap(wire);
|
||||
Const &initval = wire->attributes.at("\\init");
|
||||
Const &initval = wire->attributes.at(ID::init);
|
||||
bool remove_attribute = true;
|
||||
|
||||
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++) {
|
||||
|
@ -194,7 +194,7 @@ struct Ecp5FfinitPass : public Pass {
|
|||
}
|
||||
|
||||
if (remove_attribute)
|
||||
wire->attributes.erase("\\init");
|
||||
wire->attributes.erase(ID::init);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
@ -85,7 +85,7 @@ struct Ecp5GsrPass : public Pass {
|
|||
continue;
|
||||
|
||||
bool gsren = found_gsr;
|
||||
if (cell->get_bool_attribute("\\nogsr"))
|
||||
if (cell->get_bool_attribute(ID(nogsr)))
|
||||
gsren = false;
|
||||
cell->setParam(ID(GSR), gsren ? Const("ENABLED") : Const("DISABLED"));
|
||||
|
||||
|
@ -102,7 +102,7 @@ struct Ecp5GsrPass : public Pass {
|
|||
{
|
||||
if (cell->type != ID($_NOT_))
|
||||
continue;
|
||||
SigSpec sig_a = cell->getPort(ID(A)), sig_y = cell->getPort(ID(Y));
|
||||
SigSpec sig_a = cell->getPort(ID::A), sig_y = cell->getPort(ID::Y);
|
||||
if (GetSize(sig_a) < 1 || GetSize(sig_y) < 1)
|
||||
continue;
|
||||
SigBit a = sigmap(sig_a[0]);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue