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https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -47,7 +47,7 @@ struct Coolrunner2SopPass : public Pass {
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dict<SigBit, tuple<SigBit, Cell*>> not_cells;
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$_NOT_")
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if (cell->type == ID($_NOT_))
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{
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auto not_input = sigmap(cell->getPort(ID::A)[0]);
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auto not_output = sigmap(cell->getPort(ID::Y)[0]);
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@ -56,43 +56,43 @@ struct Coolrunner2SopPass : public Pass {
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}
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// Find wires that need to become special product terms
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dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
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dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
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dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv;
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dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv;
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for (auto cell : module->selected_cells())
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{
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if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
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"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
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if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
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ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
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{
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if (cell->hasPort("\\PRE"))
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special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\PRE"));
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if (cell->hasPort("\\CLR"))
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special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\CLR"));
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if (cell->hasPort("\\CE"))
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special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\CE"));
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if (cell->hasPort(ID(PRE)))
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special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
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make_tuple(cell, ID(PRE)));
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if (cell->hasPort(ID::CLR))
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special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert(
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make_tuple(cell, ID::CLR));
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if (cell->hasPort(ID(CE)))
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special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
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make_tuple(cell, ID(CE)));
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if (cell->hasPort("\\C"))
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special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\C"));
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if (cell->hasPort("\\G"))
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special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
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tuple<Cell*, const char *>(cell, "\\G"));
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if (cell->hasPort(ID::C))
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special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert(
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make_tuple(cell, ID::C));
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if (cell->hasPort(ID::G))
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special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert(
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make_tuple(cell, ID::G));
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}
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}
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// Process $sop cells
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for (auto cell : module->selected_cells())
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{
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if (cell->type == "$sop")
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if (cell->type == ID($sop))
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{
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// Read the inputs/outputs/parameters of the $sop cell
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auto sop_inputs = sigmap(cell->getPort(ID::A));
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auto sop_output = sigmap(cell->getPort(ID::Y))[0];
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auto sop_depth = cell->getParam("\\DEPTH").as_int();
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auto sop_width = cell->getParam("\\WIDTH").as_int();
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auto sop_table = cell->getParam("\\TABLE");
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auto sop_depth = cell->getParam(ID::DEPTH).as_int();
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auto sop_width = cell->getParam(ID::WIDTH).as_int();
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auto sop_table = cell->getParam(ID::TABLE);
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auto sop_output_wire_name = sop_output.wire->name.c_str();
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@ -139,12 +139,12 @@ struct Coolrunner2SopPass : public Pass {
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// Construct the cell
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auto and_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
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"\\ANDTERM");
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and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
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and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
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and_cell->setPort("\\OUT", and_out);
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and_cell->setPort("\\IN", and_in_true);
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and_cell->setPort("\\IN_B", and_in_comp);
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ID(ANDTERM));
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and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
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and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
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and_cell->setPort(ID(OUT), and_out);
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and_cell->setPort(ID(IN), and_in_true);
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and_cell->setPort(ID(IN_B), and_in_comp);
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}
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if (sop_depth == 1)
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@ -152,17 +152,17 @@ struct Coolrunner2SopPass : public Pass {
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// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", has_invert);
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xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
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xor_cell->setPort("\\OUT", sop_output);
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ID(MACROCELL_XOR));
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xor_cell->setParam(ID(INVERT_OUT), has_invert);
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xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
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xor_cell->setPort(ID(OUT), sop_output);
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// Special P-term handling
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if (is_special_pterm)
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{
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// Can always connect the P-term directly if it's going
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// into something invert-capable
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for (auto x : special_pterms_inv[sop_output])
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for (const auto &x : special_pterms_inv[sop_output])
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{
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std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
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@ -170,14 +170,14 @@ struct Coolrunner2SopPass : public Pass {
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if (has_invert)
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{
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auto cell = std::get<0>(x);
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if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
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else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
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else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
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else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
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else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
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else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
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else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
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else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
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if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
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else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
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else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
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else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
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else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
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else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
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else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
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else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
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else log_assert(!"Internal error! Bad cell type!");
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}
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}
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@ -203,18 +203,18 @@ struct Coolrunner2SopPass : public Pass {
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// Construct the OR cell
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auto or_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
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"\\ORTERM");
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or_cell->setParam("\\WIDTH", sop_depth);
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or_cell->setPort("\\IN", intermed_wires);
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or_cell->setPort("\\OUT", or_to_xor_wire);
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ID(ORTERM));
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or_cell->setParam(ID::WIDTH, sop_depth);
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or_cell->setPort(ID(IN), intermed_wires);
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or_cell->setPort(ID(OUT), or_to_xor_wire);
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// Construct the XOR cell
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auto xor_cell = module->addCell(
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module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
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"\\MACROCELL_XOR");
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xor_cell->setParam("\\INVERT_OUT", has_invert);
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xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
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xor_cell->setPort("\\OUT", sop_output);
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ID(MACROCELL_XOR));
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xor_cell->setParam(ID(INVERT_OUT), has_invert);
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xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
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xor_cell->setPort(ID(OUT), sop_output);
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}
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// Finally, remove the $sop cell
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