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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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166
techlibs/coolrunner2/coolrunner2_fixup.cc
View file

@ -34,9 +34,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF1_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", true);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), true);
xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(false))
{
@ -45,9 +45,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
}
else if (inwire == SigBit(RTLIL::State::Sx))
{
@ -57,9 +57,9 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR_OUT", cellname)));
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF0_XOR", cellname)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(OUT), outwire);
}
else
{
@ -73,19 +73,19 @@ RTLIL::Wire *makexorbuffer(RTLIL::Module *module, SigBit inwire, const char *cel
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", and_to_xor_wire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), and_to_xor_wire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_XOR", inwire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", false);
xor_cell->setPort("\\IN_PTC", and_to_xor_wire);
xor_cell->setPort("\\OUT", outwire);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), false);
xor_cell->setPort(ID(IN_PTC), and_to_xor_wire);
xor_cell->setPort(ID(OUT), outwire);
}
return outwire;
@ -100,12 +100,12 @@ RTLIL::Wire *makeptermbuffer(RTLIL::Module *module, SigBit inwire)
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2fix$%s_BUF_AND", inwire_name)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", 1);
and_cell->setParam("\\COMP_INP", 0);
and_cell->setPort("\\OUT", outwire);
and_cell->setPort("\\IN", inwire);
and_cell->setPort("\\IN_B", SigSpec());
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), 1);
and_cell->setParam(ID(COMP_INP), 0);
and_cell->setPort(ID(OUT), outwire);
and_cell->setPort(ID(IN), inwire);
and_cell->setPort(ID(IN_B), SigSpec());
return outwire;
}
@ -133,10 +133,10 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_ff;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
auto output = sigmap(cell->getPort("\\Q")[0]);
auto output = sigmap(cell->getPort(ID::Q)[0]);
sig_fed_by_ff.insert(output);
}
}
@ -145,9 +145,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_xor;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\MACROCELL_XOR")
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_xor.insert(output);
}
}
@ -156,10 +156,10 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_io;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\IBUF", "\\IOBUFE"))
if (cell->type.in(ID(IBUF), ID(IOBUFE)))
{
if (cell->hasPort("\\O")) {
auto output = sigmap(cell->getPort("\\O")[0]);
if (cell->hasPort(ID::O)) {
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_io.insert(output);
}
}
@ -169,9 +169,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_pterm;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
if (cell->type == ID(ANDTERM))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
sig_fed_by_pterm.insert(output);
}
}
@ -180,9 +180,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufg;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFG")
if (cell->type == ID(BUFG))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufg.insert(output);
}
}
@ -191,9 +191,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufgsr;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGSR")
if (cell->type == ID(BUFGSR))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgsr.insert(output);
}
}
@ -202,9 +202,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_bufgts;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\BUFGTS")
if (cell->type == ID(BUFGTS))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_bufgts.insert(output);
}
}
@ -213,9 +213,9 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> sig_fed_by_ibuf;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\IBUF")
if (cell->type == ID(IBUF))
{
auto output = sigmap(cell->getPort("\\O")[0]);
auto output = sigmap(cell->getPort(ID::O)[0]);
sig_fed_by_ibuf.insert(output);
}
}
@ -254,15 +254,15 @@ struct Coolrunner2FixupPass : public Pass {
// the pad-to-zia path has to be used up and the register
// can't be packed with the ibuf.
if (fanout_count == 1 && maybe_ff_cell->type.in(
"\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit input;
if (maybe_ff_cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(maybe_ff_cell->getPort("\\T")[0]);
if (maybe_ff_cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
input = sigmap(maybe_ff_cell->getPort(ID::T)[0]);
else
input = sigmap(maybe_ff_cell->getPort("\\D")[0]);
SigBit output = sigmap(maybe_ff_cell->getPort("\\Q")[0]);
input = sigmap(maybe_ff_cell->getPort(ID::D)[0]);
SigBit output = sigmap(maybe_ff_cell->getPort(ID::Q)[0]);
if (input == ibuf_out_wire)
{
@ -279,17 +279,17 @@ struct Coolrunner2FixupPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\LDCP", "\\LDCP_N",
"\\FTCP", "\\FTCP_N", "\\FTDCP", "\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(LDCP), ID(LDCP_N),
ID(FTCP), ID(FTCP_N), ID(FTDCP), ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
// Buffering FF inputs. FF inputs can only come from either
// an IO pin or from an XOR. Otherwise AND/XOR cells need
// to be inserted.
SigBit input;
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
input = sigmap(cell->getPort("\\T")[0]);
if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
input = sigmap(cell->getPort(ID::T)[0]);
else
input = sigmap(cell->getPort("\\D")[0]);
input = sigmap(cell->getPort(ID::D)[0]);
// If the input wasn't an XOR nor an IO, then a buffer
// definitely needs to be added.
@ -302,10 +302,10 @@ struct Coolrunner2FixupPass : public Pass {
auto xor_to_ff_wire = makexorbuffer(module, input, cell->name.c_str());
if (cell->type.in("\\FTCP", "\\FTCP_N", "\\FTDCP"))
cell->setPort("\\T", xor_to_ff_wire);
if (cell->type.in(ID(FTCP), ID(FTCP_N), ID(FTDCP)))
cell->setPort(ID::T, xor_to_ff_wire);
else
cell->setPort("\\D", xor_to_ff_wire);
cell->setPort(ID::D, xor_to_ff_wire);
}
// Buffering FF clocks. FF clocks can only come from either
@ -313,10 +313,10 @@ struct Coolrunner2FixupPass : public Pass {
// in coolrunner2_sop (e.g. if clock is generated from
// AND-ing two signals) but not in all cases.
SigBit clock;
if (cell->type.in("\\LDCP", "\\LDCP_N"))
clock = sigmap(cell->getPort("\\G")[0]);
if (cell->type.in(ID(LDCP), ID(LDCP_N)))
clock = sigmap(cell->getPort(ID::G)[0]);
else
clock = sigmap(cell->getPort("\\C")[0]);
clock = sigmap(cell->getPort(ID::C)[0]);
if (!sig_fed_by_pterm[clock] && !sig_fed_by_bufg[clock])
{
@ -324,16 +324,16 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, clock);
if (cell->type.in("\\LDCP", "\\LDCP_N"))
cell->setPort("\\G", pterm_to_ff_wire);
if (cell->type.in(ID(LDCP), ID(LDCP_N)))
cell->setPort(ID::G, pterm_to_ff_wire);
else
cell->setPort("\\C", pterm_to_ff_wire);
cell->setPort(ID::C, pterm_to_ff_wire);
}
// Buffering FF set/reset. This can only come from either
// a pterm or a bufgsr.
SigBit set;
set = sigmap(cell->getPort("\\PRE")[0]);
set = sigmap(cell->getPort(ID(PRE))[0]);
if (set != SigBit(false))
{
if (!sig_fed_by_pterm[set] && !sig_fed_by_bufgsr[set])
@ -342,12 +342,12 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, set);
cell->setPort("\\PRE", pterm_to_ff_wire);
cell->setPort(ID(PRE), pterm_to_ff_wire);
}
}
SigBit reset;
reset = sigmap(cell->getPort("\\CLR")[0]);
reset = sigmap(cell->getPort(ID::CLR)[0]);
if (reset != SigBit(false))
{
if (!sig_fed_by_pterm[reset] && !sig_fed_by_bufgsr[reset])
@ -356,24 +356,24 @@ struct Coolrunner2FixupPass : public Pass {
auto pterm_to_ff_wire = makeptermbuffer(module, reset);
cell->setPort("\\CLR", pterm_to_ff_wire);
cell->setPort(ID::CLR, pterm_to_ff_wire);
}
}
// Buffering FF clock enable
// FIXME: This doesn't fully fix PTC conflicts
// FIXME: Need to ensure constant enables are optimized out
if (cell->type.in("\\FDCPE", "\\FDCPE_N", "\\FDDCPE"))
if (cell->type.in(ID(FDCPE), ID(FDCPE_N), ID(FDDCPE)))
{
SigBit ce;
ce = sigmap(cell->getPort("\\CE")[0]);
ce = sigmap(cell->getPort(ID(CE))[0]);
if (!sig_fed_by_pterm[ce])
{
log("Buffering clock enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_ff_wire = makeptermbuffer(module, ce);
cell->setPort("\\CE", pterm_to_ff_wire);
cell->setPort(ID(CE), pterm_to_ff_wire);
}
}
}
@ -381,10 +381,10 @@ struct Coolrunner2FixupPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == "\\IOBUFE")
if (cell->type == ID(IOBUFE))
{
// Buffer IOBUFE inputs. This can only be fed from an XOR or FF.
SigBit input = sigmap(cell->getPort("\\I")[0]);
SigBit input = sigmap(cell->getPort(ID::I)[0]);
if ((!sig_fed_by_xor[input] && !sig_fed_by_ff[input]) ||
packed_reg_out[input])
@ -393,22 +393,22 @@ struct Coolrunner2FixupPass : public Pass {
auto xor_to_io_wire = makexorbuffer(module, input, cell->name.c_str());
cell->setPort("\\I", xor_to_io_wire);
cell->setPort(ID::I, xor_to_io_wire);
}
// Buffer IOBUFE enables. This can only be fed from a pterm
// or a bufgts.
if (cell->hasPort("\\E"))
if (cell->hasPort(ID::E))
{
SigBit oe;
oe = sigmap(cell->getPort("\\E")[0]);
oe = sigmap(cell->getPort(ID::E)[0]);
if (!sig_fed_by_pterm[oe] && !sig_fed_by_bufgts[oe])
{
log("Buffering output enable to \"%s\"\n", cell->name.c_str());
auto pterm_to_oe_wire = makeptermbuffer(module, oe);
cell->setPort("\\E", pterm_to_oe_wire);
cell->setPort(ID::E, pterm_to_oe_wire);
}
}
}
@ -422,9 +422,9 @@ struct Coolrunner2FixupPass : public Pass {
dict<SigBit, RTLIL::Cell *> xor_out_to_xor_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\MACROCELL_XOR")
if (cell->type == ID(MACROCELL_XOR))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
xor_out_to_xor_cell[output] = cell;
}
}
@ -433,7 +433,7 @@ struct Coolrunner2FixupPass : public Pass {
pool<SigBit> xor_fanout_once;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ANDTERM")
if (cell->type == ID(ANDTERM))
continue;
for (auto &conn : cell->connections())
@ -456,7 +456,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(xor_cell->name), xor_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_xor_cell->setPort("\\OUT", new_wire);
new_xor_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
xor_fanout_once.insert(wire_in);
@ -473,9 +473,9 @@ struct Coolrunner2FixupPass : public Pass {
dict<SigBit, RTLIL::Cell *> or_out_to_or_cell;
for (auto cell : module->selected_cells())
{
if (cell->type == "\\ORTERM")
if (cell->type == ID(ORTERM))
{
auto output = sigmap(cell->getPort("\\OUT")[0]);
auto output = sigmap(cell->getPort(ID(OUT))[0]);
or_out_to_or_cell[output] = cell;
}
}
@ -504,7 +504,7 @@ struct Coolrunner2FixupPass : public Pass {
module->uniquify(or_cell->name), or_cell);
auto new_wire = module->addWire(
module->uniquify(wire_in.wire->name));
new_or_cell->setPort("\\OUT", new_wire);
new_or_cell->setPort(ID(OUT), new_wire);
cell->setPort(conn.first, new_wire);
}
or_fanout_once.insert(wire_in);

102
techlibs/coolrunner2/coolrunner2_sop.cc
View file

@ -47,7 +47,7 @@ struct Coolrunner2SopPass : public Pass {
dict<SigBit, tuple<SigBit, Cell*>> not_cells;
for (auto cell : module->selected_cells())
{
if (cell->type == "$_NOT_")
if (cell->type == ID($_NOT_))
{
auto not_input = sigmap(cell->getPort(ID::A)[0]);
auto not_output = sigmap(cell->getPort(ID::Y)[0]);
@ -56,43 +56,43 @@ struct Coolrunner2SopPass : public Pass {
}
// Find wires that need to become special product terms
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_no_inv;
dict<SigBit, pool<tuple<Cell*, std::string>>> special_pterms_inv;
dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_no_inv;
dict<SigBit, pool<tuple<Cell*, IdString>>> special_pterms_inv;
for (auto cell : module->selected_cells())
{
if (cell->type.in("\\FDCP", "\\FDCP_N", "\\FDDCP", "\\FTCP", "\\FTCP_N", "\\FTDCP",
"\\FDCPE", "\\FDCPE_N", "\\FDDCPE", "\\LDCP", "\\LDCP_N"))
if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
{
if (cell->hasPort("\\PRE"))
special_pterms_no_inv[sigmap(cell->getPort("\\PRE")[0])].insert(
tuple<Cell*, const char *>(cell, "\\PRE"));
if (cell->hasPort("\\CLR"))
special_pterms_no_inv[sigmap(cell->getPort("\\CLR")[0])].insert(
tuple<Cell*, const char *>(cell, "\\CLR"));
if (cell->hasPort("\\CE"))
special_pterms_no_inv[sigmap(cell->getPort("\\CE")[0])].insert(
tuple<Cell*, const char *>(cell, "\\CE"));
if (cell->hasPort(ID(PRE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(PRE))[0])].insert(
make_tuple(cell, ID(PRE)));
if (cell->hasPort(ID::CLR))
special_pterms_no_inv[sigmap(cell->getPort(ID::CLR)[0])].insert(
make_tuple(cell, ID::CLR));
if (cell->hasPort(ID(CE)))
special_pterms_no_inv[sigmap(cell->getPort(ID(CE))[0])].insert(
make_tuple(cell, ID(CE)));
if (cell->hasPort("\\C"))
special_pterms_inv[sigmap(cell->getPort("\\C")[0])].insert(
tuple<Cell*, const char *>(cell, "\\C"));
if (cell->hasPort("\\G"))
special_pterms_inv[sigmap(cell->getPort("\\G")[0])].insert(
tuple<Cell*, const char *>(cell, "\\G"));
if (cell->hasPort(ID::C))
special_pterms_inv[sigmap(cell->getPort(ID::C)[0])].insert(
make_tuple(cell, ID::C));
if (cell->hasPort(ID::G))
special_pterms_inv[sigmap(cell->getPort(ID::G)[0])].insert(
make_tuple(cell, ID::G));
}
}
// Process $sop cells
for (auto cell : module->selected_cells())
{
if (cell->type == "$sop")
if (cell->type == ID($sop))
{
// Read the inputs/outputs/parameters of the $sop cell
auto sop_inputs = sigmap(cell->getPort(ID::A));
auto sop_output = sigmap(cell->getPort(ID::Y))[0];
auto sop_depth = cell->getParam("\\DEPTH").as_int();
auto sop_width = cell->getParam("\\WIDTH").as_int();
auto sop_table = cell->getParam("\\TABLE");
auto sop_depth = cell->getParam(ID::DEPTH).as_int();
auto sop_width = cell->getParam(ID::WIDTH).as_int();
auto sop_table = cell->getParam(ID::TABLE);
auto sop_output_wire_name = sop_output.wire->name.c_str();
@ -139,12 +139,12 @@ struct Coolrunner2SopPass : public Pass {
// Construct the cell
auto and_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_AND%d", sop_output_wire_name, i)),
"\\ANDTERM");
and_cell->setParam("\\TRUE_INP", GetSize(and_in_true));
and_cell->setParam("\\COMP_INP", GetSize(and_in_comp));
and_cell->setPort("\\OUT", and_out);
and_cell->setPort("\\IN", and_in_true);
and_cell->setPort("\\IN_B", and_in_comp);
ID(ANDTERM));
and_cell->setParam(ID(TRUE_INP), GetSize(and_in_true));
and_cell->setParam(ID(COMP_INP), GetSize(and_in_comp));
and_cell->setPort(ID(OUT), and_out);
and_cell->setPort(ID(IN), and_in_true);
and_cell->setPort(ID(IN_B), and_in_comp);
}
if (sop_depth == 1)
@ -152,17 +152,17 @@ struct Coolrunner2SopPass : public Pass {
// If there is only one term, don't construct an OR cell. Directly construct the XOR gate
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_PTC", *intermed_wires.begin());
xor_cell->setPort("\\OUT", sop_output);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_PTC), *intermed_wires.begin());
xor_cell->setPort(ID(OUT), sop_output);
// Special P-term handling
if (is_special_pterm)
{
// Can always connect the P-term directly if it's going
// into something invert-capable
for (auto x : special_pterms_inv[sop_output])
for (const auto &x : special_pterms_inv[sop_output])
{
std::get<0>(x)->setPort(std::get<1>(x), *intermed_wires.begin());
@ -170,14 +170,14 @@ struct Coolrunner2SopPass : public Pass {
if (has_invert)
{
auto cell = std::get<0>(x);
if (cell->type == "\\FDCP") cell->type = "\\FDCP_N";
else if (cell->type == "\\FDCP_N") cell->type = "\\FDCP";
else if (cell->type == "\\FTCP") cell->type = "\\FTCP_N";
else if (cell->type == "\\FTCP_N") cell->type = "\\FTCP";
else if (cell->type == "\\FDCPE") cell->type = "\\FDCPE_N";
else if (cell->type == "\\FDCPE_N") cell->type = "\\FDCPE";
else if (cell->type == "\\LDCP") cell->type = "\\LDCP_N";
else if (cell->type == "\\LDCP_N") cell->type = "\\LDCP";
if (cell->type == ID(FDCP)) cell->type = ID(FDCP_N);
else if (cell->type == ID(FDCP_N)) cell->type = ID(FDCP);
else if (cell->type == ID(FTCP)) cell->type = ID(FTCP_N);
else if (cell->type == ID(FTCP_N)) cell->type = ID(FTCP);
else if (cell->type == ID(FDCPE)) cell->type = ID(FDCPE_N);
else if (cell->type == ID(FDCPE_N)) cell->type = ID(FDCPE);
else if (cell->type == ID(LDCP)) cell->type = ID(LDCP_N);
else if (cell->type == ID(LDCP_N)) cell->type = ID(LDCP);
else log_assert(!"Internal error! Bad cell type!");
}
}
@ -203,18 +203,18 @@ struct Coolrunner2SopPass : public Pass {
// Construct the OR cell
auto or_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_OR", sop_output_wire_name)),
"\\ORTERM");
or_cell->setParam("\\WIDTH", sop_depth);
or_cell->setPort("\\IN", intermed_wires);
or_cell->setPort("\\OUT", or_to_xor_wire);
ID(ORTERM));
or_cell->setParam(ID::WIDTH, sop_depth);
or_cell->setPort(ID(IN), intermed_wires);
or_cell->setPort(ID(OUT), or_to_xor_wire);
// Construct the XOR cell
auto xor_cell = module->addCell(
module->uniquify(stringf("$xc2sop$%s_XOR", sop_output_wire_name)),
"\\MACROCELL_XOR");
xor_cell->setParam("\\INVERT_OUT", has_invert);
xor_cell->setPort("\\IN_ORTERM", or_to_xor_wire);
xor_cell->setPort("\\OUT", sop_output);
ID(MACROCELL_XOR));
xor_cell->setParam(ID(INVERT_OUT), has_invert);
xor_cell->setPort(ID(IN_ORTERM), or_to_xor_wire);
xor_cell->setPort(ID(OUT), sop_output);
}
// Finally, remove the $sop cell