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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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24
techlibs/anlogic/anlogic_eqn.cc
View file

@ -74,34 +74,34 @@ struct AnlogicEqnPass : public Pass {
{
for (auto cell : module->selected_cells())
{
if (cell->type == "\\AL_MAP_LUT1")
if (cell->type == ID(AL_MAP_LUT1))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),1));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),1));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT2")
if (cell->type == ID(AL_MAP_LUT2))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),2));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),2));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT3")
if (cell->type == ID(AL_MAP_LUT3))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),3));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),3));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT4")
if (cell->type == ID(AL_MAP_LUT4))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),4));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),4));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT5")
if (cell->type == ID(AL_MAP_LUT5))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),5));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),5));
cnt++;
}
if (cell->type == "\\AL_MAP_LUT6")
if (cell->type == ID(AL_MAP_LUT6))
{
cell->setParam("\\EQN", init2eqn(cell->getParam("\\INIT"),6));
cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT),6));
cnt++;
}
}

38
techlibs/anlogic/anlogic_fixcarry.cc
View file

@ -39,13 +39,13 @@ static void fix_carry_chain(Module *module)
for (auto cell : module->cells())
{
if (cell->type == "\\AL_MAP_ADDER") {
if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
if (bit_i0 == State::S0 && bit_i1== State::S0) {
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigSpec o = cell->getPort("\\o");
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigSpec o = cell->getPort(ID(o));
if (GetSize(o) == 2) {
SigBit bit_o = o[0];
ci_bits.insert(bit_ci);
@ -57,11 +57,11 @@ static void fix_carry_chain(Module *module)
vector<Cell*> adders_to_fix_cells;
for (auto cell : module->cells())
{
if (cell->type == "\\AL_MAP_ADDER") {
if (cell->getParam("\\ALUTYPE") != Const("ADD")) continue;
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigBit bit_i0 = get_bit_or_zero(cell->getPort("\\a"));
SigBit bit_i1 = get_bit_or_zero(cell->getPort("\\b"));
if (cell->type == ID(AL_MAP_ADDER)) {
if (cell->getParam(ID(ALUTYPE)) != Const("ADD")) continue;
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit bit_i0 = get_bit_or_zero(cell->getPort(ID(a)));
SigBit bit_i1 = get_bit_or_zero(cell->getPort(ID(b)));
SigBit canonical_bit = sigmap(bit_ci);
if (!ci_bits.count(canonical_bit))
continue;
@ -75,23 +75,23 @@ static void fix_carry_chain(Module *module)
for (auto cell : adders_to_fix_cells)
{
SigBit bit_ci = get_bit_or_zero(cell->getPort("\\c"));
SigBit bit_ci = get_bit_or_zero(cell->getPort(ID(c)));
SigBit canonical_bit = sigmap(bit_ci);
auto bit = mapping_bits.at(canonical_bit);
log("Fixing %s cell named %s breaking carry chain.\n", log_id(cell->type), log_id(cell));
Cell *c = module->addCell(NEW_ID, "\\AL_MAP_ADDER");
Cell *c = module->addCell(NEW_ID, ID(AL_MAP_ADDER));
SigBit new_bit = module->addWire(NEW_ID);
SigBit dummy_bit = module->addWire(NEW_ID);
SigSpec bits;
bits.append(dummy_bit);
bits.append(new_bit);
c->setParam("\\ALUTYPE", Const("ADD_CARRY"));
c->setPort("\\a", bit);
c->setPort("\\b", State::S0);
c->setPort("\\c", State::S0);
c->setPort("\\o", bits);
c->setParam(ID(ALUTYPE), Const("ADD_CARRY"));
c->setPort(ID(a), bit);
c->setPort(ID(b), State::S0);
c->setPort(ID(c), State::S0);
c->setPort(ID(o), bits);
cell->setPort("\\c", new_bit);
cell->setPort(ID(c), new_bit);
}
}