3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-29 15:37:59 +00:00

kernel: big fat patch to use more ID::*, otherwise ID(*)

This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions

View file

@ -262,7 +262,7 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
for (auto port : {ID::A, ID::B, ID::C, ID::D}) {
if (!cell->hasPort(port))
continue;
auto bit = sigmap(SigBit(cell->getPort(port)));
@ -395,18 +395,18 @@ struct ExtractFaWorker
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), 1);
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
@ -501,18 +501,18 @@ struct ExtractFaWorker
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), 1);
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), State::S0);
cell->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
}