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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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148
passes/techmap/abc.cc
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@ -170,7 +170,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
{
if (clk_polarity != (cell->type == ID($_DFF_P_)))
return;
if (clk_sig != assign_map(cell->getPort(ID(C))))
if (clk_sig != assign_map(cell->getPort(ID::C)))
return;
if (GetSize(en_sig) != 0)
return;
@ -183,17 +183,17 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
return;
if (en_polarity != cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_)))
return;
if (clk_sig != assign_map(cell->getPort(ID(C))))
if (clk_sig != assign_map(cell->getPort(ID::C)))
return;
if (en_sig != assign_map(cell->getPort(ID(E))))
if (en_sig != assign_map(cell->getPort(ID::E)))
return;
goto matching_dff;
}
if (0) {
matching_dff:
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
if (keepff)
for (auto &c : sig_q.chunks())
@ -263,7 +263,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID(S));
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
@ -285,7 +285,7 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID(C));
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
@ -307,8 +307,8 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID(C));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
assign_map.apply(sig_a);
@ -1032,9 +1032,9 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
RTLIL::Wire *w = it.second;
RTLIL::Wire *orig_wire = nullptr;
RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
if (orig_wire != nullptr && orig_wire->attributes.count(ID(src)))
wire->attributes[ID(src)] = orig_wire->attributes[ID(src)];
if (markgroups) wire->attributes[ID(abcgroup)] = map_autoidx;
if (orig_wire != nullptr && orig_wire->attributes.count(ID::src))
wire->attributes[ID::src] = orig_wire->attributes[ID::src];
if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx;
design->select(module, wire);
}
@ -1060,7 +1060,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
if (c->type == ID(NOT)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_NOT_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
@ -1068,7 +1068,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
if (c->type.in(ID(AND), ID(OR), ID(XOR), ID(NAND), ID(NOR), ID(XNOR), ID(ANDNOT), ID(ORNOT))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
@ -1077,89 +1077,89 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
if (c->type.in(ID(MUX), ID(NMUX))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX4)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX4_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX8)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX8_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)]));
cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)]));
cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)]));
cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)]));
cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type == ID(MUX16)) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), ID($_MUX16_));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(E), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(E)).as_wire()->name)]));
cell->setPort(ID(F), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(F)).as_wire()->name)]));
cell->setPort(ID(G), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(G)).as_wire()->name)]));
cell->setPort(ID(H), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(H)).as_wire()->name)]));
cell->setPort(ID(I), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(I)).as_wire()->name)]));
cell->setPort(ID(J), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(J)).as_wire()->name)]));
cell->setPort(ID(K), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(K)).as_wire()->name)]));
cell->setPort(ID(L), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(L)).as_wire()->name)]));
cell->setPort(ID(M), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(M)).as_wire()->name)]));
cell->setPort(ID(N), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(N)).as_wire()->name)]));
cell->setPort(ID(O), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(O)).as_wire()->name)]));
cell->setPort(ID(P), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(P)).as_wire()->name)]));
cell->setPort(ID(S), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(S)).as_wire()->name)]));
cell->setPort(ID(T), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(T)).as_wire()->name)]));
cell->setPort(ID(U), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(U)).as_wire()->name)]));
cell->setPort(ID(V), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(V)).as_wire()->name)]));
cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::E, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::E).as_wire()->name)]));
cell->setPort(ID::F, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::F).as_wire()->name)]));
cell->setPort(ID::G, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::G).as_wire()->name)]));
cell->setPort(ID::H, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::H).as_wire()->name)]));
cell->setPort(ID::I, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::I).as_wire()->name)]));
cell->setPort(ID::J, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::J).as_wire()->name)]));
cell->setPort(ID::K, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::K).as_wire()->name)]));
cell->setPort(ID::L, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::L).as_wire()->name)]));
cell->setPort(ID::M, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::M).as_wire()->name)]));
cell->setPort(ID::N, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::N).as_wire()->name)]));
cell->setPort(ID::O, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::O).as_wire()->name)]));
cell->setPort(ID::P, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::P).as_wire()->name)]));
cell->setPort(ID::S, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::S).as_wire()->name)]));
cell->setPort(ID::T, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::T).as_wire()->name)]));
cell->setPort(ID::U, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::U).as_wire()->name)]));
cell->setPort(ID::V, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::V).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI3), ID(OAI3))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
}
if (c->type.in(ID(AOI4), ID(OAI4))) {
RTLIL::Cell *cell = module->addCell(remap_name(c->name), stringf("$_%s_", c->type.c_str()+1));
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::A, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)]));
cell->setPort(ID::B, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::B).as_wire()->name)]));
cell->setPort(ID(C), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(C)).as_wire()->name)]));
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID::C, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::C).as_wire()->name)]));
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::Y, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)]));
design->select(module, cell);
continue;
@ -1172,12 +1172,12 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
cell->setPort(ID(E), en_sig);
cell->setPort(ID::E, en_sig);
}
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
cell->setPort(ID(C), clk_sig);
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)]));
cell->setPort(ID::C, clk_sig);
design->select(module, cell);
continue;
}
@ -1201,17 +1201,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
} else {
log_assert(en_sig.size() == 1);
cell = module->addCell(remap_name(c->name), stringf("$_DFFE_%c%c_", clk_polarity ? 'P' : 'N', en_polarity ? 'P' : 'N'));
cell->setPort(ID(E), en_sig);
cell->setPort(ID::E, en_sig);
}
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
cell->setPort(ID(D), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(D)).as_wire()->name)]));
cell->setPort(ID(Q), RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID(Q)).as_wire()->name)]));
cell->setPort(ID(C), clk_sig);
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->setPort(ID::D, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::D).as_wire()->name)]));
cell->setPort(ID::Q, RTLIL::SigSpec(module->wires_[remap_name(c->getPort(ID::Q).as_wire()->name)]));
cell->setPort(ID::C, clk_sig);
design->select(module, cell);
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID(LUT)).as_int() == 2) {
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wires_[remap_name(c->getPort(ID::A).as_wire()->name)];
SigSpec my_y = module->wires_[remap_name(c->getPort(ID::Y).as_wire()->name)];
module->connect(my_y, my_a);
@ -1219,7 +1219,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
}
RTLIL::Cell *cell = module->addCell(remap_name(c->name), c->type);
if (markgroups) cell->attributes[ID(abcgroup)] = map_autoidx;
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
cell->parameters = c->parameters;
for (auto &conn : c->connections()) {
RTLIL::SigSpec newsig;
@ -1244,10 +1244,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
if (recover_init)
for (auto wire : mapped_mod->wires()) {
if (wire->attributes.count(ID(init))) {
if (wire->attributes.count(ID::init)) {
Wire *w = module->wires_[remap_name(wire->name)];
log_assert(w->attributes.count(ID(init)) == 0);
w->attributes[ID(init)] = wire->attributes.at(ID(init));
log_assert(w->attributes.count(ID::init) == 0);
w->attributes[ID::init] = wire->attributes.at(ID::init);
}
}
@ -1869,9 +1869,9 @@ struct AbcPass : public Pass {
signal_init.clear();
for (Wire *wire : mod->wires())
if (wire->attributes.count(ID(init))) {
if (wire->attributes.count(ID::init)) {
SigSpec initsig = assign_map(wire);
Const initval = wire->attributes.at(ID(init));
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
switch (initval[i]) {
case State::S0:
@ -1930,14 +1930,14 @@ struct AbcPass : public Pass {
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
{
key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
key = clkdomain_t(cell->type == ID($_DFF_P_), assign_map(cell->getPort(ID::C)), true, RTLIL::SigSpec());
}
else
if (cell->type.in(ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_)))
{
bool this_clk_pol = cell->type.in(ID($_DFFE_PN_), ID($_DFFE_PP_));
bool this_en_pol = cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, assign_map(cell->getPort(ID(E))));
key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID::C)), this_en_pol, assign_map(cell->getPort(ID::E)));
}
else
continue;

2
passes/techmap/abc9.cc
View file

@ -318,7 +318,7 @@ struct Abc9Pass : public ScriptPass
log("Skipping module %s as it contains processes.\n", log_id(mod));
continue;
}
log_assert(!mod->attributes.count(ID(abc9_box_id)));
log_assert(!mod->attributes.count(ID::abc9_box_id));
log_push();
active_design->selection().select(mod);

106
passes/techmap/abc9_ops.cc
View file

@ -41,8 +41,8 @@ void check(RTLIL::Design *design)
if (m->name.begins_with("$paramod"))
continue;
auto flop = m->get_bool_attribute(ID(abc9_flop));
auto it = m->attributes.find(ID(abc9_box_id));
auto flop = m->get_bool_attribute(ID::abc9_flop);
auto it = m->attributes.find(ID::abc9_box_id);
if (!flop) {
if (it == m->attributes.end())
continue;
@ -59,7 +59,7 @@ void check(RTLIL::Design *design)
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
if (w->get_bool_attribute(ID::abc9_carry)) {
if (w->port_input) {
if (carry_in != IdString())
log_error("Module '%s' contains more than one (* abc9_carry *) input port.\n", log_id(m));
@ -99,7 +99,7 @@ void mark_scc(RTLIL::Module *module)
// write_xaiger to break this wire into PI and POs)
pool<RTLIL::Const> ids_seen;
for (auto cell : module->cells()) {
auto it = cell->attributes.find(ID(abc9_scc_id));
auto it = cell->attributes.find(ID::abc9_scc_id);
if (it == cell->attributes.end())
continue;
auto id = it->second;
@ -111,7 +111,7 @@ void mark_scc(RTLIL::Module *module)
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
w->set_bool_attribute(ID(abc9_scc));
w->set_bool_attribute(ID::abc9_scc);
module->connect(w, c.second);
c.second = w;
}
@ -130,7 +130,7 @@ void prep_dff(RTLIL::Module *module)
dict<clkdomain_t, int> clk_to_mergeability;
for (auto cell : module->cells()) {
if (cell->type != "$__ABC9_FF_")
if (cell->type != ID($__ABC9_FF_))
continue;
Wire *abc9_clock_wire = module->wire(stringf("%s.clock", cell->name.c_str()));
@ -141,7 +141,7 @@ void prep_dff(RTLIL::Module *module)
clkdomain_t key(abc9_clock);
auto r = clk_to_mergeability.insert(std::make_pair(abc9_clock, clk_to_mergeability.size() + 1));
auto r2 = cell->attributes.insert(ID(abc9_mergeability));;
auto r2 = cell->attributes.insert(ID::abc9_mergeability);
log_assert(r2.second);
r2.first->second = r.first->second;
}
@ -152,20 +152,20 @@ void prep_dff(RTLIL::Module *module)
dict<SigSpec, SigSpec> replace;
for (auto cell : holes_module->cells().to_vector()) {
if (!cell->type.in("$_DFF_N_", "$_DFF_NN0_", "$_DFF_NN1_", "$_DFF_NP0_", "$_DFF_NP1_",
"$_DFF_P_", "$_DFF_PN0_", "$_DFF_PN1", "$_DFF_PP0_", "$_DFF_PP1_"))
if (!cell->type.in(ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1), ID($_DFF_PP0_), ID($_DFF_PP1_)))
continue;
SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q");
SigBit D = cell->getPort(ID::D);
SigBit Q = cell->getPort(ID::Q);
// Emulate async control embedded inside $_DFF_* cell with mux in front of D
if (cell->type.in("$_DFF_NN0_", "$_DFF_PN0_"))
D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NN1_", "$_DFF_PN1_"))
D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP0_", "$_DFF_PP0_"))
D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort("\\R"));
else if (cell->type.in("$_DFF_NP1_", "$_DFF_PP1_"))
D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort("\\R"));
if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_PN0_)))
D = holes_module->MuxGate(NEW_ID, State::S0, D, cell->getPort(ID::R));
else if (cell->type.in(ID($_DFF_NN1_), ID($_DFF_PN1_)))
D = holes_module->MuxGate(NEW_ID, State::S1, D, cell->getPort(ID::R));
else if (cell->type.in(ID($_DFF_NP0_), ID($_DFF_PP0_)))
D = holes_module->MuxGate(NEW_ID, D, State::S0, cell->getPort(ID::R));
else if (cell->type.in(ID($_DFF_NP1_), ID($_DFF_PP1_)))
D = holes_module->MuxGate(NEW_ID, D, State::S1, cell->getPort(ID::R));
// Remove the $_DFF_* cell from what needs to be a combinatorial box
holes_module->remove(cell);
Wire *port;
@ -208,17 +208,17 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
dict<IdString, std::vector<IdString>> box_ports;
for (auto cell : module->cells()) {
if (cell->type == "$__ABC9_FF_")
if (cell->type == ID($__ABC9_FF_))
continue;
if (cell->has_keep_attr())
continue;
auto inst_module = module->design->module(cell->type);
bool abc9_flop = inst_module && inst_module->get_bool_attribute("\\abc9_flop");
bool abc9_flop = inst_module && inst_module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop && !dff)
continue;
if ((inst_module && inst_module->get_bool_attribute("\\abc9_box")) || abc9_flop) {
if ((inst_module && inst_module->get_bool_attribute(ID::abc9_box)) || abc9_flop) {
auto r = box_ports.insert(cell->type);
if (r.second) {
// Make carry in the last PI, and carry out the last PO
@ -227,7 +227,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (const auto &port_name : inst_module->ports) {
auto w = inst_module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
@ -289,7 +289,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
RTLIL::Module *holes_module = design->addModule(stringf("%s$holes", module->name.c_str()));
log_assert(holes_module);
holes_module->set_bool_attribute("\\abc9_holes");
holes_module->set_bool_attribute(ID::abc9_holes);
dict<IdString, Cell*> cell_cache;
TimingInfo timing;
@ -300,10 +300,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
log_assert(cell);
RTLIL::Module* box_module = design->module(cell->type);
if (!box_module || (!box_module->get_bool_attribute("\\abc9_box") && !box_module->get_bool_attribute("\\abc9_flop")))
if (!box_module || (!box_module->get_bool_attribute(ID::abc9_box) && !box_module->get_bool_attribute(ID::abc9_flop)))
continue;
cell->attributes["\\abc9_box_seq"] = box_count++;
cell->attributes[ID::abc9_box_seq] = box_count++;
IdString derived_type = box_module->derive(design, cell->parameters);
box_module = design->module(derived_type);
@ -314,7 +314,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc");
if (box_module->get_bool_attribute("\\whitebox")) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(cell->name, derived_type);
if (box_module->has_processes())
@ -345,7 +345,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
// For flops only, create an extra 1-bit input that drives a new wire
// called "<cell>.abc9_ff.Q" that is used below
if (box_module->get_bool_attribute("\\abc9_flop")) {
if (box_module->get_bool_attribute(ID::abc9_flop)) {
box_inputs++;
Wire *holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
if (!holes_wire) {
@ -402,13 +402,13 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
continue;
if (!inst_module->get_blackbox_attribute())
continue;
if (inst_module->attributes.count(ID(abc9_box)))
if (inst_module->attributes.count(ID::abc9_box))
continue;
IdString derived_type = inst_module->derive(design, cell->parameters);
inst_module = design->module(derived_type);
log_assert(inst_module);
if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) {
if (dff_mode && inst_module->get_bool_attribute(ID::abc9_flop)) {
flops.insert(inst_module);
continue; // do not add $__ABC9_DELAY boxes to flops
// as delays will be captured in the flop box
@ -451,9 +451,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
}
#endif
auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY));
box->setPort(ID(I), conn.second[i]);
box->setPort(ID(O), O[i]);
box->setParam(ID(DELAY), d);
box->setPort(ID::I, conn.second[i]);
box->setPort(ID::O, O[i]);
box->setParam(ID::DELAY, d);
conn.second[i] = O[i];
}
}
@ -466,7 +466,7 @@ void prep_lut(RTLIL::Design *design, int maxlut)
std::vector<std::tuple<int, IdString, int, std::vector<int>>> table;
for (auto module : design->modules()) {
auto it = module->attributes.find(ID(abc9_lut));
auto it = module->attributes.find(ID::abc9_lut);
if (it == module->attributes.end())
continue;
@ -527,7 +527,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
std::stringstream ss;
int abc9_box_id = 1;
for (auto module : design->modules()) {
auto it = module->attributes.find(ID(abc9_box_id));
auto it = module->attributes.find(ID::abc9_box_id);
if (it == module->attributes.end())
continue;
abc9_box_id = std::max(abc9_box_id, it->second.as_int());
@ -535,9 +535,9 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
dict<IdString,std::vector<IdString>> box_ports;
for (auto module : design->modules()) {
auto abc9_flop = module->get_bool_attribute(ID(abc9_flop));
auto abc9_flop = module->get_bool_attribute(ID::abc9_flop);
if (abc9_flop) {
auto r = module->attributes.insert(ID(abc9_box_id));
auto r = module->attributes.insert(ID::abc9_box_id);
if (!r.second)
continue;
r.first->second = abc9_box_id++;
@ -604,10 +604,10 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
}
}
else {
if (!module->attributes.erase(ID(abc9_box)))
if (!module->attributes.erase(ID::abc9_box))
continue;
auto r = module->attributes.insert(ID(abc9_box_id));
auto r = module->attributes.insert(ID::abc9_box_id);
if (!r.second)
continue;
r.first->second = abc9_box_id++;
@ -621,7 +621,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
for (const auto &port_name : module->ports) {
auto w = module->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
@ -650,7 +650,7 @@ void prep_box(RTLIL::Design *design, bool dff_mode)
outputs.emplace_back(wire, i);
}
ss << log_id(module) << " " << module->attributes.at(ID(abc9_box_id)).as_int();
ss << log_id(module) << " " << module->attributes.at(ID::abc9_box_id).as_int();
ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0");
ss << " " << GetSize(inputs) << " " << GetSize(outputs) << std::endl;
@ -727,7 +727,7 @@ void reintegrate(RTLIL::Module *module)
dict<IdString,std::vector<IdString>> box_ports;
for (auto m : design->modules()) {
if (!m->attributes.count(ID(abc9_box_id)))
if (!m->attributes.count(ID::abc9_box_id))
continue;
auto r = box_ports.insert(m->name);
@ -740,7 +740,7 @@ void reintegrate(RTLIL::Module *module)
for (const auto &port_name : m->ports) {
auto w = m->wire(port_name);
log_assert(w);
if (w->get_bool_attribute("\\abc9_carry")) {
if (w->get_bool_attribute(ID::abc9_carry)) {
log_assert(w->port_input != w->port_output);
if (w->port_input)
carry_in = port_name;
@ -763,7 +763,7 @@ void reintegrate(RTLIL::Module *module)
continue;
if (cell->type.in(ID($_AND_), ID($_NOT_), ID($__ABC9_FF_)))
module->remove(cell);
else if (cell->attributes.erase("\\abc9_box_seq"))
else if (cell->attributes.erase(ID::abc9_box_seq))
boxes.emplace_back(cell);
}
@ -874,7 +874,7 @@ void reintegrate(RTLIL::Module *module)
IdString derived_type = box_module->derive(design, existing_cell->parameters);
RTLIL::Module* derived_module = design->module(derived_type);
log_assert(derived_module);
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at("\\abc9_box_id").as_int()));
log_assert(mapped_cell->type == stringf("$__boxid%d", derived_module->attributes.at(ID::abc9_box_id).as_int()));
mapped_cell->type = existing_cell->type;
RTLIL::Cell *cell = module->addCell(remap_name(mapped_cell->name), mapped_cell->type);
@ -882,16 +882,16 @@ void reintegrate(RTLIL::Module *module)
cell->attributes = existing_cell->attributes;
module->swap_names(cell, existing_cell);
auto jt = mapped_cell->connections_.find("\\i");
auto jt = mapped_cell->connections_.find(ID(i));
log_assert(jt != mapped_cell->connections_.end());
SigSpec inputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
jt = mapped_cell->connections_.find("\\o");
jt = mapped_cell->connections_.find(ID(o));
log_assert(jt != mapped_cell->connections_.end());
SigSpec outputs = std::move(jt->second);
mapped_cell->connections_.erase(jt);
auto abc9_flop = box_module->attributes.count("\\abc9_flop");
auto abc9_flop = box_module->attributes.count(ID::abc9_flop);
if (!abc9_flop) {
for (const auto &i : inputs)
bit_users[i].insert(mapped_cell->name);
@ -966,7 +966,7 @@ void reintegrate(RTLIL::Module *module)
RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
RTLIL::Wire *wire = module->wire(port);
log_assert(wire);
wire->attributes.erase(ID(abc9_scc));
wire->attributes.erase(ID::abc9_scc);
RTLIL::Wire *remap_wire = module->wire(remap_name(port));
RTLIL::SigSpec signal(wire, 0, GetSize(remap_wire));
@ -1033,7 +1033,7 @@ void reintegrate(RTLIL::Module *module)
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID::A);
RTLIL::Const mask = sink_cell->getParam(ID(LUT));
RTLIL::Const mask = sink_cell->getParam(ID::LUT);
int index = 0;
for (; index < GetSize(A); index++)
if (A[index] == a_bit)
@ -1047,7 +1047,7 @@ void reintegrate(RTLIL::Module *module)
}
A[index] = y_bit;
sink_cell->setPort(ID::A, A);
sink_cell->setParam(ID(LUT), mask);
sink_cell->setParam(ID::LUT, mask);
}
// Since we have rewritten all sinks (which we know
@ -1056,7 +1056,7 @@ void reintegrate(RTLIL::Module *module)
// that the original driving LUT will become dangling
// and get cleaned away
clone_lut:
driver_mask = driver_lut->getParam(ID(LUT));
driver_mask = driver_lut->getParam(ID::LUT);
for (auto &b : driver_mask.bits) {
if (b == RTLIL::State::S0) b = RTLIL::State::S1;
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
@ -1228,7 +1228,7 @@ struct Abc9OpsPass : public Pass {
prep_box(design, dff_mode);
for (auto mod : design->selected_modules()) {
if (mod->get_bool_attribute("\\abc9_holes"))
if (mod->get_bool_attribute(ID::abc9_holes))
continue;
if (mod->processes.size() > 0) {

26
passes/techmap/alumacc.cc
View file

@ -72,7 +72,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID(X)), false, alu_cell->get_src_attribute());
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->get_src_attribute());
return cached_eq;
}
@ -84,7 +84,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_cf() {
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID(CO));
cached_cf = alu_cell->getPort(ID::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
}
@ -93,7 +93,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_of() {
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort(ID(CO)), alu_cell->getPort(ID(CI))};
cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
@ -154,7 +154,7 @@ struct AlumaccWorker
if (cell->type.in(ID($pos), ID($neg)))
{
new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = cell->type == ID($neg);
n->macc.ports.push_back(new_port);
}
@ -162,12 +162,12 @@ struct AlumaccWorker
if (cell->type.in(ID($add), ID($sub)))
{
new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
new_port.in_a = sigmap(cell->getPort(ID::B));
new_port.is_signed = cell->getParam(ID(B_SIGNED)).as_bool();
new_port.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
new_port.do_subtract = cell->type == ID($sub);
n->macc.ports.push_back(new_port);
}
@ -176,7 +176,7 @@ struct AlumaccWorker
{
new_port.in_a = sigmap(cell->getPort(ID::A));
new_port.in_b = sigmap(cell->getPort(ID::B));
new_port.is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
new_port.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_port.do_subtract = false;
n->macc.ports.push_back(new_port);
}
@ -399,7 +399,7 @@ struct AlumaccWorker
bool cmp_less = cell->type.in(ID($lt), ID($le));
bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
@ -439,7 +439,7 @@ struct AlumaccWorker
for (auto cell : eq_cells)
{
bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
@ -495,11 +495,11 @@ struct AlumaccWorker
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);
n->alu_cell->setPort(ID(CI), GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID(BI), n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID(X), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID(CO), module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)

10
passes/techmap/clkbufmap.cc
View file

@ -118,8 +118,6 @@ struct ClkbufmapPass : public Pass {
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_out;
dict<pair<IdString, pair<IdString, int>>, pair<IdString, int>> inv_ports_in;
IdString clkbuf_inhibit("\\clkbuf_inhibit");
// Process submodules before module using them.
std::vector<Module *> modules_sorted;
pool<Module *> modules_processed;
@ -131,13 +129,13 @@ struct ClkbufmapPass : public Pass {
if (module->get_blackbox_attribute()) {
for (auto port : module->ports) {
auto wire = module->wire(port);
if (wire->get_bool_attribute("\\clkbuf_driver"))
if (wire->get_bool_attribute(ID::clkbuf_driver))
for (int i = 0; i < GetSize(wire); i++)
buf_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
if (wire->get_bool_attribute("\\clkbuf_sink"))
if (wire->get_bool_attribute(ID::clkbuf_sink))
for (int i = 0; i < GetSize(wire); i++)
sink_ports.insert(make_pair(module->name, make_pair(wire->name, i)));
auto it = wire->attributes.find("\\clkbuf_inv");
auto it = wire->attributes.find(ID::clkbuf_inv);
if (it != wire->attributes.end()) {
IdString in_name = RTLIL::escape_id(it->second.decode_string());
for (int i = 0; i < GetSize(wire); i++) {
@ -217,7 +215,7 @@ struct ClkbufmapPass : public Pass {
if (wire->port_input && wire->port_output)
continue;
bool process_wire = module->selected(wire);
if (!select && wire->get_bool_attribute(clkbuf_inhibit))
if (!select && wire->get_bool_attribute(ID::clkbuf_inhibit))
process_wire = false;
if (!process_wire) {
// This wire is supposed to be bypassed, so make sure we don't buffer it in

40
passes/techmap/dff2dffe.cc
View file

@ -88,7 +88,7 @@ struct Dff2dffeWorker
cell_int_t mux_cell_int = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mux_cell_int.first->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap(mux_cell_int.first->getPort(ID::B));
RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID(S)));
RTLIL::SigSpec sig_s = sigmap(mux_cell_int.first->getPort(ID::S));
int width = GetSize(sig_a), index = mux_cell_int.second;
for (int i = 0; i < GetSize(sig_s); i++)
@ -185,8 +185,8 @@ struct Dff2dffeWorker
void handle_dff_cell(RTLIL::Cell *dff_cell)
{
RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID(D)));
RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID(Q)));
RTLIL::SigSpec sig_d = sigmap(dff_cell->getPort(ID::D));
RTLIL::SigSpec sig_q = sigmap(dff_cell->getPort(ID::Q));
std::map<patterns_t, std::set<int>> grouped_patterns;
std::set<int> remaining_indices;
@ -208,15 +208,15 @@ struct Dff2dffeWorker
}
if (!direct_dict.empty()) {
log(" converting %s cell %s to %s for %s -> %s.\n", log_id(dff_cell->type), log_id(dff_cell), log_id(direct_dict.at(dff_cell->type)), log_signal(new_sig_d), log_signal(new_sig_q));
dff_cell->setPort(ID(E), make_patterns_logic(it.first, true));
dff_cell->setPort(ID::E, make_patterns_logic(it.first, true));
dff_cell->type = direct_dict.at(dff_cell->type);
} else
if (dff_cell->type == ID($dff)) {
RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID(CLK)), make_patterns_logic(it.first, false),
new_sig_d, new_sig_q, dff_cell->getParam(ID(CLK_POLARITY)).as_bool(), true);
RTLIL::Cell *new_cell = module->addDffe(NEW_ID, dff_cell->getPort(ID::CLK), make_patterns_logic(it.first, false),
new_sig_d, new_sig_q, dff_cell->getParam(ID::CLK_POLARITY).as_bool(), true);
log(" created $dffe cell %s for %s -> %s.\n", log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
} else {
RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID(C)), make_patterns_logic(it.first, true),
RTLIL::Cell *new_cell = module->addDffeGate(NEW_ID, dff_cell->getPort(ID::C), make_patterns_logic(it.first, true),
new_sig_d, new_sig_q, dff_cell->type == ID($_DFF_P_), true);
log(" created %s cell %s for %s -> %s.\n", log_id(new_cell->type), log_id(new_cell), log_signal(new_sig_d), log_signal(new_sig_q));
}
@ -235,9 +235,9 @@ struct Dff2dffeWorker
new_sig_d.append(sig_d[i]);
new_sig_q.append(sig_q[i]);
}
dff_cell->setPort(ID(D), new_sig_d);
dff_cell->setPort(ID(Q), new_sig_q);
dff_cell->setParam(ID(WIDTH), GetSize(remaining_indices));
dff_cell->setPort(ID::D, new_sig_d);
dff_cell->setPort(ID::Q, new_sig_q);
dff_cell->setParam(ID::WIDTH, GetSize(remaining_indices));
}
}
@ -361,19 +361,19 @@ struct Dff2dffePass : public Pass {
for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type)
continue;
if (sigmap(cell->getPort(ID(EN))) == sigmap(cell_other->getPort(ID(EN))))
if (sigmap(cell->getPort(ID::EN)) == sigmap(cell_other->getPort(ID::EN)))
ce_use++;
}
if (ce_use >= min_ce_use)
continue;
}
RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID(D))));
mod->addDff(NEW_ID, cell->getPort(ID(CLK)), tmp, cell->getPort(ID(Q)), cell->getParam(ID(CLK_POLARITY)).as_bool());
if (cell->getParam(ID(EN_POLARITY)).as_bool())
mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(EN)), tmp);
RTLIL::SigSpec tmp = mod->addWire(NEW_ID, GetSize(cell->getPort(ID::D)));
mod->addDff(NEW_ID, cell->getPort(ID::CLK), tmp, cell->getPort(ID::Q), cell->getParam(ID::CLK_POLARITY).as_bool());
if (cell->getParam(ID::EN_POLARITY).as_bool())
mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::EN), tmp);
else
mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(EN)), tmp);
mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::EN), tmp);
mod->remove(cell);
continue;
}
@ -383,7 +383,7 @@ struct Dff2dffePass : public Pass {
for (auto cell_other : mod->selected_cells()) {
if (cell_other->type != cell->type)
continue;
if (sigmap(cell->getPort(ID(E))) == sigmap(cell_other->getPort(ID(E))))
if (sigmap(cell->getPort(ID::E)) == sigmap(cell_other->getPort(ID::E)))
ce_use++;
}
if (ce_use >= min_ce_use)
@ -393,11 +393,11 @@ struct Dff2dffePass : public Pass {
bool clk_pol = cell->type.compare(7, 1, "P") == 0;
bool en_pol = cell->type.compare(8, 1, "P") == 0;
RTLIL::SigSpec tmp = mod->addWire(NEW_ID);
mod->addDff(NEW_ID, cell->getPort(ID(C)), tmp, cell->getPort(ID(Q)), clk_pol);
mod->addDff(NEW_ID, cell->getPort(ID::C), tmp, cell->getPort(ID::Q), clk_pol);
if (en_pol)
mod->addMux(NEW_ID, cell->getPort(ID(Q)), cell->getPort(ID(D)), cell->getPort(ID(E)), tmp);
mod->addMux(NEW_ID, cell->getPort(ID::Q), cell->getPort(ID::D), cell->getPort(ID::E), tmp);
else
mod->addMux(NEW_ID, cell->getPort(ID(D)), cell->getPort(ID(Q)), cell->getPort(ID(E)), tmp);
mod->addMux(NEW_ID, cell->getPort(ID::D), cell->getPort(ID::Q), cell->getPort(ID::E), tmp);
mod->remove(cell);
continue;
}

12
passes/techmap/dff2dffs.cc
View file

@ -90,7 +90,7 @@ struct Dff2dffsPass : public Pass {
for (auto cell : ff_cells)
{
SigSpec sig_d = cell->getPort(ID(D));
SigSpec sig_d = cell->getPort(ID::D);
if (GetSize(sig_d) < 1)
continue;
@ -103,7 +103,7 @@ struct Dff2dffsPass : public Pass {
Cell *mux_cell = sr_muxes.at(bit_d);
SigBit bit_a = sigmap(mux_cell->getPort(ID::A));
SigBit bit_b = sigmap(mux_cell->getPort(ID::B));
SigBit bit_s = sigmap(mux_cell->getPort(ID(S)));
SigBit bit_s = sigmap(mux_cell->getPort(ID::S));
SigBit sr_val, sr_sig;
bool invert_sr;
@ -120,9 +120,9 @@ struct Dff2dffsPass : public Pass {
}
if (match_init) {
SigBit bit_q = cell->getPort(ID(Q));
SigBit bit_q = cell->getPort(ID::Q);
if (bit_q.wire) {
auto it = bit_q.wire->attributes.find(ID(init));
auto it = bit_q.wire->attributes.find(ID::init);
if (it != bit_q.wire->attributes.end()) {
auto init_val = it->second[bit_q.offset];
if (init_val == State::S1 && sr_val != State::S1)
@ -155,8 +155,8 @@ struct Dff2dffsPass : public Pass {
else cell->type = ID($__DFFS_PP0_);
}
}
cell->setPort(ID(R), sr_sig);
cell->setPort(ID(D), bit_d);
cell->setPort(ID::R, sr_sig);
cell->setPort(ID::D, bit_d);
}
}
}

10
passes/techmap/dffinit.cc
View file

@ -99,8 +99,8 @@ struct DffinitPass : public Pass {
pool<SigBit> used_bits;
for (auto wire : module->selected_wires()) {
if (wire->attributes.count(ID(init))) {
Const value = wire->attributes.at(ID(init));
if (wire->attributes.count(ID::init)) {
Const value = wire->attributes.at(ID::init);
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i];
@ -161,8 +161,8 @@ struct DffinitPass : public Pass {
}
for (auto wire : module->selected_wires())
if (wire->attributes.count(ID(init))) {
Const &value = wire->attributes.at(ID(init));
if (wire->attributes.count(ID::init)) {
Const &value = wire->attributes.at(ID::init);
bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
@ -173,7 +173,7 @@ struct DffinitPass : public Pass {
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
wire->attributes.erase(ID(init));
wire->attributes.erase(ID::init);
}
}
}

52
passes/techmap/dffsr2dff.cc
View file

@ -27,15 +27,15 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
{
if (cell->type == ID($dffsr))
{
int width = cell->getParam(ID(WIDTH)).as_int();
bool setpol = cell->getParam(ID(SET_POLARITY)).as_bool();
bool clrpol = cell->getParam(ID(CLR_POLARITY)).as_bool();
int width = cell->getParam(ID::WIDTH).as_int();
bool setpol = cell->getParam(ID::SET_POLARITY).as_bool();
bool clrpol = cell->getParam(ID::CLR_POLARITY).as_bool();
SigBit setunused = setpol ? State::S0 : State::S1;
SigBit clrunused = clrpol ? State::S0 : State::S1;
SigSpec setsig = sigmap(cell->getPort(ID(SET)));
SigSpec clrsig = sigmap(cell->getPort(ID(CLR)));
SigSpec setsig = sigmap(cell->getPort(ID::SET));
SigSpec clrsig = sigmap(cell->getPort(ID::CLR));
Const reset_val;
SigSpec setctrl, clrctrl;
@ -78,19 +78,19 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
log("Converting %s cell %s.%s to $adff.\n", log_id(cell->type), log_id(module), log_id(cell));
if (GetSize(setctrl) == 1) {
cell->setPort(ID(ARST), setctrl);
cell->setParam(ID(ARST_POLARITY), setpol);
cell->setPort(ID::ARST, setctrl);
cell->setParam(ID::ARST_POLARITY, setpol);
} else {
cell->setPort(ID(ARST), clrctrl);
cell->setParam(ID(ARST_POLARITY), clrpol);
cell->setPort(ID::ARST, clrctrl);
cell->setParam(ID::ARST_POLARITY, clrpol);
}
cell->type = ID($adff);
cell->unsetPort(ID(SET));
cell->unsetPort(ID(CLR));
cell->setParam(ID(ARST_VALUE), reset_val);
cell->unsetParam(ID(SET_POLARITY));
cell->unsetParam(ID(CLR_POLARITY));
cell->unsetPort(ID::SET);
cell->unsetPort(ID::CLR);
cell->setParam(ID::ARST_VALUE, reset_val);
cell->unsetParam(ID::SET_POLARITY);
cell->unsetParam(ID::CLR_POLARITY);
return;
}
@ -102,8 +102,8 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
char setpol = cell->type.c_str()[9];
char clrpol = cell->type.c_str()[10];
SigBit setbit = sigmap(cell->getPort(ID(S)));
SigBit clrbit = sigmap(cell->getPort(ID(R)));
SigBit setbit = sigmap(cell->getPort(ID::S));
SigBit clrbit = sigmap(cell->getPort(ID::R));
SigBit setunused = setpol == 'P' ? State::S0 : State::S1;
SigBit clrunused = clrpol == 'P' ? State::S0 : State::S1;
@ -112,14 +112,14 @@ void dffsr_worker(SigMap &sigmap, Module *module, Cell *cell)
if (setbit == setunused) {
cell->type = stringf("$_DFF_%c%c0_", clkpol, clrpol);
cell->unsetPort(ID(S));
cell->unsetPort(ID::S);
goto converted_gate;
}
if (clrbit == clrunused) {
cell->type = stringf("$_DFF_%c%c1_", clkpol, setpol);
cell->setPort(ID(R), cell->getPort(ID(S)));
cell->unsetPort(ID(S));
cell->setPort(ID::R, cell->getPort(ID::S));
cell->unsetPort(ID::S);
goto converted_gate;
}
@ -135,9 +135,9 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
{
if (cell->type == ID($adff))
{
bool rstpol = cell->getParam(ID(ARST_POLARITY)).as_bool();
bool rstpol = cell->getParam(ID::ARST_POLARITY).as_bool();
SigBit rstunused = rstpol ? State::S0 : State::S1;
SigSpec rstsig = sigmap(cell->getPort(ID(ARST)));
SigSpec rstsig = sigmap(cell->getPort(ID::ARST));
if (rstsig != rstunused)
return;
@ -145,9 +145,9 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
log("Converting %s cell %s.%s to $dff.\n", log_id(cell->type), log_id(module), log_id(cell));
cell->type = ID($dff);
cell->unsetPort(ID(ARST));
cell->unsetParam(ID(ARST_VALUE));
cell->unsetParam(ID(ARST_POLARITY));
cell->unsetPort(ID::ARST);
cell->unsetParam(ID::ARST_VALUE);
cell->unsetParam(ID::ARST_POLARITY);
return;
}
@ -158,7 +158,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
char clkpol = cell->type.c_str()[6];
char rstpol = cell->type.c_str()[7];
SigBit rstbit = sigmap(cell->getPort(ID(R)));
SigBit rstbit = sigmap(cell->getPort(ID::R));
SigBit rstunused = rstpol == 'P' ? State::S0 : State::S1;
if (rstbit != rstunused)
@ -168,7 +168,7 @@ void adff_worker(SigMap &sigmap, Module *module, Cell *cell)
log("Converting %s cell %s.%s to %s.\n", log_id(cell->type), log_id(module), log_id(cell), log_id(newtype));
cell->type = newtype;
cell->unsetPort(ID(R));
cell->unsetPort(ID::R);
return;
}

62
passes/techmap/extract.cc
View file

@ -58,36 +58,36 @@ public:
return value;
#define param_bool(_n) if (param == _n) return value.as_bool();
param_bool(ID(ARST_POLARITY));
param_bool(ID(A_SIGNED));
param_bool(ID(B_SIGNED));
param_bool(ID(CLK_ENABLE));
param_bool(ID(CLK_POLARITY));
param_bool(ID(CLR_POLARITY));
param_bool(ID(EN_POLARITY));
param_bool(ID(SET_POLARITY));
param_bool(ID(TRANSPARENT));
param_bool(ID::ARST_POLARITY);
param_bool(ID::A_SIGNED);
param_bool(ID::B_SIGNED);
param_bool(ID::CLK_ENABLE);
param_bool(ID::CLK_POLARITY);
param_bool(ID::CLR_POLARITY);
param_bool(ID::EN_POLARITY);
param_bool(ID::SET_POLARITY);
param_bool(ID::TRANSPARENT);
#undef param_bool
#define param_int(_n) if (param == _n) return value.as_int();
param_int(ID(ABITS))
param_int(ID(A_WIDTH))
param_int(ID(B_WIDTH))
param_int(ID(CTRL_IN_WIDTH))
param_int(ID(CTRL_OUT_WIDTH))
param_int(ID(OFFSET))
param_int(ID(PRIORITY))
param_int(ID(RD_PORTS))
param_int(ID(SIZE))
param_int(ID(STATE_BITS))
param_int(ID(STATE_NUM))
param_int(ID(STATE_NUM_LOG2))
param_int(ID(STATE_RST))
param_int(ID(S_WIDTH))
param_int(ID(TRANS_NUM))
param_int(ID(WIDTH))
param_int(ID(WR_PORTS))
param_int(ID(Y_WIDTH))
param_int(ID::ABITS)
param_int(ID::A_WIDTH)
param_int(ID::B_WIDTH)
param_int(ID::CTRL_IN_WIDTH)
param_int(ID::CTRL_OUT_WIDTH)
param_int(ID::OFFSET)
param_int(ID::PRIORITY)
param_int(ID::RD_PORTS)
param_int(ID::SIZE)
param_int(ID::STATE_BITS)
param_int(ID::STATE_NUM)
param_int(ID::STATE_NUM_LOG2)
param_int(ID::STATE_RST)
param_int(ID::S_WIDTH)
param_int(ID::TRANS_NUM)
param_int(ID::WIDTH)
param_int(ID::WR_PORTS)
param_int(ID::Y_WIDTH)
#undef param_int
return value;
@ -341,10 +341,10 @@ RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit:
bool compareSortNeedleList(RTLIL::Module *left, RTLIL::Module *right)
{
int left_idx = 0, right_idx = 0;
if (left->attributes.count(ID(extract_order)) > 0)
left_idx = left->attributes.at(ID(extract_order)).as_int();
if (right->attributes.count(ID(extract_order)) > 0)
right_idx = right->attributes.at(ID(extract_order)).as_int();
if (left->attributes.count(ID::extract_order) > 0)
left_idx = left->attributes.at(ID::extract_order).as_int();
if (right->attributes.count(ID::extract_order) > 0)
right_idx = right->attributes.at(ID::extract_order).as_int();
if (left_idx != right_idx)
return left_idx < right_idx;
return left->name < right->name;

94
passes/techmap/extract_counter.cc
View file

@ -131,23 +131,23 @@ int counter_tryextract(
SigMap& sigmap = index.sigmap;
//Both inputs must be unsigned, so don't extract anything with a signed input
bool a_sign = cell->getParam(ID(A_SIGNED)).as_bool();
bool b_sign = cell->getParam(ID(B_SIGNED)).as_bool();
bool a_sign = cell->getParam(ID::A_SIGNED).as_bool();
bool b_sign = cell->getParam(ID::B_SIGNED).as_bool();
if(a_sign || b_sign)
return 3;
//CO and X must be unconnected (exactly one connection to each port)
if(!is_unconnected(sigmap(cell->getPort(ID(CO))), index))
if(!is_unconnected(sigmap(cell->getPort(ID::CO)), index))
return 7;
if(!is_unconnected(sigmap(cell->getPort(ID(X))), index))
if(!is_unconnected(sigmap(cell->getPort(ID::X)), index))
return 8;
//true if $alu is performing A - B, else A + B
bool alu_is_subtract;
//BI and CI must be both constant 0 or both constant 1 as well
const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID(BI)));
const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID(CI)));
const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID::BI));
const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID::CI));
if(bi_port.is_fully_const() && bi_port.as_int() == 1 &&
ci_port.is_fully_const() && ci_port.as_int() == 1)
{
@ -169,8 +169,8 @@ int counter_tryextract(
if(alu_is_subtract)
{
const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
const int a_width = cell->getParam(ID::A_WIDTH).as_int();
const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
// down, cnt <= cnt - 1
@ -197,8 +197,8 @@ int counter_tryextract(
}
else
{
const int a_width = cell->getParam(ID(A_WIDTH)).as_int();
const int b_width = cell->getParam(ID(B_WIDTH)).as_int();
const int a_width = cell->getParam(ID::A_WIDTH).as_int();
const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A));
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
@ -245,9 +245,9 @@ int counter_tryextract(
//Check if counter is an appropriate size
int count_width;
if (alu_port_use_a)
count_width = cell->getParam(ID(A_WIDTH)).as_int();
count_width = cell->getParam(ID::A_WIDTH).as_int();
else
count_width = cell->getParam(ID(B_WIDTH)).as_int();
count_width = cell->getParam(ID::B_WIDTH).as_int();
extract.width = count_width;
if( (count_width < settings.minwidth) || (count_width > settings.maxwidth) )
return 1;
@ -283,7 +283,7 @@ int counter_tryextract(
//S connection of the mux must come from an inverter if down, eq if up
//(need not be the only load)
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID(S)));
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID::S));
extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
Cell* overflow_cell = NULL;
@ -293,7 +293,7 @@ int counter_tryextract(
continue;
if(!extract.count_is_up && c->type != ID($logic_not))
continue;
if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID(S), true))
if(!is_full_bus(muxsel, index, c, ID::Y, count_mux, ID::S, true))
continue;
overflow_cell = c;
@ -324,17 +324,17 @@ int counter_tryextract(
return 24;
count_reg = *cey_loads.begin();
if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID(D))))
if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID::D)))
return 24;
//Mux should have A driven by count Q, and B by muxy
//if A and B are swapped, CE polarity is inverted
if(sigmap(cemux->getPort(ID::B)) == muxy &&
sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID(Q))))
sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = false;
}
else if(sigmap(cemux->getPort(ID::A)) == muxy &&
sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID(Q))))
sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q)))
{
extract.ce_inverted = true;
}
@ -345,7 +345,7 @@ int counter_tryextract(
//Select of the mux is our clock enable
extract.has_ce = true;
extract.ce = sigmap(cemux->getPort(ID(S)));
extract.ce = sigmap(cemux->getPort(ID::S));
}
else
extract.has_ce = false;
@ -361,10 +361,10 @@ int counter_tryextract(
extract.has_reset = true;
//Check polarity of reset - we may have to add an inverter later on!
extract.rst_inverted = (count_reg->getParam(ID(ARST_POLARITY)).as_int() != 1);
extract.rst_inverted = (count_reg->getParam(ID::ARST_POLARITY).as_int() != 1);
//Verify ARST_VALUE is zero or full scale
int rst_value = count_reg->getParam(ID(ARST_VALUE)).as_int();
int rst_value = count_reg->getParam(ID::ARST_VALUE).as_int();
if(rst_value == 0)
extract.rst_to_max = false;
else if(rst_value == extract.count_value)
@ -373,7 +373,7 @@ int counter_tryextract(
return 23;
//Save the reset
extract.rst = sigmap(count_reg->getPort(ID(ARST)));
extract.rst = sigmap(count_reg->getPort(ID::ARST));
}
//TODO: support synchronous reset
else
@ -386,10 +386,10 @@ int counter_tryextract(
return 16;
if(extract.ce_inverted && !is_full_bus(muxy, index, count_mux, ID::Y, cemux, ID::A))
return 16;
if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID(D)))
if(!is_full_bus(cey, index, cemux, ID::Y, count_reg, ID::D))
return 16;
}
else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID(D)))
else if(!is_full_bus(muxy, index, count_mux, ID::Y, count_reg, ID::D))
return 16;
//TODO: Verify count_reg CLK_POLARITY is 1
@ -397,7 +397,7 @@ int counter_tryextract(
//Register output must have exactly two loads, the inverter and ALU
//(unless we have a parallel output!)
//If we have a clock enable, 3 is OK
const RTLIL::SigSpec qport = count_reg->getPort(ID(Q));
const RTLIL::SigSpec qport = count_reg->getPort(ID::Q);
extract.poutsig = qport;
extract.has_pout = false;
const RTLIL::SigSpec cnout = sigmap(qport);
@ -450,12 +450,12 @@ int counter_tryextract(
}
if(!extract.count_is_up)
{
if(!is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
if(!is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true))
return 18;
}
else
{
if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::A, true))
if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true))
{
// B must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B));
@ -463,7 +463,7 @@ int counter_tryextract(
return 12;
extract.count_value = overflow.as_int();
}
else if(is_full_bus(cnout, index, count_reg, ID(Q), overflow_cell, ID::B, true))
else if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::B, true))
{
// A must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A));
@ -476,21 +476,21 @@ int counter_tryextract(
return 18;
}
}
if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::A, true))
if(alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::A, true))
return 19;
if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID(Q), cell, ID::B, true))
if(!alu_port_use_a && !is_full_bus(cnout, index, count_reg, ID::Q, cell, ID::B, true))
return 19;
//Look up the clock from the register
extract.clk = sigmap(count_reg->getPort(ID(CLK)));
extract.clk = sigmap(count_reg->getPort(ID::CLK));
if(!extract.count_is_up)
{
//Register output net must have an INIT attribute equal to the count value
extract.rwire = cnout.as_wire();
if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end())
return 20;
int rinit = extract.rwire->attributes[ID(init)].as_int();
int rinit = extract.rwire->attributes[ID::init].as_int();
if(rinit != extract.count_value)
return 21;
}
@ -498,9 +498,9 @@ int counter_tryextract(
{
//Register output net must not have an INIT attribute or it must be zero
extract.rwire = cnout.as_wire();
if(extract.rwire->attributes.find(ID(init)) == extract.rwire->attributes.end())
if(extract.rwire->attributes.find(ID::init) == extract.rwire->attributes.end())
return 0;
int rinit = extract.rwire->attributes[ID(init)].as_int();
int rinit = extract.rwire->attributes[ID::init].as_int();
if(rinit != 0)
return 21;
}
@ -534,7 +534,7 @@ void counter_worker(
RTLIL::Wire* port_wire = port.as_wire();
bool force_extract = false;
bool never_extract = false;
string count_reg_src = port_wire->attributes[ID(src)].decode_string().c_str();
string count_reg_src = port_wire->attributes[ID::src].decode_string().c_str();
if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end())
{
pool<string> sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT));
@ -618,16 +618,16 @@ void counter_worker(
//Wipe all of the old connections to the ALU
cell->unsetPort(ID::A);
cell->unsetPort(ID::B);
cell->unsetPort(ID(BI));
cell->unsetPort(ID(CI));
cell->unsetPort(ID(CO));
cell->unsetPort(ID(X));
cell->unsetPort(ID::BI);
cell->unsetPort(ID::CI);
cell->unsetPort(ID::CO);
cell->unsetPort(ID::X);
cell->unsetPort(ID::Y);
cell->unsetParam(ID(A_SIGNED));
cell->unsetParam(ID(A_WIDTH));
cell->unsetParam(ID(B_SIGNED));
cell->unsetParam(ID(B_WIDTH));
cell->unsetParam(ID(Y_WIDTH));
cell->unsetParam(ID::A_SIGNED);
cell->unsetParam(ID::A_WIDTH);
cell->unsetParam(ID::B_SIGNED);
cell->unsetParam(ID::B_WIDTH);
cell->unsetParam(ID::Y_WIDTH);
//Change the cell type
cell->type = ID($__COUNT_);
@ -657,8 +657,8 @@ void counter_worker(
//Hook up other stuff
//cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1));
cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value));
cell->setParam(ID(WIDTH), RTLIL::Const(extract.width));
cell->setPort(ID(CLK), extract.clk);
cell->setParam(ID::WIDTH, RTLIL::Const(extract.width));
cell->setPort(ID::CLK, extract.clk);
cell->setPort(ID(OUT), extract.outsig);
//Hook up clock enable
@ -747,7 +747,7 @@ void counter_worker(
int newbits = ceil(log2(extract.count_value));
if(extract.width != newbits)
{
cell->setParam(ID(WIDTH), RTLIL::Const(newbits));
cell->setParam(ID::WIDTH, RTLIL::Const(newbits));
log(" Optimizing out %d unused high-order bits (new width is %d)\n",
extract.width - newbits,
newbits);

14
passes/techmap/extract_fa.cc
View file

@ -262,7 +262,7 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit);
for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
for (auto port : {ID::A, ID::B, ID::C, ID::D}) {
if (!cell->hasPort(port))
continue;
auto bit = sigmap(SigBit(cell->getPort(port)));
@ -395,18 +395,18 @@ struct ExtractFaWorker
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), 1);
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
@ -501,18 +501,18 @@ struct ExtractFaWorker
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), 1);
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", log_id(cell));
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID(C), State::S0);
cell->setPort(ID::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
cell->setPort(ID(X), X);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
}

6
passes/techmap/extract_reduce.cc
View file

@ -294,9 +294,9 @@ struct ExtractReducePass : public Pass
gt == GateType::And ? ID($reduce_and) :
gt == GateType::Or ? ID($reduce_or) :
gt == GateType::Xor ? ID($reduce_xor) : "");
new_reduce_cell->setParam(ID(A_SIGNED), 0);
new_reduce_cell->setParam(ID(A_WIDTH), input.size());
new_reduce_cell->setParam(ID(Y_WIDTH), 1);
new_reduce_cell->setParam(ID::A_SIGNED, 0);
new_reduce_cell->setParam(ID::A_WIDTH, input.size());
new_reduce_cell->setParam(ID::Y_WIDTH, 1);
new_reduce_cell->setPort(ID::A, input);
new_reduce_cell->setPort(ID::Y, output);

2
passes/techmap/extractinv.cc
View file

@ -90,7 +90,7 @@ struct ExtractinvPass : public Pass {
auto cell_wire = cell_module->wire(port.first);
if (!cell_wire)
continue;
auto it = cell_wire->attributes.find("\\invertible_pin");
auto it = cell_wire->attributes.find(ID::invertible_pin);
if (it == cell_wire->attributes.end())
continue;
IdString param_name = RTLIL::escape_id(it->second.decode_string());

2
passes/techmap/flowmap.cc
View file

@ -1413,7 +1413,7 @@ struct FlowmapWorker
for (auto gate_node : lut_gates[node])
{
auto gate_origin = node_origins[gate_node];
lut->add_strpool_attribute(ID(src), gate_origin.cell->get_strpool_attribute(ID(src)));
lut->add_strpool_attribute(ID::src, gate_origin.cell->get_strpool_attribute(ID::src));
packed_count++;
}
lut_count++;

2
passes/techmap/insbuf.cc
View file

@ -41,7 +41,7 @@ struct InsbufPass : public Pass {
{
log_header(design, "Executing INSBUF pass (insert buffer cells for connected wires).\n");
IdString celltype = "$_BUF_", in_portname = ID::A, out_portname = ID::Y;
IdString celltype = ID($_BUF_), in_portname = ID::A, out_portname = ID::Y;
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++)

8
passes/techmap/iopadmap.cc
View file

@ -203,7 +203,7 @@ struct IopadmapPass : public Pass {
// Collect explicitly-marked already-buffered SigBits.
for (auto wire : module->wires())
if (wire->get_bool_attribute("\\iopad_external_pin") || ignore.count(make_pair(module->name, wire->name)))
if (wire->get_bool_attribute(ID::iopad_external_pin) || ignore.count(make_pair(module->name, wire->name)))
for (int i = 0; i < GetSize(wire); i++)
buf_bits.insert(sigmap(SigBit(wire, i)));
@ -287,7 +287,7 @@ struct IopadmapPass : public Pass {
if (tbuf_cell != nullptr) {
// Found a tristate buffer — use it.
en_sig = tbuf_cell->getPort(ID(E)).as_bit();
en_sig = tbuf_cell->getPort(ID::E).as_bit();
data_sig = tbuf_cell->getPort(ID::A).as_bit();
} else if (is_driven) {
// No tristate buffer, but an always-on driver is present.
@ -476,10 +476,10 @@ struct IopadmapPass : public Pass {
}
if (wire->port_output) {
auto jt = new_wire->attributes.find(ID(init));
auto jt = new_wire->attributes.find(ID::init);
// For output ports, move \init attributes from old wire to new wire
if (jt != new_wire->attributes.end()) {
wire->attributes[ID(init)] = std::move(jt->second);
wire->attributes[ID::init] = std::move(jt->second);
new_wire->attributes.erase(jt);
}
}

2
passes/techmap/lut2mux.cc
View file

@ -27,7 +27,7 @@ int lut2mux(Cell *cell)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
Const lut = cell->getParam(ID(LUT));
Const lut = cell->getParam(ID::LUT);
int count = 1;
if (GetSize(sig_a) == 1)

16
passes/techmap/maccmap.cc
View file

@ -112,12 +112,12 @@ struct MaccmapWorker
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
cell->setParam(ID(WIDTH), width);
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
cell->setPort(ID(C), in3);
cell->setPort(ID::C, in3);
cell->setPort(ID::Y, w1);
cell->setPort(ID(X), w2);
cell->setPort(ID::X, w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb};
@ -240,15 +240,15 @@ struct MaccmapWorker
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
c->setPort(ID(CI), State::S0);
c->setPort(ID(BI), State::S0);
c->setPort(ID::CI, State::S0);
c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID(X), module->addWire(NEW_ID, width));
c->setPort(ID(CO), module->addWire(NEW_ID, width));
c->setPort(ID::X, module->addWire(NEW_ID, width));
c->setPort(ID::CO, module->addWire(NEW_ID, width));
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
c->setPort(ID(CI), tree_sum_bits.back());
c->setPort(ID::CI, tree_sum_bits.back());
tree_sum_bits.pop_back();
}
log_assert(tree_sum_bits.empty());

66
passes/techmap/muxcover.cc
View file

@ -116,7 +116,7 @@ struct MuxcoverWorker
if (!cell->input(conn.first))
continue;
for (auto bit : sigmap(conn.second)) {
if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID(S))
if (used_once.count(bit) || cell->type != ID($_MUX_) || conn.first == ID::S)
roots.insert(bit);
used_once.insert(bit);
}
@ -519,7 +519,7 @@ struct MuxcoverWorker
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::Y, bit);
return;
}
@ -529,10 +529,10 @@ struct MuxcoverWorker
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::Y, bit);
return;
}
@ -542,15 +542,15 @@ struct MuxcoverWorker
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
cell->setPort(ID(F), mux.inputs[5]);
cell->setPort(ID(G), mux.inputs[6]);
cell->setPort(ID(H), mux.inputs[7]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::E, mux.inputs[4]);
cell->setPort(ID::F, mux.inputs[5]);
cell->setPort(ID::G, mux.inputs[6]);
cell->setPort(ID::H, mux.inputs[7]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::U, mux.selects[2]);
cell->setPort(ID::Y, bit);
return;
}
@ -560,24 +560,24 @@ struct MuxcoverWorker
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID(C), mux.inputs[2]);
cell->setPort(ID(D), mux.inputs[3]);
cell->setPort(ID(E), mux.inputs[4]);
cell->setPort(ID(F), mux.inputs[5]);
cell->setPort(ID(G), mux.inputs[6]);
cell->setPort(ID(H), mux.inputs[7]);
cell->setPort(ID(I), mux.inputs[8]);
cell->setPort(ID(J), mux.inputs[9]);
cell->setPort(ID(K), mux.inputs[10]);
cell->setPort(ID(L), mux.inputs[11]);
cell->setPort(ID(M), mux.inputs[12]);
cell->setPort(ID(N), mux.inputs[13]);
cell->setPort(ID(O), mux.inputs[14]);
cell->setPort(ID(P), mux.inputs[15]);
cell->setPort(ID(S), mux.selects[0]);
cell->setPort(ID(T), mux.selects[1]);
cell->setPort(ID(U), mux.selects[2]);
cell->setPort(ID(V), mux.selects[3]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::E, mux.inputs[4]);
cell->setPort(ID::F, mux.inputs[5]);
cell->setPort(ID::G, mux.inputs[6]);
cell->setPort(ID::H, mux.inputs[7]);
cell->setPort(ID::I, mux.inputs[8]);
cell->setPort(ID::J, mux.inputs[9]);
cell->setPort(ID::K, mux.inputs[10]);
cell->setPort(ID::L, mux.inputs[11]);
cell->setPort(ID::M, mux.inputs[12]);
cell->setPort(ID::N, mux.inputs[13]);
cell->setPort(ID::O, mux.inputs[14]);
cell->setPort(ID::P, mux.inputs[15]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::U, mux.selects[2]);
cell->setPort(ID::V, mux.selects[3]);
cell->setPort(ID::Y, bit);
return;
}

2
passes/techmap/pmuxtree.cc
View file

@ -93,7 +93,7 @@ struct PmuxtreePass : public Pass {
continue;
SigSpec sig_data = cell->getPort(ID::B);
SigSpec sig_sel = cell->getPort(ID(S));
SigSpec sig_sel = cell->getPort(ID::S);
if (!cell->getPort(ID::A).is_fully_undef()) {
sig_data.append(cell->getPort(ID::A));

32
passes/techmap/shregmap.cc
View file

@ -71,12 +71,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech
bool fixup(Cell *cell, dict<int, SigBit> &taps)
{
auto D = cell->getPort(ID(D));
auto C = cell->getPort(ID(C));
auto D = cell->getPort(ID::D);
auto C = cell->getPort(ID::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
newcell->setPort(ID(CLK), C);
newcell->setPort(ID::CLK, C);
newcell->setPort(ID(IN), D);
int i = 0;
@ -117,9 +117,9 @@ struct ShregmapWorker
sigbit_with_non_chain_users.insert(bit);
}
if (wire->attributes.count(ID(init))) {
if (wire->attributes.count(ID::init)) {
SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at(ID(init));
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (initval[i] == State::S0 && !opts.zinit)
sigbit_init[initsig[i]] = false;
@ -319,7 +319,7 @@ struct ShregmapWorker
initval.push_back(State::S0);
remove_init.insert(bit);
}
first_cell->setParam(ID(INIT), initval);
first_cell->setParam(ID::INIT, initval);
}
if (opts.zinit)
@ -348,7 +348,7 @@ struct ShregmapWorker
first_cell->type = shreg_cell_type_str;
first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam(ID(DEPTH), depth);
first_cell->setParam(ID::DEPTH, depth);
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
remove_cells.insert(first_cell);
@ -366,18 +366,18 @@ struct ShregmapWorker
for (auto wire : module->wires())
{
if (wire->attributes.count(ID(init)) == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec initsig = sigmap(wire);
Const &initval = wire->attributes.at(ID(init));
Const &initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
if (remove_init.count(initsig[i]))
initval[i] = State::Sx;
if (SigSpec(initval).is_fully_undef())
wire->attributes.erase(ID(init));
wire->attributes.erase(ID::init);
}
remove_cells.clear();
@ -548,19 +548,19 @@ struct ShregmapPass : public Pass {
bool en_neg = enpol == "neg" || enpol == "any" || enpol == "any_or_none";
if (clk_pos && en_none)
opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFF_P_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_none)
opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFF_N_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_pos)
opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFFE_PP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_pos && en_neg)
opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFFE_PN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_pos)
opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFFE_NP_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (clk_neg && en_neg)
opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID(D)), IdString(ID(Q)));
opts.ffcells[ID($_DFFE_NN_)] = make_pair(IdString(ID::D), IdString(ID::Q));
if (en_pos || en_neg)
opts.ffe = true;

206
passes/techmap/simplemap.cc
View file

@ -31,11 +31,11 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
}
@ -46,7 +46,7 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
@ -57,8 +57,8 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID(A_SIGNED)).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID(B_SIGNED)).as_bool());
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->parameters.at(ID::B_SIGNED).as_bool());
if (cell->type == ID($xnor))
{
@ -66,7 +66,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_t[i]);
gate->setPort(ID::Y, sig_y[i]);
}
@ -83,7 +83,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::Y, sig_y[i]);
@ -134,7 +134,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
@ -147,7 +147,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
last_output_cell = gate;
@ -175,7 +175,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
@ -204,7 +204,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
}
@ -233,7 +233,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
gate->setPort(ID::Y, sig_y);
@ -244,24 +244,24 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
bool is_signed = cell->parameters.at(ID(A_SIGNED)).as_bool();
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
xor_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
xor_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
reduce_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
reduce_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_reduce(module, reduce_cell);
module->remove(reduce_cell);
if (!is_ne) {
RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y);
not_cell->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
not_cell->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
simplemap_lognot(module, not_cell);
module->remove(not_cell);
}
@ -275,10 +275,10 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID(S), cell->getPort(ID(S)));
gate->setPort(ID::S, cell->getPort(ID::S));
gate->setPort(ID::Y, sig_y[i]);
}
}
@ -286,14 +286,14 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_e = cell->getPort(ID(EN));
RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID(E), sig_e);
gate->setPort(ID::E, sig_e);
gate->setPort(ID::Y, sig_y[i]);
}
}
@ -301,18 +301,18 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec lut_ctrl = cell->getPort(ID::A);
SigSpec lut_data = cell->getParam(ID(LUT));
lut_data.extend_u0(1 << cell->getParam(ID(WIDTH)).as_int());
SigSpec lut_data = cell->getParam(ID::LUT);
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec sig_s = lut_ctrl[idx];
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID(S), lut_ctrl[idx]);
gate->setPort(ID::S, lut_ctrl[idx]);
gate->setPort(ID::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
@ -324,10 +324,10 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec ctrl = cell->getPort(ID::A);
SigSpec table = cell->getParam(ID(TABLE));
SigSpec table = cell->getParam(ID::TABLE);
int width = cell->getParam(ID(WIDTH)).as_int();
int depth = cell->getParam(ID(DEPTH)).as_int();
int width = cell->getParam(ID::WIDTH).as_int();
int depth = cell->getParam(ID::DEPTH).as_int();
table.extend_u0(2 * width * depth);
SigSpec products;
@ -353,7 +353,7 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
int offset = cell->parameters.at(ID(OFFSET)).as_int();
int offset = cell->parameters.at(ID::OFFSET).as_int();
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
@ -369,156 +369,156 @@ void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
std::string gate_type = stringf("$_SR_%c%c_", set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(S), sig_s[i]);
gate->setPort(ID(R), sig_r[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::S, sig_s[i]);
gate->setPort(ID::R, sig_r[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_ff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
int width = cell->parameters.at(ID::WIDTH).as_int();
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = ID($_FF_);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFF_%c_", clk_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(C), sig_clk);
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::C, sig_clk);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dffe(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFFE_%c%c_", clk_pol, en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(C), sig_clk);
gate->setPort(ID(E), sig_en);
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::C, sig_clk);
gate->setPort(ID::E, sig_en);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dffsr(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char set_pol = cell->parameters.at(ID(SET_POLARITY)).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at(ID(CLR_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
char set_pol = cell->parameters.at(ID::SET_POLARITY).as_bool() ? 'P' : 'N';
char clr_pol = cell->parameters.at(ID::CLR_POLARITY).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_s = cell->getPort(ID(SET));
RTLIL::SigSpec sig_r = cell->getPort(ID(CLR));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_s = cell->getPort(ID::SET);
RTLIL::SigSpec sig_r = cell->getPort(ID::CLR);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DFFSR_%c%c%c_", clk_pol, set_pol, clr_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(C), sig_clk);
gate->setPort(ID(S), sig_s[i]);
gate->setPort(ID(R), sig_r[i]);
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::C, sig_clk);
gate->setPort(ID::S, sig_s[i]);
gate->setPort(ID::R, sig_r[i]);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_adff(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char clk_pol = cell->parameters.at(ID(CLK_POLARITY)).as_bool() ? 'P' : 'N';
char rst_pol = cell->parameters.at(ID(ARST_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char clk_pol = cell->parameters.at(ID::CLK_POLARITY).as_bool() ? 'P' : 'N';
char rst_pol = cell->parameters.at(ID::ARST_POLARITY).as_bool() ? 'P' : 'N';
std::vector<RTLIL::State> rst_val = cell->parameters.at(ID(ARST_VALUE)).bits;
std::vector<RTLIL::State> rst_val = cell->parameters.at(ID::ARST_VALUE).bits;
while (int(rst_val.size()) < width)
rst_val.push_back(RTLIL::State::S0);
RTLIL::SigSpec sig_clk = cell->getPort(ID(CLK));
RTLIL::SigSpec sig_rst = cell->getPort(ID(ARST));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_rst = cell->getPort(ID::ARST);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type_0 = stringf("$_DFF_%c%c0_", clk_pol, rst_pol);
IdString gate_type_1 = stringf("$_DFF_%c%c1_", clk_pol, rst_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, rst_val.at(i) == RTLIL::State::S1 ? gate_type_1 : gate_type_0);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(C), sig_clk);
gate->setPort(ID(R), sig_rst);
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::C, sig_clk);
gate->setPort(ID::R, sig_rst);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}
void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at(ID(WIDTH)).as_int();
char en_pol = cell->parameters.at(ID(EN_POLARITY)).as_bool() ? 'P' : 'N';
int width = cell->parameters.at(ID::WIDTH).as_int();
char en_pol = cell->parameters.at(ID::EN_POLARITY).as_bool() ? 'P' : 'N';
RTLIL::SigSpec sig_en = cell->getPort(ID(EN));
RTLIL::SigSpec sig_d = cell->getPort(ID(D));
RTLIL::SigSpec sig_q = cell->getPort(ID(Q));
RTLIL::SigSpec sig_en = cell->getPort(ID::EN);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_q = cell->getPort(ID::Q);
IdString gate_type = stringf("$_DLATCH_%c_", en_pol);
for (int i = 0; i < width; i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->add_strpool_attribute(ID(src), cell->get_strpool_attribute(ID(src)));
gate->setPort(ID(E), sig_en);
gate->setPort(ID(D), sig_d[i]);
gate->setPort(ID(Q), sig_q[i]);
gate->add_strpool_attribute(ID::src, cell->get_strpool_attribute(ID::src));
gate->setPort(ID::E, sig_en);
gate->setPort(ID::D, sig_d[i]);
gate->setPort(ID::Q, sig_q[i]);
}
}

80
passes/techmap/techmap.cc
View file

@ -146,7 +146,7 @@ struct TechmapWorker
record.value = it.second;
result[p].push_back(record);
it.second->attributes[ID::keep] = RTLIL::Const(1);
it.second->attributes[ID(_techmap_special_)] = RTLIL::Const(1);
it.second->attributes[ID::_techmap_special_] = RTLIL::Const(1);
}
}
@ -175,12 +175,12 @@ struct TechmapWorker
}
std::string orig_cell_name;
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID(src));
pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
orig_cell_name = cell->name.str();
if (!flatten_mode) {
for (auto &it : tpl->cells_)
if (it.first == ID(_TECHMAP_REPLACE_)) {
if (it.first == ID::_TECHMAP_REPLACE_) {
module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
break;
}
@ -197,8 +197,8 @@ struct TechmapWorker
m->start_offset = it.second->start_offset;
m->size = it.second->size;
m->attributes = it.second->attributes;
if (m->attributes.count(ID(src)))
m->add_strpool_attribute(ID(src), extra_src_attrs);
if (m->attributes.count(ID::src))
m->add_strpool_attribute(ID::src, extra_src_attrs);
module->memories[m->name] = m;
memory_renames[it.first] = m->name;
design->select(module, m);
@ -215,7 +215,7 @@ struct TechmapWorker
IdString posportname = stringf("$%d", it.second->port_id);
positional_ports[posportname] = it.first;
if (!flatten_mode && it.second->get_bool_attribute(ID(techmap_autopurge)) &&
if (!flatten_mode && it.second->get_bool_attribute(ID::techmap_autopurge) &&
(!cell->hasPort(it.second->name) || !GetSize(cell->getPort(it.second->name))) &&
(!cell->hasPort(posportname) || !GetSize(cell->getPort(posportname))))
{
@ -231,12 +231,12 @@ struct TechmapWorker
apply_prefix(cell->name, w_name);
RTLIL::Wire *w = module->wire(w_name);
if (w != nullptr) {
if (!flatten_mode || !w->get_bool_attribute(ID(hierconn))) {
if (!flatten_mode || !w->get_bool_attribute(ID::hierconn)) {
temp_renamed_wires[w] = w->name;
module->rename(w, NEW_ID);
w = nullptr;
} else {
w->attributes.erase(ID(hierconn));
w->attributes.erase(ID::hierconn);
if (GetSize(w) < GetSize(it.second)) {
log_warning("Widening signal %s.%s to match size of %s.%s (via %s.%s).\n", log_id(module), log_id(w),
log_id(tpl), log_id(it.second), log_id(module), log_id(cell));
@ -250,11 +250,11 @@ struct TechmapWorker
w->port_output = false;
w->port_id = 0;
if (!flatten_mode)
w->attributes.erase(ID(techmap_autopurge));
if (it.second->get_bool_attribute(ID(_techmap_special_)))
w->attributes.erase(ID::techmap_autopurge);
if (it.second->get_bool_attribute(ID::_techmap_special_))
w->attributes.clear();
if (w->attributes.count(ID(src)))
w->add_strpool_attribute(ID(src), extra_src_attrs);
if (w->attributes.count(ID::src))
w->add_strpool_attribute(ID::src, extra_src_attrs);
}
design->select(module, w);
@ -363,7 +363,7 @@ struct TechmapWorker
}
for (auto &attr : w->attributes) {
if (attr.first == ID(src))
if (attr.first == ID::src)
continue;
auto lhs = GetSize(extra_connect.first);
auto rhs = GetSize(extra_connect.second);
@ -380,7 +380,7 @@ struct TechmapWorker
for (auto &it : tpl->cells_)
{
IdString c_name = it.second->name.str();
bool techmap_replace_cell = (!flatten_mode) && (c_name == ID(_TECHMAP_REPLACE_));
bool techmap_replace_cell = (!flatten_mode) && (c_name == ID::_TECHMAP_REPLACE_);
if (techmap_replace_cell)
c_name = orig_cell_name;
@ -421,19 +421,19 @@ struct TechmapWorker
c->unsetPort(it2);
if (c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
IdString memid = c->getParam(ID(MEMID)).decode_string();
IdString memid = c->getParam(ID::MEMID).decode_string();
log_assert(memory_renames.count(memid) != 0);
c->setParam(ID(MEMID), Const(memory_renames[memid].str()));
c->setParam(ID::MEMID, Const(memory_renames[memid].str()));
}
if (c->type == ID($mem)) {
IdString memid = c->getParam(ID(MEMID)).decode_string();
IdString memid = c->getParam(ID::MEMID).decode_string();
apply_prefix(cell->name, memid);
c->setParam(ID(MEMID), Const(memid.c_str()));
c->setParam(ID::MEMID, Const(memid.c_str()));
}
if (c->attributes.count(ID(src)))
c->add_strpool_attribute(ID(src), extra_src_attrs);
if (c->attributes.count(ID::src))
c->add_strpool_attribute(ID::src, extra_src_attrs);
if (techmap_replace_cell)
for (auto attr : cell->attributes)
@ -481,8 +481,8 @@ struct TechmapWorker
pool<SigBit> remove_init_bits;
for (auto wire : module->wires()) {
if (wire->attributes.count("\\init")) {
Const value = wire->attributes.at("\\init");
if (wire->attributes.count(ID::init)) {
Const value = wire->attributes.at(ID::init);
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++)
if (value[i] != State::Sx)
init_bits[sigmap(SigBit(wire, i))] = value[i];
@ -509,9 +509,9 @@ struct TechmapWorker
}
if (flatten_mode) {
bool keepit = cell->get_bool_attribute(ID(keep_hierarchy));
bool keepit = cell->get_bool_attribute(ID::keep_hierarchy);
for (auto &tpl_name : celltypeMap.at(cell_type))
if (map->modules_[tpl_name]->get_bool_attribute(ID(keep_hierarchy)))
if (map->modules_[tpl_name]->get_bool_attribute(ID::keep_hierarchy))
keepit = true;
if (keepit) {
if (!flatten_keep_list[cell]) {
@ -577,13 +577,13 @@ struct TechmapWorker
{
std::string extmapper_name;
if (tpl->get_bool_attribute(ID(techmap_simplemap)))
if (tpl->get_bool_attribute(ID::techmap_simplemap))
extmapper_name = "simplemap";
if (tpl->get_bool_attribute(ID(techmap_maccmap)))
if (tpl->get_bool_attribute(ID::techmap_maccmap))
extmapper_name = "maccmap";
if (tpl->attributes.count(ID(techmap_wrap)))
if (tpl->attributes.count(ID::techmap_wrap))
extmapper_name = "wrap";
if (!extmapper_name.empty())
@ -598,7 +598,7 @@ struct TechmapWorker
m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
if (extmapper_name == "wrap")
m_name += ":" + sha1(tpl->attributes.at(ID(techmap_wrap)).decode_string());
m_name += ":" + sha1(tpl->attributes.at(ID::techmap_wrap).decode_string());
RTLIL::Design *extmapper_design = extern_mode && !in_recursion ? design : tpl->design;
RTLIL::Module *extmapper_module = extmapper_design->module(m_name);
@ -613,7 +613,7 @@ struct TechmapWorker
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name.in(ID::Y, ID(Q)))
if (w->name.in(ID::Y, ID::Q))
w->port_output = true;
else
w->port_input = true;
@ -641,7 +641,7 @@ struct TechmapWorker
}
if (extmapper_name == "wrap") {
std::string cmd_string = tpl->attributes.at(ID(techmap_wrap)).decode_string();
std::string cmd_string = tpl->attributes.at(ID::techmap_wrap).decode_string();
log("Running \"%s\" on wrapper %s.\n", cmd_string.c_str(), log_id(extmapper_module));
mkdebug.on();
Pass::call_on_module(extmapper_design, extmapper_module, cmd_string);
@ -709,8 +709,8 @@ struct TechmapWorker
continue;
}
if (tpl->avail_parameters.count(ID(_TECHMAP_CELLTYPE_)) != 0)
parameters[ID(_TECHMAP_CELLTYPE_)] = RTLIL::unescape_id(cell->type);
if (tpl->avail_parameters.count(ID::_TECHMAP_CELLTYPE_) != 0)
parameters[ID::_TECHMAP_CELLTYPE_] = RTLIL::unescape_id(cell->type);
for (auto conn : cell->connections()) {
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@ -760,8 +760,8 @@ struct TechmapWorker
bits = i;
// Increment index by one to get number of bits
bits++;
if (tpl->avail_parameters.count(ID(_TECHMAP_BITS_CONNMAP_)))
parameters[ID(_TECHMAP_BITS_CONNMAP_)] = bits;
if (tpl->avail_parameters.count(ID::_TECHMAP_BITS_CONNMAP_))
parameters[ID::_TECHMAP_BITS_CONNMAP_] = bits;
for (auto conn : cell->connections())
if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
@ -1030,8 +1030,8 @@ struct TechmapWorker
if (!remove_init_bits.empty()) {
for (auto wire : module->wires())
if (wire->attributes.count("\\init")) {
Const &value = wire->attributes.at("\\init");
if (wire->attributes.count(ID::init)) {
Const &value = wire->attributes.at(ID::init);
bool do_cleanup = true;
for (int i = 0; i < min(GetSize(value), GetSize(wire)); i++) {
SigBit bit = sigmap(SigBit(wire, i));
@ -1042,7 +1042,7 @@ struct TechmapWorker
}
if (do_cleanup) {
log("Removing init attribute from wire %s.%s.\n", log_id(module), log_id(wire));
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
}
}
@ -1302,8 +1302,8 @@ struct TechmapPass : public Pass {
std::map<RTLIL::IdString, std::set<RTLIL::IdString, RTLIL::sort_by_id_str>> celltypeMap;
for (auto &it : map->modules_) {
if (it.second->attributes.count(ID(techmap_celltype)) && !it.second->attributes.at(ID(techmap_celltype)).bits.empty()) {
char *p = strdup(it.second->attributes.at(ID(techmap_celltype)).decode_string().c_str());
if (it.second->attributes.count(ID::techmap_celltype) && !it.second->attributes.at(ID::techmap_celltype).bits.empty()) {
char *p = strdup(it.second->attributes.at(ID::techmap_celltype).decode_string().c_str());
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
free(p);
@ -1389,7 +1389,7 @@ struct FlattenPass : public Pass {
RTLIL::Module *top_mod = NULL;
if (design->full_selection())
for (auto mod : design->modules())
if (mod->get_bool_attribute(ID(top)))
if (mod->get_bool_attribute(ID::top))
top_mod = mod;
std::set<RTLIL::Cell*> handled_cells;

14
passes/techmap/tribuf.cc
View file

@ -71,7 +71,7 @@ struct TribufWorker {
if (cell->type.in(ID($mux), ID($_MUX_)))
{
IdString en_port = cell->type == ID($mux) ? ID(EN) : ID(E);
IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) {
@ -81,9 +81,9 @@ struct TribufWorker {
if (is_all_z(cell->getPort(ID::A))) {
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(en_port, cell->getPort(ID(S)));
cell->setPort(en_port, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID(S));
cell->unsetPort(ID::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
@ -91,9 +91,9 @@ struct TribufWorker {
}
if (is_all_z(cell->getPort(ID::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID(S))));
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
cell->unsetPort(ID(S));
cell->unsetPort(ID::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
@ -121,9 +121,9 @@ struct TribufWorker {
SigSpec pmux_b, pmux_s;
for (auto cell : it.second) {
if (cell->type == ID($tribuf))
pmux_s.append(cell->getPort(ID(EN)));
pmux_s.append(cell->getPort(ID::EN));
else
pmux_s.append(cell->getPort(ID(E)));
pmux_s.append(cell->getPort(ID::E));
pmux_b.append(cell->getPort(ID::A));
module->remove(cell);
}

18
passes/techmap/zinit.cc
View file

@ -62,12 +62,12 @@ struct ZinitPass : public Pass {
for (auto wire : module->selected_wires())
{
if (wire->attributes.count(ID(init)) == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec wirebits = sigmap(wire);
Const initval = wire->attributes.at(ID(init));
wire->attributes.erase(ID(init));
Const initval = wire->attributes.at(ID::init);
wire->attributes.erase(ID::init);
for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
{
@ -103,8 +103,8 @@ struct ZinitPass : public Pass {
if (!dff_types.count(cell->type))
continue;
SigSpec sig_d = sigmap(cell->getPort(ID(D)));
SigSpec sig_q = sigmap(cell->getPort(ID(Q)));
SigSpec sig_d = sigmap(cell->getPort(ID::D));
SigSpec sig_q = sigmap(cell->getPort(ID::Q));
if (GetSize(sig_d) < 1 || GetSize(sig_q) < 1)
continue;
@ -120,14 +120,14 @@ struct ZinitPass : public Pass {
}
Wire *initwire = module->addWire(NEW_ID, GetSize(initval));
initwire->attributes[ID(init)] = initval;
initwire->attributes[ID::init] = initval;
for (int i = 0; i < GetSize(initwire); i++)
if (initval.bits.at(i) == State::S1)
{
sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
initwire->attributes[ID(init)].bits.at(i) = State::S0;
initwire->attributes[ID::init].bits.at(i) = State::S0;
}
else
{
@ -137,8 +137,8 @@ struct ZinitPass : public Pass {
log("FF init value for cell %s (%s): %s = %s\n", log_id(cell), log_id(cell->type),
log_signal(sig_q), log_signal(initval));
cell->setPort(ID(D), sig_d);
cell->setPort(ID(Q), initwire);
cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, initwire);
}
for (auto &it : initbits)