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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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18
passes/proc/proc_arst.cc
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@ -39,23 +39,23 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
if (cell->type == "$reduce_or" && cell->getPort(ID::Y) == signal)
if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$reduce_bool" && cell->getPort(ID::Y) == signal)
if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == "$logic_not" && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
if (cell->type == "$not" && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
}
if (cell->type.in("$eq", "$eqx") && cell->getPort(ID::Y) == signal) {
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool())
polarity = !polarity;
@ -68,7 +68,7 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
}
}
if (cell->type.in("$ne", "$nex") && cell->getPort(ID::Y) == signal) {
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool())
polarity = !polarity;
@ -261,8 +261,8 @@ struct ProcArstPass : public Pass {
for (auto &act : sync->actions) {
RTLIL::SigSpec arst_sig, arst_val;
for (auto &chunk : act.first.chunks())
if (chunk.wire && chunk.wire->attributes.count("\\init")) {
RTLIL::SigSpec value = chunk.wire->attributes.at("\\init");
if (chunk.wire && chunk.wire->attributes.count(ID::init)) {
RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init);
value.extend_u0(chunk.wire->width, false);
arst_sig.append(chunk);
arst_val.append(value.extract(chunk.offset, chunk.width));
@ -285,7 +285,7 @@ struct ProcArstPass : public Pass {
}
for (auto wire : delete_initattr_wires)
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
} ProcArstPass;