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https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -65,7 +65,7 @@ struct WreduceWorker
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SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
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SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
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SigSpec sig_s = mi.sigmap(cell->getPort(ID(S)));
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SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
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SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
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std::vector<SigBit> bits_removed;
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@ -141,8 +141,8 @@ struct WreduceWorker
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{
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// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
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SigSpec sig_d = mi.sigmap(cell->getPort(ID(D)));
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SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q)));
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SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
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SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
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bool is_adff = (cell->type == ID($adff));
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Const initval, arst_value;
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@ -151,8 +151,8 @@ struct WreduceWorker
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if (width_before == 0)
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return;
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if (cell->parameters.count(ID(ARST_VALUE))) {
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arst_value = cell->parameters[ID(ARST_VALUE)];
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if (cell->parameters.count(ID::ARST_VALUE)) {
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arst_value = cell->parameters[ID::ARST_VALUE];
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}
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bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0;
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@ -220,13 +220,13 @@ struct WreduceWorker
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work_queue_bits.insert(bit);
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// Narrow ARST_VALUE parameter to new size.
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if (cell->parameters.count(ID(ARST_VALUE))) {
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if (cell->parameters.count(ID::ARST_VALUE)) {
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arst_value.bits.resize(GetSize(sig_q));
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cell->setParam(ID(ARST_VALUE), arst_value);
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cell->setParam(ID::ARST_VALUE, arst_value);
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}
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cell->setPort(ID(D), sig_d);
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cell->setPort(ID(Q), sig_q);
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cell->setPort(ID::D, sig_d);
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cell->setPort(ID::Q, sig_q);
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cell->fixup_parameters();
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}
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@ -306,8 +306,8 @@ struct WreduceWorker
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GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
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log("Converting cell %s.%s (%s) from signed to unsigned.\n",
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log_id(module), log_id(cell), log_id(cell->type));
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cell->setParam(ID(A_SIGNED), 0);
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cell->setParam(ID(B_SIGNED), 0);
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cell->setParam(ID::A_SIGNED, 0);
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cell->setParam(ID::B_SIGNED, 0);
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port_a_signed = false;
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port_b_signed = false;
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did_something = true;
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@ -319,7 +319,7 @@ struct WreduceWorker
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if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
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log("Converting cell %s.%s (%s) from signed to unsigned.\n",
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log_id(module), log_id(cell), log_id(cell->type));
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cell->setParam(ID(A_SIGNED), 0);
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cell->setParam(ID::A_SIGNED, 0);
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port_a_signed = false;
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did_something = true;
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}
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@ -349,7 +349,7 @@ struct WreduceWorker
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if (cell->type.in(ID($pos), ID($add), ID($mul), ID($and), ID($or), ID($xor), ID($sub)))
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{
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bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool() || cell->type == ID($sub);
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bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
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int a_size = 0, b_size = 0;
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if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
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@ -392,8 +392,8 @@ struct WreduceWorker
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static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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{
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int count = w->attributes.size();
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count -= w->attributes.count(ID(src));
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count -= w->attributes.count(ID(unused_bits));
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count -= w->attributes.count(ID::src);
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count -= w->attributes.count(ID::unused_bits);
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return count;
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}
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@ -406,8 +406,8 @@ struct WreduceWorker
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if (w->get_bool_attribute(ID::keep))
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for (auto bit : mi.sigmap(w))
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keep_bits.insert(bit);
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if (w->attributes.count(ID(init))) {
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Const initval = w->attributes.at(ID(init));
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if (w->attributes.count(ID::init)) {
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Const initval = w->attributes.at(ID::init);
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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for (int i = 0; i < width; i++)
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@ -464,8 +464,8 @@ struct WreduceWorker
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if (!remove_init_bits.empty()) {
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for (auto w : module->wires()) {
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if (w->attributes.count(ID(init))) {
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Const initval = w->attributes.at(ID(init));
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if (w->attributes.count(ID::init)) {
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Const initval = w->attributes.at(ID::init);
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Const new_initval(State::Sx, GetSize(w));
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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@ -473,7 +473,7 @@ struct WreduceWorker
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if (!remove_init_bits.count(initsig[i]))
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new_initval[i] = initval[i];
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}
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w->attributes.at(ID(init)) = new_initval;
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w->attributes.at(ID::init) = new_initval;
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}
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}
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}
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@ -539,7 +539,7 @@ struct WreducePass : public Pass {
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SigSpec sig = c->getPort(ID::Y);
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if (!sig.has_const()) {
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c->setPort(ID::Y, sig[0]);
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c->setParam(ID(Y_WIDTH), 1);
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c->setParam(ID::Y_WIDTH, 1);
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sig.remove(0);
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module->connect(sig, Const(0, GetSize(sig)));
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}
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@ -549,7 +549,7 @@ struct WreducePass : public Pass {
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{
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SigSpec A = c->getPort(ID::A);
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int original_a_width = GetSize(A);
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if (c->getParam(ID(A_SIGNED)).as_bool()) {
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if (c->getParam(ID::A_SIGNED).as_bool()) {
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while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
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A.remove(GetSize(A)-1, 1);
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} else {
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@ -560,12 +560,12 @@ struct WreducePass : public Pass {
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log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
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original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type));
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c->setPort(ID::A, A);
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c->setParam(ID(A_WIDTH), GetSize(A));
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c->setParam(ID::A_WIDTH, GetSize(A));
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}
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SigSpec B = c->getPort(ID::B);
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int original_b_width = GetSize(B);
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if (c->getParam(ID(B_SIGNED)).as_bool()) {
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if (c->getParam(ID::B_SIGNED).as_bool()) {
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while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
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B.remove(GetSize(B)-1, 1);
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} else {
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@ -576,23 +576,23 @@ struct WreducePass : public Pass {
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log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
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original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type));
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c->setPort(ID::B, B);
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c->setParam(ID(B_WIDTH), GetSize(B));
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c->setParam(ID::B_WIDTH, GetSize(B));
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}
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}
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if (!opt_memx && c->type.in(ID($memrd), ID($memwr), ID($meminit))) {
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IdString memid = c->getParam(ID(MEMID)).decode_string();
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IdString memid = c->getParam(ID::MEMID).decode_string();
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RTLIL::Memory *mem = module->memories.at(memid);
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if (mem->start_offset >= 0) {
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int cur_addrbits = c->getParam(ID(ABITS)).as_int();
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int cur_addrbits = c->getParam(ID::ABITS).as_int();
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int max_addrbits = ceil_log2(mem->start_offset + mem->size);
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if (cur_addrbits > max_addrbits) {
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log("Removed top %d address bits (of %d) from memory %s port %s.%s (%s).\n",
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cur_addrbits-max_addrbits, cur_addrbits,
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c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
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log_id(module), log_id(c), log_id(memid));
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c->setParam(ID(ABITS), max_addrbits);
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c->setPort(ID(ADDR), c->getPort(ID(ADDR)).extract(0, max_addrbits));
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c->setParam(ID::ABITS, max_addrbits);
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c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
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}
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}
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}
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