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https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -46,7 +46,7 @@ struct OnehotDatabase
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for (auto wire : module->wires())
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{
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auto it = wire->attributes.find(ID(init));
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auto it = wire->attributes.find(ID::init);
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if (it == wire->attributes.end())
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continue;
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@ -65,10 +65,10 @@ struct OnehotDatabase
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if (cell->type.in(ID($adff), ID($dff), ID($dffe), ID($dlatch), ID($ff)))
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{
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output = cell->getPort(ID(Q));
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output = cell->getPort(ID::Q);
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if (cell->type == ID($adff))
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inputs.push_back(cell->getParam(ID(ARST_VALUE)));
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inputs.push_back(cell->getPort(ID(D)));
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inputs.push_back(cell->getParam(ID::ARST_VALUE));
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inputs.push_back(cell->getPort(ID::D));
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}
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if (cell->type.in(ID($mux), ID($pmux)))
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@ -299,16 +299,16 @@ struct Pmux2ShiftxPass : public Pass {
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SigSpec A = sigmap(cell->getPort(ID::A));
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SigSpec B = sigmap(cell->getPort(ID::B));
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int a_width = cell->getParam(ID(A_WIDTH)).as_int();
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int b_width = cell->getParam(ID(B_WIDTH)).as_int();
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int a_width = cell->getParam(ID::A_WIDTH).as_int();
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int b_width = cell->getParam(ID::B_WIDTH).as_int();
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if (a_width < b_width) {
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bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
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bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
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A.extend_u0(b_width, a_signed);
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}
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if (b_width < a_width) {
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bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
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B.extend_u0(a_width, b_signed);
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}
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@ -368,7 +368,7 @@ struct Pmux2ShiftxPass : public Pass {
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continue;
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string src = cell->get_src_attribute();
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int width = cell->getParam(ID(WIDTH)).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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int width_bits = ceil_log2(width);
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int extwidth = width;
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@ -379,7 +379,7 @@ struct Pmux2ShiftxPass : public Pass {
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SigSpec A = cell->getPort(ID::A);
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SigSpec B = cell->getPort(ID::B);
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SigSpec S = sigmap(cell->getPort(ID(S)));
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SigSpec S = sigmap(cell->getPort(ID::S));
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for (int i = 0; i < GetSize(S); i++)
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{
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if (!eqdb.count(S[i]))
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@ -400,7 +400,7 @@ struct Pmux2ShiftxPass : public Pass {
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log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
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}
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SigSpec updated_S = cell->getPort(ID(S));
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SigSpec updated_S = cell->getPort(ID::S);
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SigSpec updated_B = cell->getPort(ID::B);
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while (!seldb.empty())
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@ -727,9 +727,9 @@ struct Pmux2ShiftxPass : public Pass {
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}
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// update $pmux cell
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cell->setPort(ID(S), updated_S);
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cell->setPort(ID::S, updated_S);
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cell->setPort(ID::B, updated_B);
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cell->setParam(ID(S_WIDTH), GetSize(updated_S));
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cell->setParam(ID::S_WIDTH, GetSize(updated_S));
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}
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}
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}
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@ -785,16 +785,16 @@ struct OnehotPass : public Pass {
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SigSpec A = sigmap(cell->getPort(ID::A));
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SigSpec B = sigmap(cell->getPort(ID::B));
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int a_width = cell->getParam(ID(A_WIDTH)).as_int();
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int b_width = cell->getParam(ID(B_WIDTH)).as_int();
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int a_width = cell->getParam(ID::A_WIDTH).as_int();
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int b_width = cell->getParam(ID::B_WIDTH).as_int();
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if (a_width < b_width) {
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bool a_signed = cell->getParam(ID(A_SIGNED)).as_int();
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bool a_signed = cell->getParam(ID::A_SIGNED).as_int();
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A.extend_u0(b_width, a_signed);
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}
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if (b_width < a_width) {
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bool b_signed = cell->getParam(ID(B_SIGNED)).as_int();
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bool b_signed = cell->getParam(ID::B_SIGNED).as_int();
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B.extend_u0(a_width, b_signed);
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}
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