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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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32
passes/opt/opt_share.cc
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@ -98,8 +98,8 @@ struct ExtSigSpec {
bool cell_supported(RTLIL::Cell *cell)
{
if (cell->type.in(ID($alu))) {
RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
@ -139,7 +139,7 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
if (cell->type == ID($alu) && port_name == ID::B)
return cell->getPort(ID(BI));
return cell->getPort(ID::BI);
else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1);
@ -190,7 +190,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto shared_op = ports[0].op;
if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int());
max_width = std::max(max_width, shared_op->getParam(ID::Y_WIDTH).as_int());
for (auto &operand : muxed_operands)
@ -210,7 +210,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec mux_y = mux->getPort(ID::Y);
RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B);
RTLIL::SigSpec mux_s = mux->getPort(ID(S));
RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
RTLIL::SigSpec shared_pmux_b;
@ -237,7 +237,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b);
mux->setPort(ID::Y, mux_y);
mux->setPort(ID(S), mux_s);
mux->setPort(ID::S, mux_s);
for (const auto &op : muxed_operands)
shared_pmux_b.append(op.sig);
@ -245,26 +245,26 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
if (shared_op->type.in(ID($alu))) {
RTLIL::SigSpec alu_x = shared_op->getPort(ID(X));
RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO));
RTLIL::SigSpec alu_x = shared_op->getPort(ID::X);
RTLIL::SigSpec alu_co = shared_op->getPort(ID::CO);
shared_op->setPort(ID(X), alu_x.extract(0, conn_width));
shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
shared_op->setPort(ID::X, alu_x.extract(0, conn_width));
shared_op->setPort(ID::CO, alu_co.extract(0, conn_width));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
if (!is_fine)
shared_op->setParam(ID(Y_WIDTH), conn_width);
shared_op->setParam(ID::Y_WIDTH, conn_width);
if (decode_port(shared_op, ID::A, &assign_map) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID(B_WIDTH), max_width);
shared_op->setParam(ID::B_WIDTH, max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID(A_WIDTH), max_width);
shared_op->setParam(ID::A_WIDTH, max_width);
}
}
@ -452,7 +452,7 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
remove_connected_ops(cell->getPort(ID(S)));
remove_connected_ops(cell->getPort(ID::S));
find_op_mux_conns(cell);
} else {
for (auto &conn : cell->connections())
@ -510,7 +510,7 @@ struct OptSharePass : public Pass {
continue;
if (cell->type == ID($alu)) {
for (RTLIL::IdString port_name : {ID(X), ID(CO)}) {
for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
auto mux_insig = assign_map(cell->getPort(port_name));
outsig_to_operator[mux_insig] = cell;
for (auto outbit : mux_insig)
@ -552,7 +552,7 @@ struct OptSharePass : public Pass {
if (p.mux->type.in(ID($mux), ID($_MUX_)))
mux_port_num = 2;
else
mux_port_num = p.mux->getPort(ID(S)).size();
mux_port_num = p.mux->getPort(ID::S).size();
mux_port_conns.resize(mux_port_num);
}