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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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28
passes/opt/opt_reduce.cc
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@ -96,7 +96,7 @@ struct OptReduceWorker
}
cell->setPort(ID::A, new_sig_a);
cell->parameters[ID(A_WIDTH)] = RTLIL::Const(new_sig_a.size());
cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return;
}
@ -104,7 +104,7 @@ struct OptReduceWorker
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID(S)));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
pool<RTLIL::SigSpec> handled_sig;
@ -127,9 +127,9 @@ struct OptReduceWorker
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
reduce_or_cell->parameters[ID(A_SIGNED)] = RTLIL::Const(0);
reduce_or_cell->parameters[ID(A_WIDTH)] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID(Y_WIDTH)] = RTLIL::Const(1);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
this_s = RTLIL::SigSpec(reduce_or_wire);
@ -156,12 +156,12 @@ struct OptReduceWorker
else
{
cell->setPort(ID::B, new_sig_b);
cell->setPort(ID(S), new_sig_s);
cell->setPort(ID::S, new_sig_s);
if (new_sig_s.size() > 1) {
cell->parameters[ID(S_WIDTH)] = RTLIL::Const(new_sig_s.size());
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
cell->type = ID($mux);
cell->parameters.erase(ID(S_WIDTH));
cell->parameters.erase(ID::S_WIDTH);
}
}
}
@ -222,14 +222,14 @@ struct OptReduceWorker
}
cell->setPort(ID::B, RTLIL::SigSpec());
for (int i = 1; i <= cell->getPort(ID(S)).size(); i++)
for (int i = 1; i <= cell->getPort(ID::S).size(); i++)
for (auto &in_tuple : consolidated_in_tuples) {
RTLIL::SigSpec new_b = cell->getPort(ID::B);
new_b.append(in_tuple.at(i));
cell->setPort(ID::B, new_b);
}
cell->parameters[ID(WIDTH)] = RTLIL::Const(new_sig_y.size());
cell->parameters[ID::WIDTH] = RTLIL::Const(new_sig_y.size());
cell->setPort(ID::Y, new_sig_y);
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
@ -255,14 +255,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mem))
mem_wren_sigs.add(assign_map(cell->getPort(ID(WR_EN))));
mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
if (cell->type == ID($memwr))
mem_wren_sigs.add(assign_map(cell->getPort(ID(EN))));
mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID(Q)))))
mem_wren_sigs.add(assign_map(cell->getPort(ID(D))));
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
}
bool keep_expanding_mem_wren_sigs = true;