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https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -81,15 +81,15 @@ struct MemoryMapWorker
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std::set<int> static_ports;
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std::map<int, RTLIL::SigSpec> static_cells_map;
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int wr_ports = cell->parameters["\\WR_PORTS"].as_int();
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int rd_ports = cell->parameters["\\RD_PORTS"].as_int();
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int wr_ports = cell->parameters[ID::WR_PORTS].as_int();
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int rd_ports = cell->parameters[ID::RD_PORTS].as_int();
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int mem_size = cell->parameters["\\SIZE"].as_int();
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int mem_width = cell->parameters["\\WIDTH"].as_int();
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int mem_offset = cell->parameters["\\OFFSET"].as_int();
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int mem_abits = cell->parameters["\\ABITS"].as_int();
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int mem_size = cell->parameters[ID::SIZE].as_int();
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int mem_width = cell->parameters[ID::WIDTH].as_int();
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int mem_offset = cell->parameters[ID::OFFSET].as_int();
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int mem_abits = cell->parameters[ID::ABITS].as_int();
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SigSpec init_data = cell->getParam("\\INIT");
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SigSpec init_data = cell->getParam(ID::INIT);
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init_data.extend_u0(mem_size*mem_width, true);
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// delete unused memory cell
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@ -99,22 +99,22 @@ struct MemoryMapWorker
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}
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// all write ports must share the same clock
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RTLIL::SigSpec clocks = cell->getPort("\\WR_CLK");
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RTLIL::Const clocks_pol = cell->parameters["\\WR_CLK_POLARITY"];
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RTLIL::Const clocks_en = cell->parameters["\\WR_CLK_ENABLE"];
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RTLIL::SigSpec clocks = cell->getPort(ID::WR_CLK);
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RTLIL::Const clocks_pol = cell->parameters[ID::WR_CLK_POLARITY];
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RTLIL::Const clocks_en = cell->parameters[ID::WR_CLK_ENABLE];
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clocks_pol.bits.resize(wr_ports);
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clocks_en.bits.resize(wr_ports);
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RTLIL::SigSpec refclock;
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RTLIL::State refclock_pol = RTLIL::State::Sx;
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for (int i = 0; i < clocks.size(); i++) {
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RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(i * mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(i * mem_width, mem_width);
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if (wr_en.is_fully_const() && !wr_en.as_bool()) {
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static_ports.insert(i);
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continue;
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}
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if (clocks_en.bits[i] != RTLIL::State::S1) {
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RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(i*mem_width, mem_width);
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RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(i*mem_width, mem_width);
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if (wr_addr.is_fully_const()) {
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// FIXME: Actually we should check for wr_en.is_fully_const() also and
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// create a $adff cell with this ports wr_en input as reset pin when wr_en
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@ -155,21 +155,21 @@ struct MemoryMapWorker
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}
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else
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), "$dff");
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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RTLIL::Cell *c = module->addCell(genid(cell->name, "", i), ID($dff));
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c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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if (clocks_pol.bits.size() > 0) {
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(clocks_pol.bits[0]);
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c->setPort("\\CLK", clocks.extract(0, 1));
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(clocks_pol.bits[0]);
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c->setPort(ID::CLK, clocks.extract(0, 1));
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} else {
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c->parameters["\\CLK_POLARITY"] = RTLIL::Const(RTLIL::State::S1);
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c->setPort("\\CLK", RTLIL::SigSpec(RTLIL::State::S0));
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c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
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c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
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}
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RTLIL::Wire *w_in = module->addWire(genid(cell->name, "", i, "$d"), mem_width);
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data_reg_in.push_back(RTLIL::SigSpec(w_in));
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c->setPort("\\D", data_reg_in.back());
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c->setPort(ID::D, data_reg_in.back());
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std::string w_out_name = stringf("%s[%d]", cell->parameters["\\MEMID"].decode_string().c_str(), i);
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std::string w_out_name = stringf("%s[%d]", cell->parameters[ID::MEMID].decode_string().c_str(), i);
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if (module->wires_.count(w_out_name) > 0)
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w_out_name = genid(cell->name, "", i, "$q");
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@ -177,10 +177,10 @@ struct MemoryMapWorker
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SigSpec w_init = init_data.extract(i*mem_width, mem_width);
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if (!w_init.is_fully_undef())
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w_out->attributes["\\init"] = w_init.as_const();
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w_out->attributes[ID::init] = w_init.as_const();
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data_reg_out.push_back(RTLIL::SigSpec(w_out));
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c->setPort("\\Q", data_reg_out.back());
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c->setPort(ID::Q, data_reg_out.back());
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}
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}
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@ -188,55 +188,55 @@ struct MemoryMapWorker
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int count_dff = 0, count_mux = 0, count_wrmux = 0;
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for (int i = 0; i < cell->parameters["\\RD_PORTS"].as_int(); i++)
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for (int i = 0; i < cell->parameters[ID::RD_PORTS].as_int(); i++)
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{
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RTLIL::SigSpec rd_addr = cell->getPort("\\RD_ADDR").extract(i*mem_abits, mem_abits);
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RTLIL::SigSpec rd_addr = cell->getPort(ID::RD_ADDR).extract(i*mem_abits, mem_abits);
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if (mem_offset)
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rd_addr = module->Sub(NEW_ID, rd_addr, SigSpec(mem_offset, GetSize(rd_addr)));
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std::vector<RTLIL::SigSpec> rd_signals;
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rd_signals.push_back(cell->getPort("\\RD_DATA").extract(i*mem_width, mem_width));
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rd_signals.push_back(cell->getPort(ID::RD_DATA).extract(i*mem_width, mem_width));
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if (cell->parameters["\\RD_CLK_ENABLE"].bits[i] == RTLIL::State::S1)
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if (cell->parameters[ID::RD_CLK_ENABLE].bits[i] == RTLIL::State::S1)
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{
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RTLIL::Cell *dff_cell = nullptr;
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if (cell->parameters["\\RD_TRANSPARENT"].bits[i] == RTLIL::State::S1)
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if (cell->parameters[ID::RD_TRANSPARENT].bits[i] == RTLIL::State::S1)
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{
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
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dff_cell->parameters["\\WIDTH"] = RTLIL::Const(mem_abits);
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dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
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dff_cell->setPort("\\D", rd_addr);
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
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dff_cell->parameters[ID::WIDTH] = RTLIL::Const(mem_abits);
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dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
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dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
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dff_cell->setPort(ID::D, rd_addr);
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count_dff++;
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RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$q"), mem_abits);
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dff_cell->setPort("\\Q", RTLIL::SigSpec(w));
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dff_cell->setPort(ID::Q, RTLIL::SigSpec(w));
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rd_addr = RTLIL::SigSpec(w);
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}
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else
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{
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), "$dff");
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dff_cell->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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dff_cell->parameters["\\CLK_POLARITY"] = RTLIL::Const(cell->parameters["\\RD_CLK_POLARITY"].bits[i]);
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dff_cell->setPort("\\CLK", cell->getPort("\\RD_CLK").extract(i, 1));
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dff_cell->setPort("\\Q", rd_signals.back());
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dff_cell = module->addCell(genid(cell->name, "$rdreg", i), ID($dff));
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dff_cell->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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dff_cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(cell->parameters[ID::RD_CLK_POLARITY].bits[i]);
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dff_cell->setPort(ID::CLK, cell->getPort(ID::RD_CLK).extract(i, 1));
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dff_cell->setPort(ID::Q, rd_signals.back());
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count_dff++;
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RTLIL::Wire *w = module->addWire(genid(cell->name, "$rdreg", i, "$d"), mem_width);
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rd_signals.clear();
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rd_signals.push_back(RTLIL::SigSpec(w));
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dff_cell->setPort("\\D", rd_signals.back());
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dff_cell->setPort(ID::D, rd_signals.back());
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}
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SigBit en_bit = cell->getPort("\\RD_EN").extract(i);
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SigBit en_bit = cell->getPort(ID::RD_EN).extract(i);
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if (en_bit != State::S1) {
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SigSpec new_d = module->Mux(genid(cell->name, "$rdenmux", i),
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dff_cell->getPort("\\Q"), dff_cell->getPort("\\D"), en_bit);
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dff_cell->setPort("\\D", new_d);
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dff_cell->getPort(ID::Q), dff_cell->getPort(ID::D), en_bit);
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dff_cell->setPort(ID::D, new_d);
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}
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}
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@ -246,8 +246,8 @@ struct MemoryMapWorker
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for (size_t k = 0; k < rd_signals.size(); k++)
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), "$mux");
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c->parameters["\\WIDTH"] = cell->parameters["\\WIDTH"];
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$rdmux", i, "", j, "", k), ID($mux));
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c->parameters[ID::WIDTH] = cell->parameters[ID::WIDTH];
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c->setPort(ID::Y, rd_signals[k]);
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c->setPort(ID::S, rd_addr.extract(mem_abits-j-1, 1));
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count_mux++;
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@ -275,11 +275,11 @@ struct MemoryMapWorker
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RTLIL::SigSpec sig = data_reg_out[i];
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for (int j = 0; j < cell->parameters["\\WR_PORTS"].as_int(); j++)
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for (int j = 0; j < cell->parameters[ID::WR_PORTS].as_int(); j++)
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{
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RTLIL::SigSpec wr_addr = cell->getPort("\\WR_ADDR").extract(j*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort("\\WR_DATA").extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->getPort("\\WR_EN").extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_addr = cell->getPort(ID::WR_ADDR).extract(j*mem_abits, mem_abits);
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RTLIL::SigSpec wr_data = cell->getPort(ID::WR_DATA).extract(j*mem_width, mem_width);
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RTLIL::SigSpec wr_en = cell->getPort(ID::WR_EN).extract(j*mem_width, mem_width);
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if (mem_offset)
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wr_addr = module->Sub(NEW_ID, wr_addr, SigSpec(mem_offset, GetSize(wr_addr)));
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@ -303,12 +303,12 @@ struct MemoryMapWorker
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if (wr_bit != State::S1)
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{
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), "$and");
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c->parameters["\\A_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\B_SIGNED"] = RTLIL::Const(0);
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c->parameters["\\A_WIDTH"] = RTLIL::Const(1);
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c->parameters["\\B_WIDTH"] = RTLIL::Const(1);
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c->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wren", i, "", j, "", wr_offset), ID($and));
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c->parameters[ID::A_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::B_SIGNED] = RTLIL::Const(0);
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c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
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c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
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c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
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c->setPort(ID::A, w);
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c->setPort(ID::B, wr_bit);
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@ -316,8 +316,8 @@ struct MemoryMapWorker
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c->setPort(ID::Y, RTLIL::SigSpec(w));
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}
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), "$mux");
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c->parameters["\\WIDTH"] = wr_width;
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RTLIL::Cell *c = module->addCell(genid(cell->name, "$wrmux", i, "", j, "", wr_offset), ID($mux));
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c->parameters[ID::WIDTH] = wr_width;
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c->setPort(ID::A, sig.extract(wr_offset, wr_width));
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c->setPort(ID::B, wr_data.extract(wr_offset, wr_width));
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c->setPort(ID::S, RTLIL::SigSpec(w));
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@ -343,7 +343,7 @@ struct MemoryMapWorker
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{
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std::vector<RTLIL::Cell*> cells;
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for (auto cell : module->selected_cells())
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if (cell->type == "$mem" && design->selected(module, cell))
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if (cell->type == ID($mem))
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cells.push_back(cell);
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for (auto cell : cells)
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handle_cell(cell);
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