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https://github.com/YosysHQ/yosys
synced 2025-07-31 00:13:18 +00:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -25,11 +25,11 @@ PRIVATE_NAMESPACE_BEGIN
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bool memcells_cmp(Cell *a, Cell *b)
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{
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if (a->type == "$memrd" && b->type == "$memrd")
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if (a->type == ID($memrd) && b->type == ID($memrd))
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return a->name < b->name;
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if (a->type == "$memrd" || b->type == "$memrd")
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return (a->type == "$memrd") < (b->type == "$memrd");
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return a->parameters.at("\\PRIORITY").as_int() < b->parameters.at("\\PRIORITY").as_int();
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if (a->type == ID($memrd) || b->type == ID($memrd))
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return (a->type == ID($memrd)) < (b->type == ID($memrd));
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return a->parameters.at(ID::PRIORITY).as_int() < b->parameters.at(ID::PRIORITY).as_int();
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}
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Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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@ -62,8 +62,8 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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for (auto &cell_it : module->cells_) {
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Cell *cell = cell_it.second;
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if (cell->type.in("$memrd", "$memwr", "$meminit") && memory->name == cell->parameters["\\MEMID"].decode_string()) {
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SigSpec addr = sigmap(cell->getPort("\\ADDR"));
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if (cell->type.in(ID($memrd), ID($memwr), ID($meminit)) && memory->name == cell->parameters[ID::MEMID].decode_string()) {
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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for (int i = 0; i < GetSize(addr); i++)
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if (addr[i] != State::S0)
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addr_bits = std::max(addr_bits, i+1);
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@ -90,10 +90,10 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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{
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log(" %s (%s)\n", log_id(cell), log_id(cell->type));
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if (cell->type == "$meminit")
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if (cell->type == ID($meminit))
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{
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SigSpec addr = sigmap(cell->getPort("\\ADDR"));
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SigSpec data = sigmap(cell->getPort("\\DATA"));
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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if (!addr.is_fully_const())
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log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), log_id(cell));
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@ -112,14 +112,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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continue;
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}
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if (cell->type == "$memwr")
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if (cell->type == ID($memwr))
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{
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SigSpec clk = sigmap(cell->getPort("\\CLK"));
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SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
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SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
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SigSpec addr = sigmap(cell->getPort("\\ADDR"));
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SigSpec data = sigmap(cell->getPort("\\DATA"));
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SigSpec en = sigmap(cell->getPort("\\EN"));
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SigSpec clk = sigmap(cell->getPort(ID::CLK));
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SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
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SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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SigSpec en = sigmap(cell->getPort(ID::EN));
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if (!en.is_fully_zero())
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{
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@ -142,15 +142,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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continue;
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}
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if (cell->type == "$memrd")
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if (cell->type == ID($memrd))
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{
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SigSpec clk = sigmap(cell->getPort("\\CLK"));
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SigSpec clk_enable = SigSpec(cell->parameters["\\CLK_ENABLE"]);
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SigSpec clk_polarity = SigSpec(cell->parameters["\\CLK_POLARITY"]);
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SigSpec transparent = SigSpec(cell->parameters["\\TRANSPARENT"]);
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SigSpec addr = sigmap(cell->getPort("\\ADDR"));
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SigSpec data = sigmap(cell->getPort("\\DATA"));
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SigSpec en = sigmap(cell->getPort("\\EN"));
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SigSpec clk = sigmap(cell->getPort(ID::CLK));
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SigSpec clk_enable = SigSpec(cell->parameters[ID::CLK_ENABLE]);
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SigSpec clk_polarity = SigSpec(cell->parameters[ID::CLK_POLARITY]);
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SigSpec transparent = SigSpec(cell->parameters[ID::TRANSPARENT]);
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SigSpec addr = sigmap(cell->getPort(ID::ADDR));
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SigSpec data = sigmap(cell->getPort(ID::DATA));
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SigSpec en = sigmap(cell->getPort(ID::EN));
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if (!en.is_fully_zero())
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{
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@ -178,13 +178,13 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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std::stringstream sstr;
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sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
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Cell *mem = module->addCell(sstr.str(), "$mem");
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mem->parameters["\\MEMID"] = Const(memory->name.str());
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mem->parameters["\\WIDTH"] = Const(memory->width);
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mem->parameters["\\OFFSET"] = Const(memory->start_offset);
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mem->parameters["\\SIZE"] = Const(memory->size);
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mem->parameters["\\ABITS"] = Const(addr_bits);
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mem->parameters["\\INIT"] = init_data;
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Cell *mem = module->addCell(sstr.str(), ID($mem));
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mem->parameters[ID::MEMID] = Const(memory->name.str());
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mem->parameters[ID::WIDTH] = Const(memory->width);
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mem->parameters[ID::OFFSET] = Const(memory->start_offset);
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mem->parameters[ID::SIZE] = Const(memory->size);
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mem->parameters[ID::ABITS] = Const(addr_bits);
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mem->parameters[ID::INIT] = init_data;
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log_assert(sig_wr_clk.size() == wr_ports);
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log_assert(sig_wr_clk_enable.size() == wr_ports && sig_wr_clk_enable.is_fully_const());
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@ -193,14 +193,14 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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log_assert(sig_wr_data.size() == wr_ports * memory->width);
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log_assert(sig_wr_en.size() == wr_ports * memory->width);
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mem->parameters["\\WR_PORTS"] = Const(wr_ports);
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mem->parameters["\\WR_CLK_ENABLE"] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
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mem->parameters["\\WR_CLK_POLARITY"] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
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mem->parameters[ID::WR_PORTS] = Const(wr_ports);
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mem->parameters[ID::WR_CLK_ENABLE] = wr_ports ? sig_wr_clk_enable.as_const() : State::S0;
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mem->parameters[ID::WR_CLK_POLARITY] = wr_ports ? sig_wr_clk_polarity.as_const() : State::S0;
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mem->setPort("\\WR_CLK", sig_wr_clk);
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mem->setPort("\\WR_ADDR", sig_wr_addr);
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mem->setPort("\\WR_DATA", sig_wr_data);
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mem->setPort("\\WR_EN", sig_wr_en);
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mem->setPort(ID::WR_CLK, sig_wr_clk);
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mem->setPort(ID::WR_ADDR, sig_wr_addr);
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mem->setPort(ID::WR_DATA, sig_wr_data);
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mem->setPort(ID::WR_EN, sig_wr_en);
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log_assert(sig_rd_clk.size() == rd_ports);
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log_assert(sig_rd_clk_enable.size() == rd_ports && sig_rd_clk_enable.is_fully_const());
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@ -208,15 +208,15 @@ Cell *handle_memory(Module *module, RTLIL::Memory *memory)
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log_assert(sig_rd_addr.size() == rd_ports * addr_bits);
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log_assert(sig_rd_data.size() == rd_ports * memory->width);
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mem->parameters["\\RD_PORTS"] = Const(rd_ports);
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mem->parameters["\\RD_CLK_ENABLE"] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
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mem->parameters["\\RD_CLK_POLARITY"] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
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mem->parameters["\\RD_TRANSPARENT"] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
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mem->parameters[ID::RD_PORTS] = Const(rd_ports);
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mem->parameters[ID::RD_CLK_ENABLE] = rd_ports ? sig_rd_clk_enable.as_const() : State::S0;
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mem->parameters[ID::RD_CLK_POLARITY] = rd_ports ? sig_rd_clk_polarity.as_const() : State::S0;
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mem->parameters[ID::RD_TRANSPARENT] = rd_ports ? sig_rd_transparent.as_const() : State::S0;
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mem->setPort("\\RD_CLK", sig_rd_clk);
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mem->setPort("\\RD_ADDR", sig_rd_addr);
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mem->setPort("\\RD_DATA", sig_rd_data);
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mem->setPort("\\RD_EN", sig_rd_en);
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mem->setPort(ID::RD_CLK, sig_rd_clk);
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mem->setPort(ID::RD_ADDR, sig_rd_addr);
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mem->setPort(ID::RD_DATA, sig_rd_data);
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mem->setPort(ID::RD_EN, sig_rd_en);
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// Copy attributes from RTLIL memory to $mem
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for (auto attr : memory->attributes)
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