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https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
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parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -81,10 +81,10 @@ struct FsmOpt
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{
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RTLIL::SigBit bit = sig.as_bit();
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if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
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if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0)
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return false;
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char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
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char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str());
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for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
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if (tok[0] && bit.offset == atoi(tok)) {
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free(str);
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@ -98,7 +98,7 @@ struct FsmOpt
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void opt_const_and_unused_inputs()
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{
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RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
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RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
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std::vector<bool> ctrl_in_used(ctrl_in.size());
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std::vector<FsmData::transition_t> new_transition_table;
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@ -119,15 +119,15 @@ struct FsmOpt
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for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
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if (!ctrl_in_used[i]) {
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log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
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log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
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for (auto &tr : new_transition_table) {
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RTLIL::SigSpec tmp(tr.ctrl_in);
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tmp.remove(i, 1);
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tr.ctrl_in = tmp.as_const();
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}
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RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
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RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
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new_ctrl_in.remove(i, 1);
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cell->setPort("\\CTRL_IN", new_ctrl_in);
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cell->setPort(ID::CTRL_IN, new_ctrl_in);
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fsm_data.num_inputs--;
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}
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}
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@ -139,12 +139,12 @@ struct FsmOpt
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void opt_unused_outputs()
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{
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for (int i = 0; i < fsm_data.num_outputs; i++) {
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RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
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RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
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if (signal_is_unused(sig)) {
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log(" Removing unused output signal %s.\n", log_signal(sig));
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RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
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RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
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new_ctrl_out.remove(i, 1);
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cell->setPort("\\CTRL_OUT", new_ctrl_out);
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cell->setPort(ID::CTRL_OUT, new_ctrl_out);
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for (auto &tr : fsm_data.transition_table) {
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RTLIL::SigSpec tmp(tr.ctrl_out);
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tmp.remove(i, 1);
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@ -158,7 +158,7 @@ struct FsmOpt
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void opt_alias_inputs()
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{
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RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
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RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
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for (int i = 0; i < ctrl_in.size(); i++)
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for (int j = i+1; j < ctrl_in.size(); j++)
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@ -195,8 +195,8 @@ struct FsmOpt
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void opt_feedback_inputs()
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{
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RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
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RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
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RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
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RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT];
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for (int j = 0; j < ctrl_out.size(); j++)
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for (int i = 0; i < ctrl_in.size(); i++)
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@ -340,12 +340,10 @@ struct FsmOptPass : public Pass {
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log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules_) {
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if (design->selected(mod_it.second))
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for (auto &cell_it : mod_it.second->cells_)
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
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FsmData::optimize_fsm(cell_it.second, mod_it.second);
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}
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == ID($fsm))
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FsmData::optimize_fsm(cell, mod);
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}
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} FsmOptPass;
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