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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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38
passes/fsm/fsm_expand.cc
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@ -47,10 +47,10 @@ struct FsmExpand
bool is_cell_merge_candidate(RTLIL::Cell *cell)
{
if (full_mode || cell->type == "$_MUX_")
if (full_mode || cell->type == ID($_MUX_))
return true;
if (cell->type.in("$mux", "$pmux"))
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->getPort(ID::A).size() < 2)
return true;
@ -81,8 +81,8 @@ struct FsmExpand
new_signals.sort_and_unify();
new_signals.remove_const();
new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
if (new_signals.size() > 3)
return false;
@ -94,10 +94,10 @@ struct FsmExpand
{
std::vector<RTLIL::Cell*> cell_list;
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
cell_list.push_back(c);
for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
cell_list.push_back(c);
current_set.clear();
@ -123,14 +123,14 @@ struct FsmExpand
if (already_optimized)
return;
int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
if (trans_num > limit_transitions)
{
log(" grown transition table to %d entries -> optimize.\n", trans_num);
FsmData::optimize_fsm(fsm_cell, module);
already_optimized = true;
trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
log(" transition table size after optimizaton: %d\n", trans_num);
limit_transitions = 16 * trans_num;
}
@ -178,14 +178,14 @@ struct FsmExpand
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size();
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
new_ctrl_in.append(input_sig);
fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size();
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
new_ctrl_out.append(output_sig);
fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
@ -246,7 +246,7 @@ struct FsmExpand
log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
already_optimized = false;
limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int();
limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
for (create_current_set(); current_set.size() > 0; create_current_set()) {
for (auto c : current_set)
@ -295,15 +295,13 @@ struct FsmExpandPass : public Pass {
}
extra_args(args, argidx, design);
for (auto &mod_it : design->modules_) {
if (!design->selected(mod_it.second))
continue;
for (auto mod : design->selected_modules()) {
std::vector<RTLIL::Cell*> fsm_cells;
for (auto &cell_it : mod_it.second->cells_)
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
fsm_cells.push_back(cell_it.second);
for (auto cell : mod->selected_cells())
if (cell->type == ID($fsm))
fsm_cells.push_back(cell);
for (auto c : fsm_cells) {
FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
FsmExpand fsm_expand(c, design, mod, full_mode);
fsm_expand.execute();
}
}