mirror of
https://github.com/YosysHQ/yosys
synced 2025-07-24 13:18:56 +00:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -55,7 +55,7 @@ ret_false:
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sig2driver.find(sig, cellport_list);
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for (auto &cellport : cellport_list)
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{
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if ((cellport.first->type != "$mux" && cellport.first->type != "$pmux") || cellport.second != ID::Y) {
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if ((cellport.first->type != ID($mux) && cellport.first->type != ID($pmux)) || cellport.second != ID::Y) {
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goto ret_false;
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}
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@ -99,7 +99,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
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RTLIL::Cell *cell = cellport.first;
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if (muxtree_cells.count(cell) > 0)
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continue;
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if (cell->type == "$logic_not" && assign_map(cell->getPort(ID::A)) == sig)
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if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
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continue;
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if (cellport.second != ID::A && cellport.second != ID::B)
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return false;
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@ -122,7 +122,7 @@ static void detect_fsm(RTLIL::Wire *wire)
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{
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bool has_fsm_encoding_attr = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() != "none";
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bool has_fsm_encoding_none = wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes.at(ID::fsm_encoding).decode_string() == "none";
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bool has_init_attr = wire->attributes.count("\\init") > 0;
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bool has_init_attr = wire->attributes.count(ID::init) > 0;
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bool is_module_port = sig_at_port.check_any(assign_map(RTLIL::SigSpec(wire)));
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bool looks_like_state_reg = false, looks_like_good_state_reg = false;
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bool is_self_resetting = false;
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@ -143,13 +143,13 @@ static void detect_fsm(RTLIL::Wire *wire)
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for (auto &cellport : cellport_list)
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{
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if ((cellport.first->type != "$dff" && cellport.first->type != "$adff") || cellport.second != "\\Q")
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if ((cellport.first->type != ID($dff) && cellport.first->type != ID($adff)) || cellport.second != ID::Q)
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continue;
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muxtree_cells.clear();
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pool<Cell*> recursion_monitor;
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RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort("\\Q"));
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RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort("\\D"));
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RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
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RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
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dict<RTLIL::SigSpec, bool> mux_tree_cache;
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if (sig_q != assign_map(wire))
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@ -173,10 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire)
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RTLIL::Cell *cell = cellport.first;
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bool set_output = false, clr_output = false;
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if (cell->type.in("$ne", "$reduce_or", "$reduce_bool"))
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if (cell->type.in(ID($ne), ID($reduce_or), ID($reduce_bool)))
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set_output = true;
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if (cell->type.in("$eq", "$logic_not", "$reduce_and"))
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if (cell->type.in(ID($eq), ID($logic_not), ID($reduce_and)))
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clr_output = true;
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if (set_output || clr_output) {
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@ -284,38 +284,34 @@ struct FsmDetectPass : public Pass {
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ct.setup_stdcells();
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ct.setup_stdcells_mem();
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for (auto &mod_it : design->modules_)
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for (auto mod : design->selected_modules())
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{
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if (!design->selected(mod_it.second))
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continue;
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module = mod_it.second;
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module = mod;
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assign_map.set(module);
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sig2driver.clear();
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sig2user.clear();
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sig_at_port.clear();
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for (auto &cell_it : module->cells_)
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for (auto &conn_it : cell_it.second->connections()) {
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if (ct.cell_output(cell_it.second->type, conn_it.first) || !ct.cell_known(cell_it.second->type)) {
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for (auto cell : module->cells())
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for (auto &conn_it : cell->connections()) {
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if (ct.cell_output(cell->type, conn_it.first) || !ct.cell_known(cell->type)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2driver.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
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sig2driver.insert(sig, sig2driver_entry_t(cell, conn_it.first));
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}
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if (!ct.cell_known(cell_it.second->type) || ct.cell_input(cell_it.second->type, conn_it.first)) {
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if (!ct.cell_known(cell->type) || ct.cell_input(cell->type, conn_it.first)) {
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RTLIL::SigSpec sig = conn_it.second;
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assign_map.apply(sig);
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sig2user.insert(sig, sig2driver_entry_t(cell_it.second, conn_it.first));
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sig2user.insert(sig, sig2driver_entry_t(cell, conn_it.first));
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}
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}
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for (auto &wire_it : module->wires_)
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if (wire_it.second->port_id != 0)
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sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
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for (auto wire : module->wires())
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if (wire->port_id != 0)
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sig_at_port.add(assign_map(wire));
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for (auto &wire_it : module->wires_)
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if (design->selected(module, wire_it.second))
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detect_fsm(wire_it.second);
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for (auto wire : module->selected_wires())
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detect_fsm(wire);
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}
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assign_map.clear();
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@ -47,10 +47,10 @@ struct FsmExpand
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bool is_cell_merge_candidate(RTLIL::Cell *cell)
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{
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if (full_mode || cell->type == "$_MUX_")
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if (full_mode || cell->type == ID($_MUX_))
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return true;
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if (cell->type.in("$mux", "$pmux"))
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if (cell->type.in(ID($mux), ID($pmux)))
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if (cell->getPort(ID::A).size() < 2)
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return true;
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@ -81,8 +81,8 @@ struct FsmExpand
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new_signals.sort_and_unify();
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new_signals.remove_const();
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_IN")));
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new_signals.remove(assign_map(fsm_cell->getPort("\\CTRL_OUT")));
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new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
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new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
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if (new_signals.size() > 3)
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return false;
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@ -94,10 +94,10 @@ struct FsmExpand
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{
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std::vector<RTLIL::Cell*> cell_list;
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for (auto c : sig2driver.find(assign_map(fsm_cell->getPort("\\CTRL_IN"))))
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for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
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cell_list.push_back(c);
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for (auto c : sig2user.find(assign_map(fsm_cell->getPort("\\CTRL_OUT"))))
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for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
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cell_list.push_back(c);
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current_set.clear();
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@ -123,14 +123,14 @@ struct FsmExpand
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if (already_optimized)
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return;
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int trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
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int trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
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if (trans_num > limit_transitions)
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{
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log(" grown transition table to %d entries -> optimize.\n", trans_num);
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FsmData::optimize_fsm(fsm_cell, module);
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already_optimized = true;
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trans_num = fsm_cell->parameters["\\TRANS_NUM"].as_int();
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trans_num = fsm_cell->parameters[ID::TRANS_NUM].as_int();
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log(" transition table size after optimizaton: %d\n", trans_num);
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limit_transitions = 16 * trans_num;
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}
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@ -178,14 +178,14 @@ struct FsmExpand
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fsm_data.copy_from_cell(fsm_cell);
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fsm_data.num_inputs += input_sig.size();
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RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort("\\CTRL_IN");
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RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
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new_ctrl_in.append(input_sig);
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fsm_cell->setPort("\\CTRL_IN", new_ctrl_in);
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fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
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fsm_data.num_outputs += output_sig.size();
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RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
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RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
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new_ctrl_out.append(output_sig);
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fsm_cell->setPort("\\CTRL_OUT", new_ctrl_out);
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fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
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if (GetSize(input_sig) > 10)
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log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",
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@ -246,7 +246,7 @@ struct FsmExpand
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log("Expanding FSM `%s' from module `%s':\n", fsm_cell->name.c_str(), module->name.c_str());
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already_optimized = false;
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limit_transitions = 16 * fsm_cell->parameters["\\TRANS_NUM"].as_int();
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limit_transitions = 16 * fsm_cell->parameters[ID::TRANS_NUM].as_int();
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for (create_current_set(); current_set.size() > 0; create_current_set()) {
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for (auto c : current_set)
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@ -295,15 +295,13 @@ struct FsmExpandPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules_) {
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if (!design->selected(mod_it.second))
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continue;
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for (auto mod : design->selected_modules()) {
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std::vector<RTLIL::Cell*> fsm_cells;
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for (auto &cell_it : mod_it.second->cells_)
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
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fsm_cells.push_back(cell_it.second);
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for (auto cell : mod->selected_cells())
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if (cell->type == ID($fsm))
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fsm_cells.push_back(cell);
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for (auto c : fsm_cells) {
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FsmExpand fsm_expand(c, design, mod_it.second, full_mode);
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FsmExpand fsm_expand(c, design, mod, full_mode);
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fsm_expand.execute();
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}
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}
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@ -57,7 +57,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
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std::string kiss_name;
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size_t i;
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attr_it = cell->attributes.find("\\fsm_export");
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attr_it = cell->attributes.find(ID::fsm_export);
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if (!filename.empty()) {
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kiss_name.assign(filename);
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} else if (attr_it != cell->attributes.end() && attr_it->second.decode_string() != "") {
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@ -173,16 +173,15 @@ struct FsmExportPass : public Pass {
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}
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extra_args(args, argidx, design);
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto &cell_it : mod_it.second->cells_)
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if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
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attr_it = cell_it.second->attributes.find("\\fsm_export");
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if (!flag_noauto || (attr_it != cell_it.second->attributes.end())) {
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write_kiss2(mod_it.second, cell_it.second, filename, flag_origenc);
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filename.clear();
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}
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == ID($fsm)) {
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attr_it = cell->attributes.find(ID::fsm_export);
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if (!flag_noauto || (attr_it != cell->attributes.end())) {
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write_kiss2(mod, cell, filename, flag_origenc);
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filename.clear();
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}
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}
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}
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} FsmExportPass;
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@ -70,7 +70,7 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
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for (auto &cellport : cellport_list)
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{
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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if ((cell->type != "$mux" && cell->type != "$pmux") || cellport.second != ID::Y) {
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if ((cell->type != ID($mux) && cell->type != ID($pmux)) || cellport.second != ID::Y) {
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log(" unexpected cell type %s (%s) found in state selection tree.\n", cell->type.c_str(), cell->name.c_str());
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return false;
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}
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@ -272,17 +272,17 @@ static void extract_fsm(RTLIL::Wire *wire)
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sig2driver.find(dff_out, cellport_list);
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for (auto &cellport : cellport_list) {
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RTLIL::Cell *cell = module->cells_.at(cellport.first);
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if ((cell->type != "$dff" && cell->type != "$adff") || cellport.second != "\\Q")
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if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
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continue;
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log(" found %s cell for state register: %s\n", cell->type.c_str(), cell->name.c_str());
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RTLIL::SigSpec sig_q = assign_map(cell->getPort("\\Q"));
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RTLIL::SigSpec sig_d = assign_map(cell->getPort("\\D"));
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clk = cell->getPort("\\CLK");
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clk_polarity = cell->parameters["\\CLK_POLARITY"].as_bool();
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if (cell->type == "$adff") {
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arst = cell->getPort("\\ARST");
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arst_polarity = cell->parameters["\\ARST_POLARITY"].as_bool();
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reset_state = cell->parameters["\\ARST_VALUE"];
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RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
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RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
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clk = cell->getPort(ID::CLK);
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clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
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if (cell->type == ID($adff)) {
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arst = cell->getPort(ID::ARST);
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arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
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reset_state = cell->parameters[ID::ARST_VALUE];
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}
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sig_q.replace(dff_out, sig_d, &dff_in);
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break;
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@ -368,14 +368,14 @@ static void extract_fsm(RTLIL::Wire *wire)
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// create fsm cell
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RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), "$fsm");
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fsm_cell->setPort("\\CLK", clk);
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fsm_cell->setPort("\\ARST", arst);
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fsm_cell->parameters["\\CLK_POLARITY"] = clk_polarity ? State::S1 : State::S0;
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fsm_cell->parameters["\\ARST_POLARITY"] = arst_polarity ? State::S1 : State::S0;
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fsm_cell->setPort("\\CTRL_IN", ctrl_in);
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fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
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fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
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RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name.c_str(), autoidx++), ID($fsm));
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fsm_cell->setPort(ID::CLK, clk);
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fsm_cell->setPort(ID::ARST, arst);
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fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
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fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
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fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
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fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
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fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
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fsm_cell->attributes = wire->attributes;
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fsm_data.copy_to_cell(fsm_cell);
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@ -424,12 +424,9 @@ struct FsmExtractPass : public Pass {
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CellTypes ct(design);
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for (auto &mod_it : design->modules_)
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for (auto mod : design->selected_modules())
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{
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if (!design->selected(mod_it.second))
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continue;
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module = mod_it.second;
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module = mod;
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assign_map.set(module);
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sig2driver.clear();
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@ -449,7 +446,7 @@ struct FsmExtractPass : public Pass {
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sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
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}
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}
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if (cell->type == "$pmux") {
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if (cell->type == ID($pmux)) {
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RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
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for (auto &bit1 : sel_sig)
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for (auto &bit2 : sel_sig)
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@ -459,10 +456,9 @@ struct FsmExtractPass : public Pass {
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}
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std::vector<RTLIL::Wire*> wire_list;
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for (auto &wire_it : module->wires_)
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if (wire_it.second->attributes.count(ID::fsm_encoding) > 0 && wire_it.second->attributes[ID::fsm_encoding].decode_string() != "none")
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if (design->selected(module, wire_it.second))
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wire_list.push_back(wire_it.second);
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for (auto wire : module->selected_wires())
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if (wire->attributes.count(ID::fsm_encoding) > 0 && wire->attributes[ID::fsm_encoding].decode_string() != "none")
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wire_list.push_back(wire);
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for (auto wire : wire_list)
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extract_fsm(wire);
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}
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@ -46,16 +46,15 @@ struct FsmInfoPass : public Pass {
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log_header(design, "Executing FSM_INFO pass (dumping all available information on FSM cells).\n");
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules_)
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if (design->selected(mod_it.second))
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for (auto &cell_it : mod_it.second->cells_)
|
||||
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second)) {
|
||||
log("\n");
|
||||
log("FSM `%s' from module `%s':\n", cell_it.second->name.c_str(), mod_it.first.c_str());
|
||||
FsmData fsm_data;
|
||||
fsm_data.copy_from_cell(cell_it.second);
|
||||
fsm_data.log_info(cell_it.second);
|
||||
}
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm)) {
|
||||
log("\n");
|
||||
log("FSM `%s' from module `%s':\n", log_id(cell), log_id(mod));
|
||||
FsmData fsm_data;
|
||||
fsm_data.copy_from_cell(cell);
|
||||
fsm_data.log_info(cell);
|
||||
}
|
||||
}
|
||||
} FsmInfoPass;
|
||||
|
||||
|
|
|
|||
|
|
@ -74,15 +74,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
|
||||
and_sig.append(RTLIL::SigSpec(eq_wire));
|
||||
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
|
||||
eq_cell->setPort(ID::A, eq_sig_a);
|
||||
eq_cell->setPort(ID::B, eq_sig_b);
|
||||
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
|
||||
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
|
||||
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
|
||||
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(eq_sig_a.size());
|
||||
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(eq_sig_b.size());
|
||||
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
|
||||
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
|
||||
eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(eq_sig_b.size());
|
||||
eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
|
||||
}
|
||||
|
||||
std::set<int> complete_in_state_cache = it.second;
|
||||
|
|
@ -102,12 +102,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
|
||||
and_sig.append(RTLIL::SigSpec(or_wire));
|
||||
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
|
||||
or_cell->setPort(ID::A, or_sig);
|
||||
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
|
||||
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
|
||||
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(or_sig.size());
|
||||
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
|
||||
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -118,15 +118,15 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
|
||||
cases_vector.append(RTLIL::SigSpec(and_wire));
|
||||
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$and");
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
|
||||
and_cell->setPort(ID::A, and_sig.extract(0, 1));
|
||||
and_cell->setPort(ID::B, and_sig.extract(1, 1));
|
||||
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
|
||||
and_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
|
||||
and_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
|
||||
and_cell->parameters["\\A_WIDTH"] = RTLIL::Const(1);
|
||||
and_cell->parameters["\\B_WIDTH"] = RTLIL::Const(1);
|
||||
and_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
|
||||
and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
|
||||
and_cell->parameters[ID::B_WIDTH] = RTLIL::Const(1);
|
||||
and_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
|
|
@ -141,12 +141,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
|
|||
}
|
||||
|
||||
if (cases_vector.size() > 1) {
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_ID, "$reduce_or");
|
||||
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
|
||||
or_cell->setPort(ID::A, cases_vector);
|
||||
or_cell->setPort(ID::Y, output);
|
||||
or_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
|
||||
or_cell->parameters["\\A_WIDTH"] = RTLIL::Const(cases_vector.size());
|
||||
or_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
|
||||
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
|
||||
} else if (cases_vector.size() == 1) {
|
||||
module->connect(RTLIL::SigSig(output, cases_vector));
|
||||
} else {
|
||||
|
|
@ -161,31 +161,31 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
|
|||
FsmData fsm_data;
|
||||
fsm_data.copy_from_cell(fsm_cell);
|
||||
|
||||
RTLIL::SigSpec ctrl_in = fsm_cell->getPort("\\CTRL_IN");
|
||||
RTLIL::SigSpec ctrl_out = fsm_cell->getPort("\\CTRL_OUT");
|
||||
RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
|
||||
RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
|
||||
|
||||
// create state register
|
||||
|
||||
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters["\\NAME"].decode_string()), fsm_data.state_bits);
|
||||
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
|
||||
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
|
||||
|
||||
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
|
||||
if (fsm_cell->getPort("\\ARST").is_fully_const()) {
|
||||
state_dff->type = "$dff";
|
||||
if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
|
||||
state_dff->type = ID($dff);
|
||||
} else {
|
||||
state_dff->type = "$adff";
|
||||
state_dff->parameters["\\ARST_POLARITY"] = fsm_cell->parameters["\\ARST_POLARITY"];
|
||||
state_dff->parameters["\\ARST_VALUE"] = fsm_data.state_table[fsm_data.reset_state];
|
||||
for (auto &bit : state_dff->parameters["\\ARST_VALUE"].bits)
|
||||
state_dff->type = ID($adff);
|
||||
state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
|
||||
state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
|
||||
for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits)
|
||||
if (bit != RTLIL::State::S1)
|
||||
bit = RTLIL::State::S0;
|
||||
state_dff->setPort("\\ARST", fsm_cell->getPort("\\ARST"));
|
||||
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
|
||||
}
|
||||
state_dff->parameters["\\WIDTH"] = RTLIL::Const(fsm_data.state_bits);
|
||||
state_dff->parameters["\\CLK_POLARITY"] = fsm_cell->parameters["\\CLK_POLARITY"];
|
||||
state_dff->setPort("\\CLK", fsm_cell->getPort("\\CLK"));
|
||||
state_dff->setPort("\\D", RTLIL::SigSpec(next_state_wire));
|
||||
state_dff->setPort("\\Q", RTLIL::SigSpec(state_wire));
|
||||
state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
|
||||
state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
|
||||
state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
|
||||
state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
|
||||
state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
|
||||
|
||||
// decode state register
|
||||
|
||||
|
|
@ -212,20 +212,20 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
|
|||
{
|
||||
encoding_is_onehot = false;
|
||||
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, "$eq");
|
||||
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
|
||||
eq_cell->setPort(ID::A, sig_a);
|
||||
eq_cell->setPort(ID::B, sig_b);
|
||||
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
|
||||
eq_cell->parameters["\\A_SIGNED"] = RTLIL::Const(false);
|
||||
eq_cell->parameters["\\B_SIGNED"] = RTLIL::Const(false);
|
||||
eq_cell->parameters["\\A_WIDTH"] = RTLIL::Const(sig_a.size());
|
||||
eq_cell->parameters["\\B_WIDTH"] = RTLIL::Const(sig_b.size());
|
||||
eq_cell->parameters["\\Y_WIDTH"] = RTLIL::Const(1);
|
||||
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
|
||||
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
|
||||
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
|
||||
eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(sig_b.size());
|
||||
eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
|
||||
}
|
||||
}
|
||||
|
||||
if (encoding_is_onehot)
|
||||
state_wire->set_bool_attribute("\\onehot");
|
||||
state_wire->set_bool_attribute(ID::onehot);
|
||||
|
||||
// generate next_state signal
|
||||
|
||||
|
|
@ -285,13 +285,13 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
|
|||
}
|
||||
}
|
||||
|
||||
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, "$pmux");
|
||||
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
|
||||
mux_cell->setPort(ID::A, sig_a);
|
||||
mux_cell->setPort(ID::B, sig_b);
|
||||
mux_cell->setPort(ID::S, sig_s);
|
||||
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
|
||||
mux_cell->parameters["\\WIDTH"] = RTLIL::Const(sig_a.size());
|
||||
mux_cell->parameters["\\S_WIDTH"] = RTLIL::Const(sig_s.size());
|
||||
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
|
||||
mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -336,15 +336,13 @@ struct FsmMapPass : public Pass {
|
|||
log_header(design, "Executing FSM_MAP pass (mapping FSMs to basic logic).\n");
|
||||
extra_args(args, 1, design);
|
||||
|
||||
for (auto &mod_it : design->modules_) {
|
||||
if (!design->selected(mod_it.second))
|
||||
continue;
|
||||
for (auto mod : design->selected_modules()) {
|
||||
std::vector<RTLIL::Cell*> fsm_cells;
|
||||
for (auto &cell_it : mod_it.second->cells_)
|
||||
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
|
||||
fsm_cells.push_back(cell_it.second);
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
fsm_cells.push_back(cell);
|
||||
for (auto cell : fsm_cells)
|
||||
map_fsm(cell, mod_it.second);
|
||||
map_fsm(cell, mod);
|
||||
}
|
||||
}
|
||||
} FsmMapPass;
|
||||
|
|
|
|||
|
|
@ -81,10 +81,10 @@ struct FsmOpt
|
|||
{
|
||||
RTLIL::SigBit bit = sig.as_bit();
|
||||
|
||||
if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
|
||||
if (bit.wire == NULL || bit.wire->attributes.count(ID::unused_bits) == 0)
|
||||
return false;
|
||||
|
||||
char *str = strdup(bit.wire->attributes["\\unused_bits"].decode_string().c_str());
|
||||
char *str = strdup(bit.wire->attributes[ID::unused_bits].decode_string().c_str());
|
||||
for (char *tok = strtok(str, " "); tok != NULL; tok = strtok(NULL, " ")) {
|
||||
if (tok[0] && bit.offset == atoi(tok)) {
|
||||
free(str);
|
||||
|
|
@ -98,7 +98,7 @@ struct FsmOpt
|
|||
|
||||
void opt_const_and_unused_inputs()
|
||||
{
|
||||
RTLIL::SigSpec ctrl_in = cell->getPort("\\CTRL_IN");
|
||||
RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
|
||||
std::vector<bool> ctrl_in_used(ctrl_in.size());
|
||||
|
||||
std::vector<FsmData::transition_t> new_transition_table;
|
||||
|
|
@ -119,15 +119,15 @@ struct FsmOpt
|
|||
|
||||
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
|
||||
if (!ctrl_in_used[i]) {
|
||||
log(" Removing unused input signal %s.\n", log_signal(cell->getPort("\\CTRL_IN").extract(i, 1)));
|
||||
log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
|
||||
for (auto &tr : new_transition_table) {
|
||||
RTLIL::SigSpec tmp(tr.ctrl_in);
|
||||
tmp.remove(i, 1);
|
||||
tr.ctrl_in = tmp.as_const();
|
||||
}
|
||||
RTLIL::SigSpec new_ctrl_in = cell->getPort("\\CTRL_IN");
|
||||
RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
|
||||
new_ctrl_in.remove(i, 1);
|
||||
cell->setPort("\\CTRL_IN", new_ctrl_in);
|
||||
cell->setPort(ID::CTRL_IN, new_ctrl_in);
|
||||
fsm_data.num_inputs--;
|
||||
}
|
||||
}
|
||||
|
|
@ -139,12 +139,12 @@ struct FsmOpt
|
|||
void opt_unused_outputs()
|
||||
{
|
||||
for (int i = 0; i < fsm_data.num_outputs; i++) {
|
||||
RTLIL::SigSpec sig = cell->getPort("\\CTRL_OUT").extract(i, 1);
|
||||
RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
|
||||
if (signal_is_unused(sig)) {
|
||||
log(" Removing unused output signal %s.\n", log_signal(sig));
|
||||
RTLIL::SigSpec new_ctrl_out = cell->getPort("\\CTRL_OUT");
|
||||
RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
|
||||
new_ctrl_out.remove(i, 1);
|
||||
cell->setPort("\\CTRL_OUT", new_ctrl_out);
|
||||
cell->setPort(ID::CTRL_OUT, new_ctrl_out);
|
||||
for (auto &tr : fsm_data.transition_table) {
|
||||
RTLIL::SigSpec tmp(tr.ctrl_out);
|
||||
tmp.remove(i, 1);
|
||||
|
|
@ -158,7 +158,7 @@ struct FsmOpt
|
|||
|
||||
void opt_alias_inputs()
|
||||
{
|
||||
RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
|
||||
RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
|
||||
|
||||
for (int i = 0; i < ctrl_in.size(); i++)
|
||||
for (int j = i+1; j < ctrl_in.size(); j++)
|
||||
|
|
@ -195,8 +195,8 @@ struct FsmOpt
|
|||
|
||||
void opt_feedback_inputs()
|
||||
{
|
||||
RTLIL::SigSpec &ctrl_in = cell->connections_["\\CTRL_IN"];
|
||||
RTLIL::SigSpec &ctrl_out = cell->connections_["\\CTRL_OUT"];
|
||||
RTLIL::SigSpec &ctrl_in = cell->connections_[ID::CTRL_IN];
|
||||
RTLIL::SigSpec &ctrl_out = cell->connections_[ID::CTRL_OUT];
|
||||
|
||||
for (int j = 0; j < ctrl_out.size(); j++)
|
||||
for (int i = 0; i < ctrl_in.size(); i++)
|
||||
|
|
@ -340,12 +340,10 @@ struct FsmOptPass : public Pass {
|
|||
log_header(design, "Executing FSM_OPT pass (simple optimizations of FSMs).\n");
|
||||
extra_args(args, 1, design);
|
||||
|
||||
for (auto &mod_it : design->modules_) {
|
||||
if (design->selected(mod_it.second))
|
||||
for (auto &cell_it : mod_it.second->cells_)
|
||||
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
|
||||
FsmData::optimize_fsm(cell_it.second, mod_it.second);
|
||||
}
|
||||
for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
||||
if (cell->type == ID($fsm))
|
||||
FsmData::optimize_fsm(cell, mod);
|
||||
}
|
||||
} FsmOptPass;
|
||||
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
|
||||
static void fm_set_fsm_print(RTLIL::Cell *cell, RTLIL::Module *module, FsmData &fsm_data, const char *prefix, FILE *f)
|
||||
{
|
||||
std::string name = cell->parameters["\\NAME"].decode_string();
|
||||
std::string name = cell->parameters[ID::NAME].decode_string();
|
||||
|
||||
fprintf(f, "set_fsm_state_vector {");
|
||||
for (int i = fsm_data.state_bits-1; i >= 0; i--)
|
||||
|
|
@ -95,7 +95,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
|
|||
log_error("FSM encoding `%s' is not supported!\n", encoding.c_str());
|
||||
|
||||
if (encfile)
|
||||
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters["\\NAME"].decode_string()).c_str());
|
||||
fprintf(encfile, ".fsm %s %s\n", log_id(module), RTLIL::unescape_id(cell->parameters[ID::NAME].decode_string()).c_str());
|
||||
|
||||
int state_idx_counter = fsm_data.reset_state >= 0 ? 1 : 0;
|
||||
for (int i = 0; i < int(fsm_data.state_table.size()); i++)
|
||||
|
|
@ -181,11 +181,10 @@ struct FsmRecodePass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
for (auto &mod_it : design->modules_)
|
||||
if (design->selected(mod_it.second))
|
||||
for (auto &cell_it : mod_it.second->cells_)
|
||||
if (cell_it.second->type == "$fsm" && design->selected(mod_it.second, cell_it.second))
|
||||
fsm_recode(cell_it.second, mod_it.second, fm_set_fsm_file, encfile, default_encoding);
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for (auto mod : design->selected_modules())
|
||||
for (auto cell : mod->selected_cells())
|
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if (cell->type == ID($fsm))
|
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fsm_recode(cell, mod, fm_set_fsm_file, encfile, default_encoding);
|
||||
|
||||
if (fm_set_fsm_file != NULL)
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fclose(fm_set_fsm_file);
|
||||
|
|
|
|||
|
|
@ -33,31 +33,31 @@ struct FsmData
|
|||
|
||||
void copy_to_cell(RTLIL::Cell *cell)
|
||||
{
|
||||
cell->parameters["\\CTRL_IN_WIDTH"] = RTLIL::Const(num_inputs);
|
||||
cell->parameters["\\CTRL_OUT_WIDTH"] = RTLIL::Const(num_outputs);
|
||||
cell->parameters[ID::CTRL_IN_WIDTH] = RTLIL::Const(num_inputs);
|
||||
cell->parameters[ID::CTRL_OUT_WIDTH] = RTLIL::Const(num_outputs);
|
||||
|
||||
int state_num_log2 = 0;
|
||||
for (int i = state_table.size(); i > 0; i = i >> 1)
|
||||
state_num_log2++;
|
||||
state_num_log2 = max(state_num_log2, 1);
|
||||
|
||||
cell->parameters["\\STATE_BITS"] = RTLIL::Const(state_bits);
|
||||
cell->parameters["\\STATE_NUM"] = RTLIL::Const(state_table.size());
|
||||
cell->parameters["\\STATE_NUM_LOG2"] = RTLIL::Const(state_num_log2);
|
||||
cell->parameters["\\STATE_RST"] = RTLIL::Const(reset_state);
|
||||
cell->parameters["\\STATE_TABLE"] = RTLIL::Const();
|
||||
cell->parameters[ID::STATE_BITS] = RTLIL::Const(state_bits);
|
||||
cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
|
||||
cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
|
||||
cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
|
||||
cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
|
||||
|
||||
for (int i = 0; i < int(state_table.size()); i++) {
|
||||
std::vector<RTLIL::State> &bits_table = cell->parameters["\\STATE_TABLE"].bits;
|
||||
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits;
|
||||
std::vector<RTLIL::State> &bits_state = state_table[i].bits;
|
||||
bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
|
||||
}
|
||||
|
||||
cell->parameters["\\TRANS_NUM"] = RTLIL::Const(transition_table.size());
|
||||
cell->parameters["\\TRANS_TABLE"] = RTLIL::Const();
|
||||
cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
|
||||
cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
|
||||
for (int i = 0; i < int(transition_table.size()); i++)
|
||||
{
|
||||
std::vector<RTLIL::State> &bits_table = cell->parameters["\\TRANS_TABLE"].bits;
|
||||
std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits;
|
||||
transition_t &tr = transition_table[i];
|
||||
|
||||
RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
|
||||
|
|
@ -78,21 +78,21 @@ struct FsmData
|
|||
|
||||
void copy_from_cell(RTLIL::Cell *cell)
|
||||
{
|
||||
num_inputs = cell->parameters["\\CTRL_IN_WIDTH"].as_int();
|
||||
num_outputs = cell->parameters["\\CTRL_OUT_WIDTH"].as_int();
|
||||
num_inputs = cell->parameters[ID::CTRL_IN_WIDTH].as_int();
|
||||
num_outputs = cell->parameters[ID::CTRL_OUT_WIDTH].as_int();
|
||||
|
||||
state_bits = cell->parameters["\\STATE_BITS"].as_int();
|
||||
reset_state = cell->parameters["\\STATE_RST"].as_int();
|
||||
state_bits = cell->parameters[ID::STATE_BITS].as_int();
|
||||
reset_state = cell->parameters[ID::STATE_RST].as_int();
|
||||
|
||||
int state_num = cell->parameters["\\STATE_NUM"].as_int();
|
||||
int state_num_log2 = cell->parameters["\\STATE_NUM_LOG2"].as_int();
|
||||
int trans_num = cell->parameters["\\TRANS_NUM"].as_int();
|
||||
int state_num = cell->parameters[ID::STATE_NUM].as_int();
|
||||
int state_num_log2 = cell->parameters[ID::STATE_NUM_LOG2].as_int();
|
||||
int trans_num = cell->parameters[ID::TRANS_NUM].as_int();
|
||||
|
||||
if (reset_state < 0 || reset_state >= state_num)
|
||||
reset_state = -1;
|
||||
|
||||
RTLIL::Const state_table = cell->parameters["\\STATE_TABLE"];
|
||||
RTLIL::Const trans_table = cell->parameters["\\TRANS_TABLE"];
|
||||
RTLIL::Const state_table = cell->parameters[ID::STATE_TABLE];
|
||||
RTLIL::Const trans_table = cell->parameters[ID::TRANS_TABLE];
|
||||
|
||||
for (int i = 0; i < state_num; i++) {
|
||||
RTLIL::Const state_code;
|
||||
|
|
@ -134,7 +134,7 @@ struct FsmData
|
|||
{
|
||||
log("-------------------------------------\n");
|
||||
log("\n");
|
||||
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters["\\NAME"].decode_string().c_str());
|
||||
log(" Information on FSM %s (%s):\n", cell->name.c_str(), cell->parameters[ID::NAME].decode_string().c_str());
|
||||
log("\n");
|
||||
log(" Number of input signals: %3d\n", num_inputs);
|
||||
log(" Number of output signals: %3d\n", num_outputs);
|
||||
|
|
@ -142,13 +142,13 @@ struct FsmData
|
|||
|
||||
log("\n");
|
||||
log(" Input signals:\n");
|
||||
RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
|
||||
RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
|
||||
for (int i = 0; i < GetSize(sig_in); i++)
|
||||
log(" %3d: %s\n", i, log_signal(sig_in[i]));
|
||||
|
||||
log("\n");
|
||||
log(" Output signals:\n");
|
||||
RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
|
||||
RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
|
||||
for (int i = 0; i < GetSize(sig_out); i++)
|
||||
log(" %3d: %s\n", i, log_signal(sig_out[i]));
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue