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kernel: big fat patch to use more ID::*, otherwise ID(*)
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parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -42,9 +42,9 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
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}
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else {
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RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
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formal_cell->setPort(ID(A), wire);
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formal_cell->setPort(ID::A, wire);
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if(enable_name == "") {
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formal_cell->setPort(ID(EN), State::S1);
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formal_cell->setPort(ID::EN, State::S1);
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log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
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}
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else {
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@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
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if(enable_wire == nullptr)
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log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
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formal_cell->setPort(ID(EN), enable_wire);
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formal_cell->setPort(ID::EN, enable_wire);
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log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
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}
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}
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@ -212,7 +212,7 @@ struct AddPass : public Pass {
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log_assert(module != nullptr);
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if (!design->selected_whole_module(module->name))
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continue;
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if (module->get_bool_attribute("\\blackbox"))
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if (module->get_bool_attribute(ID::blackbox))
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continue;
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selected_anything = true;
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