mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-24 14:53:42 +00:00
Code Activity

kernel: big fat patch to use more ID::*, otherwise ID(*)

Browse source
This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/cmds/add.cc
View file

@ -42,9 +42,9 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID(A), wire);
formal_cell->setPort(ID::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID(EN), State::S1);
formal_cell->setPort(ID::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype.c_str(), module->name.str().c_str(), name.c_str());
}
else {
@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name.c_str());
formal_cell->setPort(ID(EN), enable_wire);
formal_cell->setPort(ID::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype.c_str(), module->name.str().c_str(), name.c_str(), module->name.str().c_str(), enable_name.c_str());
}
}
@ -212,7 +212,7 @@ struct AddPass : public Pass {
log_assert(module != nullptr);
if (!design->selected_whole_module(module->name))
continue;
if (module->get_bool_attribute("\\blackbox"))
if (module->get_bool_attribute(ID::blackbox))
continue;
selected_anything = true;

2
passes/cmds/blackbox.cc
View file

@ -73,7 +73,7 @@ struct BlackboxPass : public Pass {
module->remove(remove_wires);
module->set_bool_attribute("\\blackbox");
module->set_bool_attribute(ID::blackbox);
}
}
} BlackboxPass;

4
passes/cmds/bugpoint.cc
View file

@ -155,7 +155,7 @@ struct BugpointPass : public Pass {
for (auto wire : mod->wires())
{
if (!stage2 && wire->get_bool_attribute("$bugpoint"))
if (!stage2 && wire->get_bool_attribute(ID($bugpoint)))
continue;
if (wire->port_input || wire->port_output)
@ -220,7 +220,7 @@ struct BugpointPass : public Pass {
{
log("Trying to expose cell port %s.%s.%s as module port.\n", mod->name.c_str(), cell->name.c_str(), it.first.c_str());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
wire->set_bool_attribute("$bugpoint");
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);
cell->unsetPort(it.first);

88
passes/cmds/check.cc
View file

@ -99,47 +99,47 @@ struct CheckPass : public Pass {
log_header(design, "Executing CHECK pass (checking for obvious problems).\n");
pool<IdString> fftypes;
fftypes.insert("$sr");
fftypes.insert("$ff");
fftypes.insert("$dff");
fftypes.insert("$dffe");
fftypes.insert("$dffsr");
fftypes.insert("$adff");
fftypes.insert("$dlatch");
fftypes.insert("$dlatchsr");
fftypes.insert("$_DFFE_NN_");
fftypes.insert("$_DFFE_NP_");
fftypes.insert("$_DFFE_PN_");
fftypes.insert("$_DFFE_PP_");
fftypes.insert("$_DFFSR_NNN_");
fftypes.insert("$_DFFSR_NNP_");
fftypes.insert("$_DFFSR_NPN_");
fftypes.insert("$_DFFSR_NPP_");
fftypes.insert("$_DFFSR_PNN_");
fftypes.insert("$_DFFSR_PNP_");
fftypes.insert("$_DFFSR_PPN_");
fftypes.insert("$_DFFSR_PPP_");
fftypes.insert("$_DFF_NN0_");
fftypes.insert("$_DFF_NN1_");
fftypes.insert("$_DFF_NP0_");
fftypes.insert("$_DFF_NP1_");
fftypes.insert("$_DFF_N_");
fftypes.insert("$_DFF_PN0_");
fftypes.insert("$_DFF_PN1_");
fftypes.insert("$_DFF_PP0_");
fftypes.insert("$_DFF_PP1_");
fftypes.insert("$_DFF_P_");
fftypes.insert("$_DLATCHSR_NNN_");
fftypes.insert("$_DLATCHSR_NNP_");
fftypes.insert("$_DLATCHSR_NPN_");
fftypes.insert("$_DLATCHSR_NPP_");
fftypes.insert("$_DLATCHSR_PNN_");
fftypes.insert("$_DLATCHSR_PNP_");
fftypes.insert("$_DLATCHSR_PPN_");
fftypes.insert("$_DLATCHSR_PPP_");
fftypes.insert("$_DLATCH_N_");
fftypes.insert("$_DLATCH_P_");
fftypes.insert("$_FF_");
fftypes.insert(ID($sr));
fftypes.insert(ID($ff));
fftypes.insert(ID($dff));
fftypes.insert(ID($dffe));
fftypes.insert(ID($dffsr));
fftypes.insert(ID($adff));
fftypes.insert(ID($dlatch));
fftypes.insert(ID($dlatchsr));
fftypes.insert(ID($_DFFE_NN_));
fftypes.insert(ID($_DFFE_NP_));
fftypes.insert(ID($_DFFE_PN_));
fftypes.insert(ID($_DFFE_PP_));
fftypes.insert(ID($_DFFSR_NNN_));
fftypes.insert(ID($_DFFSR_NNP_));
fftypes.insert(ID($_DFFSR_NPN_));
fftypes.insert(ID($_DFFSR_NPP_));
fftypes.insert(ID($_DFFSR_PNN_));
fftypes.insert(ID($_DFFSR_PNP_));
fftypes.insert(ID($_DFFSR_PPN_));
fftypes.insert(ID($_DFFSR_PPP_));
fftypes.insert(ID($_DFF_NN0_));
fftypes.insert(ID($_DFF_NN1_));
fftypes.insert(ID($_DFF_NP0_));
fftypes.insert(ID($_DFF_NP1_));
fftypes.insert(ID($_DFF_N_));
fftypes.insert(ID($_DFF_PN0_));
fftypes.insert(ID($_DFF_PN1_));
fftypes.insert(ID($_DFF_PP0_));
fftypes.insert(ID($_DFF_PP1_));
fftypes.insert(ID($_DFF_P_));
fftypes.insert(ID($_DLATCHSR_NNN_));
fftypes.insert(ID($_DLATCHSR_NNP_));
fftypes.insert(ID($_DLATCHSR_NPN_));
fftypes.insert(ID($_DLATCHSR_NPP_));
fftypes.insert(ID($_DLATCHSR_PNN_));
fftypes.insert(ID($_DLATCHSR_PNP_));
fftypes.insert(ID($_DLATCHSR_PPN_));
fftypes.insert(ID($_DLATCHSR_PPP_));
fftypes.insert(ID($_DLATCH_N_));
fftypes.insert(ID($_DLATCH_P_));
fftypes.insert(ID($_FF_));
for (auto module : design->selected_whole_modules_warn())
{
@ -202,8 +202,8 @@ struct CheckPass : public Pass {
if (wire->port_input && !wire->port_output)
for (auto bit : sigmap(wire))
if (bit.wire) wire_drivers_count[bit]++;
if (wire->attributes.count("\\init")) {
Const initval = wire->attributes.at("\\init");
if (wire->attributes.count(ID::init)) {
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initval) && i < GetSize(wire); i++)
if (initval[i] == State::S0 || initval[i] == State::S1)
init_bits.insert(sigmap(SigBit(wire, i)));
@ -245,7 +245,7 @@ struct CheckPass : public Pass {
if (fftypes.count(cell->type) == 0)
continue;
for (auto bit : sigmap(cell->getPort("\\Q")))
for (auto bit : sigmap(cell->getPort(ID::Q)))
init_bits.erase(bit);
}

74
passes/cmds/chformal.cc
View file

@ -77,23 +77,23 @@ struct ChformalPass : public Pass {
for (argidx = 1; argidx < args.size(); argidx++)
{
if (args[argidx] == "-assert") {
constr_types.insert("$assert");
constr_types.insert(ID($assert));
continue;
}
if (args[argidx] == "-assume") {
constr_types.insert("$assume");
constr_types.insert(ID($assume));
continue;
}
if (args[argidx] == "-live") {
constr_types.insert("$live");
constr_types.insert(ID($live));
continue;
}
if (args[argidx] == "-fair") {
constr_types.insert("$fair");
constr_types.insert(ID($fair));
continue;
}
if (args[argidx] == "-cover") {
constr_types.insert("$cover");
constr_types.insert(ID($cover));
continue;
}
if (mode == 0 && args[argidx] == "-remove") {
@ -139,11 +139,11 @@ struct ChformalPass : public Pass {
extra_args(args, argidx, design);
if (constr_types.empty()) {
constr_types.insert("$assert");
constr_types.insert("$assume");
constr_types.insert("$live");
constr_types.insert("$fair");
constr_types.insert("$cover");
constr_types.insert(ID($assert));
constr_types.insert(ID($assume));
constr_types.insert(ID($live));
constr_types.insert(ID($fair));
constr_types.insert(ID($cover));
}
if (mode == 0)
@ -171,11 +171,11 @@ struct ChformalPass : public Pass {
for (auto wire : module->wires())
{
if (wire->attributes.count("\\init") == 0)
if (wire->attributes.count(ID::init) == 0)
continue;
SigSpec initsig = sigmap(wire);
Const initval = wire->attributes.at("\\init");
Const initval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++) {
if (initval[i] == State::S0)
@ -187,17 +187,17 @@ struct ChformalPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == "$ff") {
SigSpec D = sigmap(cell->getPort("\\D"));
SigSpec Q = sigmap(cell->getPort("\\Q"));
if (cell->type == ID($ff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
}
if (cell->type == "$dff") {
SigSpec D = sigmap(cell->getPort("\\D"));
SigSpec Q = sigmap(cell->getPort("\\Q"));
SigSpec C = sigmap(cell->getPort("\\CLK"));
bool clockpol = cell->getParam("\\CLK_POLARITY").as_bool();
if (cell->type == ID($dff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec C = sigmap(cell->getPort(ID::CLK));
bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
}
@ -207,14 +207,14 @@ struct ChformalPass : public Pass {
while (true)
{
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort("\\EN"));
SigSpec EN = sigmap(cell->getPort(ID::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break;
if (!init_zero.count(EN)) {
if (cell->type == "$cover") break;
if (cell->type.in("$assert", "$assume") && !init_one.count(A)) break;
if (cell->type == ID($cover)) break;
if (cell->type.in(ID($assert), ID($assume)) && !init_one.count(A)) break;
}
const auto &A_map = ffmap.at(A);
@ -224,7 +224,7 @@ struct ChformalPass : public Pass {
break;
cell->setPort(ID::A, A_map.first);
cell->setPort("\\EN", EN_map.first);
cell->setPort(ID::EN, EN_map.first);
}
}
else
@ -234,17 +234,17 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort("\\EN");
SigSpec orig_en = cell->getPort(ID::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
new_en->attributes["\\init"] = State::S0;
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort("\\EN", new_en);
cell->setPort(ID::EN, new_en);
}
}
else
@ -254,26 +254,26 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
w->attributes["\\init"] = State::S0;
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort("\\EN", module->LogicAnd(NEW_ID, en, cell->getPort("\\EN")));
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
}
else
if (mode == 'c')
{
for (auto cell : constr_cells)
if (assert2assume && cell->type == "$assert")
cell->type = "$assume";
else if (assume2assert && cell->type == "$assume")
cell->type = "$assert";
else if (live2fair && cell->type == "$live")
cell->type = "$fair";
else if (fair2live && cell->type == "$fair")
cell->type = "$live";
if (assert2assume && cell->type == ID($assert))
cell->type = ID($assume);
else if (assume2assert && cell->type == ID($assume))
cell->type = ID($assert);
else if (live2fair && cell->type == ID($live))
cell->type = ID($fair);
else if (fair2live && cell->type == ID($fair))
cell->type = ID($live);
}
}
}

4
passes/cmds/delete.cc
View file

@ -107,8 +107,8 @@ struct DeletePass : public Pass {
for (auto &it : module->cells_) {
if (design->selected(module, it.second))
delete_cells.insert(it.second);
if (it.second->type.in("$memrd", "$memwr") &&
delete_mems.count(it.second->parameters.at("\\MEMID").decode_string()) != 0)
if (it.second->type.in(ID($memrd), ID($memwr)) &&
delete_mems.count(it.second->parameters.at(ID::MEMID).decode_string()) != 0)
delete_cells.insert(it.second);
}

2
passes/cmds/qwp.cc
View file

@ -737,7 +737,7 @@ struct QwpWorker
for (auto &node : nodes)
if (node.cell != nullptr)
node.cell->attributes["\\qwp_position"] = stringf("%f %f", node.pos, node.alt_pos);
node.cell->attributes[ID::qwp_position] = stringf("%f %f", node.pos, node.alt_pos);
vector<double> edge_lengths;
vector<double> weighted_edge_lengths;

4
passes/cmds/setattr.cc
View file

@ -159,10 +159,10 @@ struct WbflipPass : public Pass {
if (!design->selected(module))
continue;
if (module->get_bool_attribute("\\blackbox"))
if (module->get_bool_attribute(ID::blackbox))
continue;
module->set_bool_attribute("\\whitebox", !module->get_bool_attribute("\\whitebox"));
module->set_bool_attribute(ID::whitebox, !module->get_bool_attribute(ID::whitebox));
}
}
} WbflipPass;

20
passes/cmds/setundef.cc
View file

@ -360,10 +360,10 @@ struct SetundefPass : public Pass {
pool<Wire*> initwires;
pool<IdString> fftypes;
fftypes.insert("$dff");
fftypes.insert("$dffe");
fftypes.insert("$dffsr");
fftypes.insert("$adff");
fftypes.insert(ID($dff));
fftypes.insert(ID($dffe));
fftypes.insert(ID($dffsr));
fftypes.insert(ID($adff));
std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
@ -389,7 +389,7 @@ struct SetundefPass : public Pass {
if (!fftypes.count(cell->type))
continue;
for (auto bit : sigmap(cell->getPort("\\Q")))
for (auto bit : sigmap(cell->getPort(ID::Q)))
ffbits.insert(bit);
}
@ -411,7 +411,7 @@ struct SetundefPass : public Pass {
for (auto wire : initwires)
{
Const &initval = wire->attributes["\\init"];
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
for (int i = 0; i < GetSize(wire); i++) {
@ -423,7 +423,7 @@ struct SetundefPass : public Pass {
}
if (initval.is_fully_undef())
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
}
initwires.clear();
@ -439,14 +439,14 @@ struct SetundefPass : public Pass {
if (wire->name[0] == (wire_types ? '\\' : '$'))
continue;
if (!wire->attributes.count("\\init"))
if (!wire->attributes.count(ID::init))
continue;
Const &initval = wire->attributes["\\init"];
Const &initval = wire->attributes[ID::init];
initval.bits.resize(GetSize(wire), State::Sx);
if (initval.is_fully_undef()) {
wire->attributes.erase("\\init");
wire->attributes.erase(ID::init);
continue;
}

14
passes/cmds/splice.cc
View file

@ -75,10 +75,10 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
cell->parameters["\\OFFSET"] = offset;
cell->parameters["\\A_WIDTH"] = sig_a.size();
cell->parameters["\\Y_WIDTH"] = sig.size();
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
@ -132,9 +132,9 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
cell->parameters["\\A_WIDTH"] = new_sig.size();
cell->parameters["\\B_WIDTH"] = sig2.size();
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));

10
passes/cmds/splitnets.cc
View file

@ -63,14 +63,14 @@ struct SplitnetsWorker
if (wire->attributes.count(ID::src))
new_wire->attributes[ID::src] = wire->attributes.at(ID::src);
if (wire->attributes.count("\\keep"))
new_wire->attributes["\\keep"] = wire->attributes.at("\\keep");
if (wire->attributes.count(ID::keep))
new_wire->attributes[ID::keep] = wire->attributes.at(ID::keep);
if (wire->attributes.count("\\init")) {
Const old_init = wire->attributes.at("\\init"), new_init;
if (wire->attributes.count(ID::init)) {
Const old_init = wire->attributes.at(ID::init), new_init;
for (int i = offset; i < offset+width; i++)
new_init.bits.push_back(i < GetSize(old_init) ? old_init.bits.at(i) : State::Sx);
new_wire->attributes["\\init"] = new_init;
new_wire->attributes[ID::init] = new_init;
}
std::vector<RTLIL::SigBit> sigvec = RTLIL::SigSpec(new_wire).to_sigbit_vector();

34
passes/cmds/stat.cc
View file

@ -109,22 +109,22 @@ struct statdata_t
if (width_mode)
{
if (cell_type.in("$not", "$pos", "$neg",
"$logic_not", "$logic_and", "$logic_or",
"$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
"$lut", "$and", "$or", "$xor", "$xnor",
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow", "$alu")) {
if (cell_type.in(ID($not), ID($pos), ID($neg),
ID($logic_not), ID($logic_and), ID($logic_or),
ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
ID($lut), ID($and), ID($or), ID($xor), ID($xnor),
ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow), ID($alu))) {
int width_a = it.second->hasPort(ID::A) ? GetSize(it.second->getPort(ID::A)) : 0;
int width_b = it.second->hasPort(ID::B) ? GetSize(it.second->getPort(ID::B)) : 0;
int width_y = it.second->hasPort(ID::Y) ? GetSize(it.second->getPort(ID::Y)) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
else if (cell_type.in(ID($mux), ID($pmux)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Y)));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
else if (cell_type.in(ID($sr), ID($dff), ID($dffsr), ID($adff), ID($dlatch), ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort(ID::Q)));
}
if (!cell_area.empty()) {
@ -172,12 +172,12 @@ struct statdata_t
if (tech == "xilinx")
{
int lut6_cnt = num_cells_by_type["\\LUT6"];
int lut5_cnt = num_cells_by_type["\\LUT5"];
int lut4_cnt = num_cells_by_type["\\LUT4"];
int lut3_cnt = num_cells_by_type["\\LUT3"];
int lut2_cnt = num_cells_by_type["\\LUT2"];
int lut1_cnt = num_cells_by_type["\\LUT1"];
int lut6_cnt = num_cells_by_type[ID(LUT6)];
int lut5_cnt = num_cells_by_type[ID(LUT5)];
int lut4_cnt = num_cells_by_type[ID(LUT4)];
int lut3_cnt = num_cells_by_type[ID(LUT3)];
int lut2_cnt = num_cells_by_type[ID(LUT2)];
int lut1_cnt = num_cells_by_type[ID(LUT1)];
int lc_cnt = 0;
lc_cnt += lut6_cnt;
@ -235,7 +235,7 @@ struct statdata_t
if (gate_costs.count(ctype))
tran_cnt += cnum * gate_costs.at(ctype);
else if (ctype.in("$_DFF_P_", "$_DFF_N_"))
else if (ctype.in(ID($_DFF_P_), ID($_DFF_N_)))
tran_cnt += cnum * 16;
else
tran_cnt_exact = false;

4
passes/cmds/torder.cc
View file

@ -81,9 +81,9 @@ struct TorderPass : public Pass {
continue;
if (!noautostop && yosys_celltypes.cell_known(cell->type)) {
if (conn.first.in("\\Q", "\\CTRL_OUT", "\\RD_DATA"))
if (conn.first.in(ID::Q, ID::CTRL_OUT, ID::RD_DATA))
continue;
if (cell->type == "$memrd" && conn.first == "\\DATA")
if (cell->type == ID($memrd) && conn.first == ID::DATA)
continue;
}