mirror of
https://github.com/YosysHQ/yosys
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kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
112
kernel/satgen.h
112
kernel/satgen.h
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@ -224,8 +224,8 @@ struct SatGen
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void extendSignalWidth(std::vector<int> &vec_a, std::vector<int> &vec_b, RTLIL::Cell *cell, size_t y_width = 0, bool forced_signed = false)
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{
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bool is_signed = forced_signed;
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if (!forced_signed && cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters.count(ID(B_SIGNED)) > 0)
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is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
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if (!forced_signed && cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters.count(ID::B_SIGNED) > 0)
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is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
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while (vec_a.size() < vec_b.size() || vec_a.size() < y_width)
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
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while (vec_b.size() < vec_a.size() || vec_b.size() < y_width)
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@ -241,7 +241,7 @@ struct SatGen
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void extendSignalWidthUnary(std::vector<int> &vec_a, std::vector<int> &vec_y, RTLIL::Cell *cell, bool forced_signed = false)
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{
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bool is_signed = forced_signed || (cell->parameters.count(ID(A_SIGNED)) > 0 && cell->parameters[ID(A_SIGNED)].as_bool());
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bool is_signed = forced_signed || (cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool());
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while (vec_a.size() < vec_y.size())
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vec_a.push_back(is_signed && vec_a.size() > 0 ? vec_a.back() : ez->CONST_FALSE);
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while (vec_y.size() < vec_a.size())
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@ -397,8 +397,8 @@ struct SatGen
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int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
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int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
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int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0);
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int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0);
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int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
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int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
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int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
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int yy = model_undef ? ez->literal() : y;
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@ -411,8 +411,8 @@ struct SatGen
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{
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int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
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int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
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int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0);
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int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0);
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int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
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int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
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int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
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if (aoi_mode)
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@ -479,7 +479,7 @@ struct SatGen
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{
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
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std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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@ -492,7 +492,7 @@ struct SatGen
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{
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std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
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std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
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@ -508,7 +508,7 @@ struct SatGen
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{
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
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std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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@ -524,7 +524,7 @@ struct SatGen
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{
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std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
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std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
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int maybe_a = ez->CONST_TRUE;
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@ -684,7 +684,7 @@ struct SatGen
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if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
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{
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bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
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bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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@ -774,7 +774,7 @@ struct SatGen
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int extend_bit = ez->CONST_FALSE;
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if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
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if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
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extend_bit = a.back();
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while (y.size() < a.size())
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@ -792,10 +792,10 @@ struct SatGen
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shifted_a = ez->vec_shift_right(a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == ID($sshr))
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shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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shifted_a = ez->vec_shift_right(a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type.in(ID($shift), ID($shiftx)))
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shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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shifted_a = ez->vec_shift_right(a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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ez->assume(ez->vec_eq(shifted_a, yy));
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@ -807,7 +807,7 @@ struct SatGen
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std::vector<int> undef_a_shifted;
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extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
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if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID(A_SIGNED)].as_bool())
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if (!cell->type.in(ID($shift), ID($shiftx)) && cell->parameters[ID::A_SIGNED].as_bool())
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extend_bit = undef_a.back();
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while (undef_y.size() < undef_a.size())
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@ -822,13 +822,13 @@ struct SatGen
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == ID($sshr))
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID(A_SIGNED)].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, false, cell->parameters[ID::A_SIGNED].as_bool() ? undef_a.back() : ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == ID($shift))
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_FALSE, ez->CONST_FALSE);
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if (cell->type == ID($shiftx))
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID(B_SIGNED)].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
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undef_a_shifted = ez->vec_shift_right(undef_a, b, cell->parameters[ID::B_SIGNED].as_bool(), ez->CONST_TRUE, ez->CONST_TRUE);
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int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
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std::vector<int> undef_all_y_bits(undef_y.size(), undef_any_b);
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@ -945,7 +945,7 @@ struct SatGen
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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std::vector<int> a_u, b_u;
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if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
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if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
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a_u = ez->vec_ite(a.back(), ez->vec_neg(a), a);
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b_u = ez->vec_ite(b.back(), ez->vec_neg(b), b);
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} else {
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@ -971,12 +971,12 @@ struct SatGen
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std::vector<int> y_tmp = ignore_div_by_zero ? yy : ez->vec_var(y.size());
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if (cell->type == ID($div)) {
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if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
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if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
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ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(ez->XOR(a.back(), b.back()), ez->vec_neg(y_u), y_u)));
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else
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ez->assume(ez->vec_eq(y_tmp, y_u));
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} else {
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if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
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if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
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ez->assume(ez->vec_eq(y_tmp, ez->vec_ite(a.back(), ez->vec_neg(chain_buf), chain_buf)));
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else
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ez->assume(ez->vec_eq(y_tmp, chain_buf));
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@ -987,7 +987,7 @@ struct SatGen
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} else {
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std::vector<int> div_zero_result;
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if (cell->type == ID($div)) {
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if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool()) {
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if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool()) {
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std::vector<int> all_ones(y.size(), ez->CONST_TRUE);
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std::vector<int> only_first_one(y.size(), ez->CONST_FALSE);
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only_first_one.at(0) = ez->CONST_TRUE;
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@ -999,7 +999,7 @@ struct SatGen
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} else {
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int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
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div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
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if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
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if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
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else
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div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
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@ -1021,7 +1021,7 @@ struct SatGen
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> lut;
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for (auto bit : cell->getParam(ID(LUT)).bits)
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for (auto bit : cell->getParam(ID::LUT).bits)
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lut.push_back(bit == State::S1 ? ez->CONST_TRUE : ez->CONST_FALSE);
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while (GetSize(lut) < (1 << GetSize(a)))
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lut.push_back(ez->CONST_FALSE);
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@ -1070,10 +1070,10 @@ struct SatGen
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
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int width = cell->getParam(ID(WIDTH)).as_int();
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int depth = cell->getParam(ID(DEPTH)).as_int();
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int width = cell->getParam(ID::WIDTH).as_int();
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int depth = cell->getParam(ID::DEPTH).as_int();
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vector<State> table_raw = cell->getParam(ID(TABLE)).bits;
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vector<State> table_raw = cell->getParam(ID::TABLE).bits;
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while (GetSize(table_raw) < 2*width*depth)
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table_raw.push_back(State::S0);
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@ -1151,9 +1151,9 @@ struct SatGen
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{
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep);
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std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
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std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
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std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
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std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
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@ -1169,10 +1169,10 @@ struct SatGen
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{
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std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep);
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std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
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std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
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std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
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ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
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ez->assume(ez->vec_eq(undef_x, undef_y));
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@ -1185,10 +1185,10 @@ struct SatGen
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if (cell->type == ID($lcu))
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{
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std::vector<int> p = importDefSigSpec(cell->getPort(ID(P)), timestep);
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std::vector<int> g = importDefSigSpec(cell->getPort(ID(G)), timestep);
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std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
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std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
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std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
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std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
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std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
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std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
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std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
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@ -1197,10 +1197,10 @@ struct SatGen
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if (model_undef)
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{
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std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID(P)), timestep);
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std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID(G)), timestep);
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std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
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std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
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std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
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std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
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std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
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std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
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int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
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int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
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@ -1220,10 +1220,10 @@ struct SatGen
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std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
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std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
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std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
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std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
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std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
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std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep);
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std::vector<int> co = importDefSigSpec(cell->getPort(ID(CO)), timestep);
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std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
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std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
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std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
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std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
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extendSignalWidth(a, b, y, cell);
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extendSignalWidth(a, b, x, cell);
|
||||
|
|
@ -1250,12 +1250,12 @@ struct SatGen
|
|||
{
|
||||
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
|
||||
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
|
||||
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
|
||||
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep);
|
||||
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
|
||||
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
|
||||
|
||||
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
|
||||
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
|
||||
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
|
||||
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
|
||||
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
|
||||
|
||||
extendSignalWidth(undef_a, undef_b, undef_y, cell);
|
||||
extendSignalWidth(undef_a, undef_b, undef_x, cell);
|
||||
|
|
@ -1285,7 +1285,7 @@ struct SatGen
|
|||
{
|
||||
RTLIL::SigSpec a = cell->getPort(ID::A);
|
||||
RTLIL::SigSpec y = cell->getPort(ID::Y);
|
||||
ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep));
|
||||
ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1306,20 +1306,20 @@ struct SatGen
|
|||
{
|
||||
if (timestep == 1)
|
||||
{
|
||||
initial_state.add((*sigmap)(cell->getPort(ID(Q))));
|
||||
initial_state.add((*sigmap)(cell->getPort(ID::Q)));
|
||||
}
|
||||
else
|
||||
{
|
||||
std::vector<int> d = importDefSigSpec(cell->getPort(ID(D)), timestep-1);
|
||||
std::vector<int> q = importDefSigSpec(cell->getPort(ID(Q)), timestep);
|
||||
std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
|
||||
std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
|
||||
|
||||
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
|
||||
ez->assume(ez->vec_eq(d, qq));
|
||||
|
||||
if (model_undef)
|
||||
{
|
||||
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(D)), timestep-1);
|
||||
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Q)), timestep);
|
||||
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
|
||||
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
|
||||
|
||||
ez->assume(ez->vec_eq(undef_d, undef_q));
|
||||
undefGating(q, qq, undef_q);
|
||||
|
|
@ -1397,7 +1397,7 @@ struct SatGen
|
|||
{
|
||||
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
|
||||
asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
|
||||
asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
|
||||
asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
@ -1405,7 +1405,7 @@ struct SatGen
|
|||
{
|
||||
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
|
||||
assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
|
||||
assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
|
||||
assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
|
||||
return true;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue