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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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50
frontends/blif/blifparse.cc
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@ -176,7 +176,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (!strcmp(cmd, ".blackbox"))
{
module->attributes["\\blackbox"] = RTLIL::Const(1);
module->attributes[ID::blackbox] = RTLIL::Const(1);
continue;
}
@ -215,7 +215,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
vector<Cell*> remove_cells;
for (auto cell : module->cells())
if (cell->type == "$lut" && cell->getParam("\\LUT") == buffer_lut) {
if (cell->type == ID($lut) && cell->getParam(ID::LUT) == buffer_lut) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
remove_cells.push_back(cell);
}
@ -223,9 +223,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
for (auto cell : remove_cells)
module->remove(cell);
Wire *true_wire = module->wire("$true");
Wire *false_wire = module->wire("$false");
Wire *undef_wire = module->wire("$undef");
Wire *true_wire = module->wire(ID($true));
Wire *false_wire = module->wire(ID($false));
Wire *undef_wire = module->wire(ID($undef));
if (true_wire != nullptr)
module->rename(true_wire, stringf("$true$%d", ++blif_maxnum));
@ -337,7 +337,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
if (init != nullptr && (init[0] == '0' || init[0] == '1'))
blif_wire(q)->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
blif_wire(q)->attributes[ID::init] = Const(init[0] == '1' ? 1 : 0, 1);
if (clock == nullptr)
goto no_latch_clock;
@ -356,8 +356,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
} else {
cell = module->addCell(NEW_ID, dff_name);
cell->setPort("\\D", blif_wire(d));
cell->setPort("\\Q", blif_wire(q));
cell->setPort(ID::D, blif_wire(d));
cell->setPort(ID::Q, blif_wire(q));
}
}
@ -476,7 +476,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
finished_parsing_constval:
if (state == RTLIL::State::Sa)
state = RTLIL::State::S0;
if (output_sig.as_wire()->name == "$undef")
if (output_sig.as_wire()->name == ID($undef))
state = RTLIL::State::Sx;
module->connect(RTLIL::SigSig(output_sig, state));
goto continue_without_read;
@ -484,10 +484,10 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sop_mode)
{
sopcell = module->addCell(NEW_ID, "$sop");
sopcell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
sopcell->parameters["\\DEPTH"] = 0;
sopcell->parameters["\\TABLE"] = RTLIL::Const();
sopcell = module->addCell(NEW_ID, ID($sop));
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
sopcell->parameters[ID::DEPTH] = 0;
sopcell->parameters[ID::TABLE] = RTLIL::Const();
sopcell->setPort(ID::A, input_sig);
sopcell->setPort(ID::Y, output_sig);
sopmode = -1;
@ -495,12 +495,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
}
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, "$lut");
cell->parameters["\\WIDTH"] = RTLIL::Const(input_sig.size());
cell->parameters["\\LUT"] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
cell->setPort(ID::A, input_sig);
cell->setPort(ID::Y, output_sig);
lutptr = &cell->parameters.at("\\LUT");
lutptr = &cell->parameters.at(ID::LUT);
lut_default_state = RTLIL::State::Sx;
lastcell = cell;
}
@ -523,22 +523,22 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
if (sopcell)
{
log_assert(sopcell->parameters["\\WIDTH"].as_int() == input_len);
sopcell->parameters["\\DEPTH"] = sopcell->parameters["\\DEPTH"].as_int() + 1;
log_assert(sopcell->parameters[ID::WIDTH].as_int() == input_len);
sopcell->parameters[ID::DEPTH] = sopcell->parameters[ID::DEPTH].as_int() + 1;
for (int i = 0; i < input_len; i++)
switch (input[i]) {
case '0':
sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break;
case '1':
sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
sopcell->parameters["\\TABLE"].bits.push_back(State::S1);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S1);
break;
default:
sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
sopcell->parameters["\\TABLE"].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
sopcell->parameters[ID::TABLE].bits.push_back(State::S0);
break;
}