mirror of
https://github.com/YosysHQ/yosys
synced 2025-06-24 06:43:41 +00:00
kernel: big fat patch to use more ID::*, otherwise ID(*)
This commit is contained in:
Eddie Hung
parent
2d86563bb2
commit
956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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@ -401,9 +401,9 @@ struct FirrtlWorker
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{
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const auto wireName = make_id(wire->name);
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// If a wire has initial data, issue a warning since FIRRTL doesn't currently support it.
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if (wire->attributes.count("\\init")) {
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if (wire->attributes.count(ID::init)) {
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log_warning("Initial value (%s) for (%s.%s) not supported\n",
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wire->attributes.at("\\init").as_string().c_str(),
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wire->attributes.at(ID::init).as_string().c_str(),
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log_id(module), log_id(wire));
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}
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if (wire->port_id)
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@ -431,18 +431,18 @@ struct FirrtlWorker
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}
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// Not a module instance. Set up cell properties
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bool extract_y_bits = false; // Assume no extraction of final bits will be required.
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int a_width = cell->parameters.at("\\A_WIDTH", ndef).as_int(); // The width of "A"
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int b_width = cell->parameters.at("\\B_WIDTH", ndef).as_int(); // The width of "A"
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const int y_width = cell->parameters.at("\\Y_WIDTH", ndef).as_int(); // The width of the result
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const bool a_signed = cell->parameters.at("\\A_SIGNED", ndef).as_bool();
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const bool b_signed = cell->parameters.at("\\B_SIGNED", ndef).as_bool();
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int a_width = cell->parameters.at(ID::A_WIDTH, ndef).as_int(); // The width of "A"
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int b_width = cell->parameters.at(ID::B_WIDTH, ndef).as_int(); // The width of "A"
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const int y_width = cell->parameters.at(ID::Y_WIDTH, ndef).as_int(); // The width of the result
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const bool a_signed = cell->parameters.at(ID::A_SIGNED, ndef).as_bool();
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const bool b_signed = cell->parameters.at(ID::B_SIGNED, ndef).as_bool();
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bool firrtl_is_signed = a_signed; // The result is signed (subsequent code may change this).
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int firrtl_width = 0;
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string primop;
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bool always_uint = false;
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string y_id = make_id(cell->name);
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if (cell->type.in("$not", "$logic_not", "$neg", "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_bool", "$reduce_xnor"))
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if (cell->type.in(ID($not), ID($logic_not), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
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{
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string a_expr = make_expr(cell->getPort(ID::A));
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wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
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@ -452,29 +452,29 @@ struct FirrtlWorker
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}
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// Don't use the results of logical operations (a single bit) to control padding
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if (!(cell->type.in("$eq", "$eqx", "$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$reduce_bool", "$logic_not") && y_width == 1) ) {
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if (!(cell->type.in(ID($eq), ID($eqx), ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($reduce_bool), ID($logic_not)) && y_width == 1) ) {
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a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
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}
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// Assume the FIRRTL width is a single bit.
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firrtl_width = 1;
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if (cell->type == "$not") primop = "not";
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else if (cell->type == "$neg") {
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if (cell->type == ID($not)) primop = "not";
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else if (cell->type == ID($neg)) {
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primop = "neg";
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firrtl_is_signed = true; // Result of "neg" is signed (an SInt).
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firrtl_width = a_width;
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} else if (cell->type == "$logic_not") {
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} else if (cell->type == ID($logic_not)) {
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primop = "eq";
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a_expr = stringf("%s, UInt(0)", a_expr.c_str());
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}
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else if (cell->type == "$reduce_and") primop = "andr";
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else if (cell->type == "$reduce_or") primop = "orr";
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else if (cell->type == "$reduce_xor") primop = "xorr";
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else if (cell->type == "$reduce_xnor") {
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else if (cell->type == ID($reduce_and)) primop = "andr";
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else if (cell->type == ID($reduce_or)) primop = "orr";
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else if (cell->type == ID($reduce_xor)) primop = "xorr";
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else if (cell->type == ID($reduce_xnor)) {
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primop = "not";
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a_expr = stringf("xorr(%s)", a_expr.c_str());
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}
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else if (cell->type == "$reduce_bool") {
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else if (cell->type == ID($reduce_bool)) {
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primop = "neq";
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// Use the sign of the a_expr and its width as the type (UInt/SInt) and width of the comparand.
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a_expr = stringf("%s, %cInt<%d>(0)", a_expr.c_str(), a_signed ? 'S' : 'U', a_width);
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@ -490,9 +490,9 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or", "$eq", "$eqx",
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"$gt", "$ge", "$lt", "$le", "$ne", "$nex", "$shr", "$sshr", "$sshl", "$shl",
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"$logic_and", "$logic_or", "$pow"))
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or), ID($eq), ID($eqx),
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ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
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ID($logic_and), ID($logic_or), ID($pow)))
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{
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string a_expr = make_expr(cell->getPort(ID::A));
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string b_expr = make_expr(cell->getPort(ID::B));
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@ -508,7 +508,7 @@ struct FirrtlWorker
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}
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// Shift amount is always unsigned, and needn't be padded to result width,
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// otherwise, we need to cast the b_expr appropriately
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if (b_signed && !cell->type.in("$shr", "$sshr", "$shl", "$sshl", "$pow")) {
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if (b_signed && !cell->type.in(ID($shr), ID($sshr), ID($shl), ID($sshl), ID($pow))) {
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b_expr = "asSInt(" + b_expr + ")";
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// Expand the "B" operand to the result width
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if (b_width < y_width) {
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@ -519,7 +519,7 @@ struct FirrtlWorker
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// For the arithmetic ops, expand operand widths to result widths befor performing the operation.
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// This corresponds (according to iverilog) to what verilog compilers implement.
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if (cell->type.in("$add", "$sub", "$mul", "$div", "$mod", "$xor", "$xnor", "$and", "$or"))
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if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($xor), ID($xnor), ID($and), ID($or)))
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{
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if (a_width < y_width) {
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a_expr = stringf("pad(%s, %d)", a_expr.c_str(), y_width);
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@ -534,78 +534,78 @@ struct FirrtlWorker
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firrtl_width = a_width;
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auto a_sig = cell->getPort(ID::A);
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if (cell->type == "$add") {
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if (cell->type == ID($add)) {
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primop = "add";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = max(a_width, b_width);
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} else if (cell->type == "$sub") {
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} else if (cell->type == ID($sub)) {
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primop = "sub";
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firrtl_is_signed = true;
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int a_widthInc = (!a_signed && b_signed) ? 2 : (a_signed && !b_signed) ? 1 : 0;
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int b_widthInc = (a_signed && !b_signed) ? 2 : (!a_signed && b_signed) ? 1 : 0;
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firrtl_width = max(a_width + a_widthInc, b_width + b_widthInc);
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} else if (cell->type == "$mul") {
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} else if (cell->type == ID($mul)) {
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primop = "mul";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = a_width + b_width;
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} else if (cell->type == "$div") {
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} else if (cell->type == ID($div)) {
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primop = "div";
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firrtl_is_signed = a_signed | b_signed;
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firrtl_width = a_width;
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} else if (cell->type == "$mod") {
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} else if (cell->type == ID($mod)) {
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primop = "rem";
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firrtl_width = min(a_width, b_width);
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} else if (cell->type == "$and") {
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} else if (cell->type == ID($and)) {
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primop = "and";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type == "$or" ) {
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else if (cell->type == ID($or) ) {
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primop = "or";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type == "$xor") {
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else if (cell->type == ID($xor)) {
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primop = "xor";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if (cell->type == "$xnor") {
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else if (cell->type == ID($xnor)) {
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primop = "xnor";
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always_uint = true;
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firrtl_width = max(a_width, b_width);
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}
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else if ((cell->type == "$eq") | (cell->type == "$eqx")) {
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else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
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primop = "eq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == "$ne") | (cell->type == "$nex")) {
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else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
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primop = "neq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == "$gt") {
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else if (cell->type == ID($gt)) {
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primop = "gt";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == "$ge") {
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else if (cell->type == ID($ge)) {
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primop = "geq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == "$lt") {
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else if (cell->type == ID($lt)) {
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primop = "lt";
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always_uint = true;
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firrtl_width = 1;
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}
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else if (cell->type == "$le") {
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else if (cell->type == ID($le)) {
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primop = "leq";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == "$shl") | (cell->type == "$sshl")) {
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else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
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// FIRRTL will widen the result (y) by the amount of the shift.
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// We'll need to offset this by extracting the un-widened portion as Verilog would do.
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extract_y_bits = true;
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@ -623,7 +623,7 @@ struct FirrtlWorker
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firrtl_width = a_width + (1 << b_width) - 1;
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}
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}
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else if ((cell->type == "$shr") | (cell->type == "$sshr")) {
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else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
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// We don't need to extract a specific range of bits.
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extract_y_bits = false;
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// Is the shift amount constant?
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@ -640,26 +640,26 @@ struct FirrtlWorker
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// We'll need to do some special fixups if the source (and thus result) is signed.
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if (firrtl_is_signed) {
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// If this is a "logical" shift right, pretend the source is unsigned.
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if (cell->type == "$shr") {
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if (cell->type == ID($shr)) {
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a_expr = "asUInt(" + a_expr + ")";
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}
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}
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}
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else if ((cell->type == "$logic_and")) {
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else if ((cell->type == ID($logic_and))) {
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primop = "and";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == "$logic_or")) {
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else if ((cell->type == ID($logic_or))) {
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primop = "or";
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a_expr = "neq(" + a_expr + ", UInt(0))";
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b_expr = "neq(" + b_expr + ", UInt(0))";
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always_uint = true;
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firrtl_width = 1;
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}
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else if ((cell->type == "$pow")) {
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else if ((cell->type == ID($pow))) {
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if (a_sig.is_fully_const() && a_sig.as_int() == 2) {
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// We'll convert this to a shift. To simplify things, change the a_expr to "1"
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// so we can use b_expr directly as a shift amount.
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@ -689,7 +689,7 @@ struct FirrtlWorker
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}
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}
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if (!cell->parameters.at("\\B_SIGNED").as_bool()) {
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if (!cell->parameters.at(ID::B_SIGNED).as_bool()) {
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b_expr = "asUInt(" + b_expr + ")";
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}
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@ -718,9 +718,9 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in("$mux"))
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if (cell->type.in(ID($mux)))
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{
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int width = cell->parameters.at("\\WIDTH").as_int();
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int width = cell->parameters.at(ID::WIDTH).as_int();
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string a_expr = make_expr(cell->getPort(ID::A));
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string b_expr = make_expr(cell->getPort(ID::B));
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string s_expr = make_expr(cell->getPort(ID::S));
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@ -734,26 +734,26 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in("$mem"))
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if (cell->type.in(ID($mem)))
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{
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string mem_id = make_id(cell->name);
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int abits = cell->parameters.at("\\ABITS").as_int();
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int width = cell->parameters.at("\\WIDTH").as_int();
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int size = cell->parameters.at("\\SIZE").as_int();
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int abits = cell->parameters.at(ID::ABITS).as_int();
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int width = cell->parameters.at(ID::WIDTH).as_int();
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int size = cell->parameters.at(ID::SIZE).as_int();
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memory m(cell, mem_id, abits, size, width);
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int rd_ports = cell->parameters.at("\\RD_PORTS").as_int();
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int wr_ports = cell->parameters.at("\\WR_PORTS").as_int();
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int rd_ports = cell->parameters.at(ID::RD_PORTS).as_int();
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int wr_ports = cell->parameters.at(ID::WR_PORTS).as_int();
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Const initdata = cell->parameters.at("\\INIT");
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Const initdata = cell->parameters.at(ID::INIT);
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for (State bit : initdata.bits)
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if (bit != State::Sx)
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log_error("Memory with initialization data: %s.%s\n", log_id(module), log_id(cell));
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Const rd_clk_enable = cell->parameters.at("\\RD_CLK_ENABLE");
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Const wr_clk_enable = cell->parameters.at("\\WR_CLK_ENABLE");
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Const wr_clk_polarity = cell->parameters.at("\\WR_CLK_POLARITY");
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Const rd_clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE);
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Const wr_clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE);
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Const wr_clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY);
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int offset = cell->parameters.at("\\OFFSET").as_int();
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int offset = cell->parameters.at(ID::OFFSET).as_int();
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if (offset != 0)
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log_error("Memory with nonzero offset: %s.%s\n", log_id(module), log_id(cell));
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@ -762,8 +762,8 @@ struct FirrtlWorker
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if (rd_clk_enable[i] != State::S0)
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log_error("Clocked read port %d on memory %s.%s.\n", i, log_id(module), log_id(cell));
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SigSpec addr_sig = cell->getPort("\\RD_ADDR").extract(i*abits, abits);
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SigSpec data_sig = cell->getPort("\\RD_DATA").extract(i*width, width);
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SigSpec addr_sig = cell->getPort(ID::RD_ADDR).extract(i*abits, abits);
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SigSpec data_sig = cell->getPort(ID::RD_DATA).extract(i*width, width);
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string addr_expr = make_expr(addr_sig);
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string name(stringf("%s.r%d", m.name.c_str(), i));
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bool clk_enable = false;
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@ -789,14 +789,14 @@ struct FirrtlWorker
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bool clk_enable = true;
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bool clk_parity = true;
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bool transparency = false;
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SigSpec addr_sig =cell->getPort("\\WR_ADDR").extract(i*abits, abits);
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SigSpec addr_sig =cell->getPort(ID::WR_ADDR).extract(i*abits, abits);
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string addr_expr = make_expr(addr_sig);
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SigSpec data_sig =cell->getPort("\\WR_DATA").extract(i*width, width);
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SigSpec data_sig =cell->getPort(ID::WR_DATA).extract(i*width, width);
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string data_expr = make_expr(data_sig);
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SigSpec clk_sig = cell->getPort("\\WR_CLK").extract(i);
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SigSpec clk_sig = cell->getPort(ID::WR_CLK).extract(i);
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string clk_expr = make_expr(clk_sig);
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SigSpec wen_sig = cell->getPort("\\WR_EN").extract(i*width, width);
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SigSpec wen_sig = cell->getPort(ID::WR_EN).extract(i*width, width);
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string wen_expr = make_expr(wen_sig[0]);
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for (int i = 1; i < GetSize(wen_sig); i++)
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@ -813,23 +813,23 @@ struct FirrtlWorker
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continue;
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}
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if (cell->type.in("$memwr", "$memrd", "$meminit"))
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if (cell->type.in(ID($memwr), ID($memrd), ID($meminit)))
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{
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std::string cell_type = fid(cell->type);
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std::string mem_id = make_id(cell->parameters["\\MEMID"].decode_string());
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int abits = cell->parameters.at("\\ABITS").as_int();
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int width = cell->parameters.at("\\WIDTH").as_int();
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std::string mem_id = make_id(cell->parameters[ID::MEMID].decode_string());
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int abits = cell->parameters.at(ID::ABITS).as_int();
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int width = cell->parameters.at(ID::WIDTH).as_int();
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memory *mp = nullptr;
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if (cell->type == "$meminit" ) {
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if (cell->type == ID($meminit) ) {
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log_error("$meminit (%s.%s.%s) currently unsupported\n", log_id(module), log_id(cell), mem_id.c_str());
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} else {
|
||||
// It's a $memwr or $memrd. Remember the read/write port parameters for the eventual FIRRTL memory definition.
|
||||
auto addrSig = cell->getPort("\\ADDR");
|
||||
auto dataSig = cell->getPort("\\DATA");
|
||||
auto enableSig = cell->getPort("\\EN");
|
||||
auto clockSig = cell->getPort("\\CLK");
|
||||
Const clk_enable = cell->parameters.at("\\CLK_ENABLE");
|
||||
Const clk_polarity = cell->parameters.at("\\CLK_POLARITY");
|
||||
auto addrSig = cell->getPort(ID::ADDR);
|
||||
auto dataSig = cell->getPort(ID::DATA);
|
||||
auto enableSig = cell->getPort(ID::EN);
|
||||
auto clockSig = cell->getPort(ID::CLK);
|
||||
Const clk_enable = cell->parameters.at(ID::CLK_ENABLE);
|
||||
Const clk_polarity = cell->parameters.at(ID::CLK_POLARITY);
|
||||
|
||||
// Do we already have an entry for this memory?
|
||||
if (memories.count(mem_id) == 0) {
|
||||
|
|
@ -840,13 +840,13 @@ struct FirrtlWorker
|
|||
int portNum = 0;
|
||||
bool transparency = false;
|
||||
string data_expr = make_expr(dataSig);
|
||||
if (cell->type.in("$memwr")) {
|
||||
if (cell->type.in(ID($memwr))) {
|
||||
portNum = (int) mp->write_ports.size();
|
||||
write_port wp(stringf("%s.w%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig, dataSig);
|
||||
mp->add_memory_write_port(wp);
|
||||
cell_exprs.push_back(stringf("%s%s.data <= %s\n", indent.c_str(), wp.name.c_str(), data_expr.c_str()));
|
||||
cell_exprs.push_back(wp.gen_write(indent.c_str()));
|
||||
} else if (cell->type.in("$memrd")) {
|
||||
} else if (cell->type.in(ID($memrd))) {
|
||||
portNum = (int) mp->read_ports.size();
|
||||
read_port rp(stringf("%s.r%d", mem_id.c_str(), portNum), clk_enable.as_bool(), clk_polarity.as_bool(), transparency, clockSig, enableSig, addrSig);
|
||||
mp->add_memory_read_port(rp);
|
||||
|
|
@ -857,20 +857,20 @@ struct FirrtlWorker
|
|||
continue;
|
||||
}
|
||||
|
||||
if (cell->type.in("$dff"))
|
||||
if (cell->type.in(ID($dff)))
|
||||
{
|
||||
bool clkpol = cell->parameters.at("\\CLK_POLARITY").as_bool();
|
||||
bool clkpol = cell->parameters.at(ID::CLK_POLARITY).as_bool();
|
||||
if (clkpol == false)
|
||||
log_error("Negative edge clock on FF %s.%s.\n", log_id(module), log_id(cell));
|
||||
|
||||
int width = cell->parameters.at("\\WIDTH").as_int();
|
||||
string expr = make_expr(cell->getPort("\\D"));
|
||||
string clk_expr = "asClock(" + make_expr(cell->getPort("\\CLK")) + ")";
|
||||
int width = cell->parameters.at(ID::WIDTH).as_int();
|
||||
string expr = make_expr(cell->getPort(ID::D));
|
||||
string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
|
||||
|
||||
wire_decls.push_back(stringf(" reg %s: UInt<%d>, %s\n", y_id.c_str(), width, clk_expr.c_str()));
|
||||
|
||||
cell_exprs.push_back(stringf(" %s <= %s\n", y_id.c_str(), expr.c_str()));
|
||||
register_reverse_wire_map(y_id, cell->getPort("\\Q"));
|
||||
register_reverse_wire_map(y_id, cell->getPort(ID::Q));
|
||||
|
||||
continue;
|
||||
}
|
||||
|
|
@ -881,7 +881,7 @@ struct FirrtlWorker
|
|||
process_instance(cell, wire_exprs);
|
||||
continue;
|
||||
}
|
||||
if (cell->type == "$shiftx") {
|
||||
if (cell->type == ID($shiftx)) {
|
||||
// assign y = a[b +: y_width];
|
||||
// We'll extract the correct bits as part of the primop.
|
||||
|
||||
|
|
@ -890,10 +890,10 @@ struct FirrtlWorker
|
|||
string b_expr = make_expr(cell->getPort(ID::B));
|
||||
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
|
||||
|
||||
if (cell->getParam("\\B_SIGNED").as_bool()) {
|
||||
if (cell->getParam(ID::B_SIGNED).as_bool()) {
|
||||
// Use validif to constrain the selection (test the sign bit)
|
||||
auto b_string = b_expr.c_str();
|
||||
int b_sign = cell->parameters.at("\\B_WIDTH").as_int() - 1;
|
||||
int b_sign = cell->parameters.at(ID::B_WIDTH).as_int() - 1;
|
||||
b_expr = stringf("validif(not(bits(%s, %d, %d)), %s)", b_string, b_sign, b_sign, b_string);
|
||||
}
|
||||
string expr = stringf("dshr(%s, %s)", a_expr.c_str(), b_expr.c_str());
|
||||
|
|
@ -902,7 +902,7 @@ struct FirrtlWorker
|
|||
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
|
||||
continue;
|
||||
}
|
||||
if (cell->type == "$shift") {
|
||||
if (cell->type == ID($shift)) {
|
||||
// assign y = a >> b;
|
||||
// where b may be negative
|
||||
|
||||
|
|
@ -912,7 +912,7 @@ struct FirrtlWorker
|
|||
string expr;
|
||||
wire_decls.push_back(stringf(" wire %s: UInt<%d>\n", y_id.c_str(), y_width));
|
||||
|
||||
if (cell->getParam("\\B_SIGNED").as_bool()) {
|
||||
if (cell->getParam(ID::B_SIGNED).as_bool()) {
|
||||
// We generate a left or right shift based on the sign of b.
|
||||
std::string dshl = stringf("bits(dshl(%s, %s), 0, %d)", a_expr.c_str(), gen_dshl(b_expr, b_width).c_str(), y_width);
|
||||
std::string dshr = stringf("dshr(%s, %s)", a_expr.c_str(), b_string);
|
||||
|
|
@ -928,7 +928,7 @@ struct FirrtlWorker
|
|||
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
|
||||
continue;
|
||||
}
|
||||
if (cell->type == "$pos") {
|
||||
if (cell->type == ID($pos)) {
|
||||
// assign y = a;
|
||||
// printCell(cell);
|
||||
string a_expr = make_expr(cell->getPort(ID::A));
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue