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kernel: big fat patch to use more ID::*, otherwise ID(*)

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This commit is contained in:
Eddie Hung 2020-04-02 09:51:32 -07:00
parent 2d86563bb2
commit 956ecd48f7
152 changed files with 4503 additions and 4391 deletions
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212
backends/btor/btor.cc
View file

@ -98,8 +98,8 @@ struct BtorWorker
string getinfo(T *obj, bool srcsym = false)
{
string infostr = log_id(obj);
if (obj->attributes.count("\\src")) {
string src = obj->attributes.at("\\src").decode_string().c_str();
if (obj->attributes.count(ID::src)) {
string src = obj->attributes.at(ID::src).decode_string().c_str();
if (srcsym && infostr[0] == '$') {
std::replace(src.begin(), src.end(), ' ', '_');
if (srcsymbols.count(src) || module->count_id("\\" + src)) {
@ -183,40 +183,40 @@ struct BtorWorker
cell_recursion_guard.insert(cell);
btorf_push(log_id(cell));
if (cell->type.in("$add", "$sub", "$mul", "$and", "$or", "$xor", "$xnor", "$shl", "$sshl", "$shr", "$sshr", "$shift", "$shiftx",
"$concat", "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_"))
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor), ID($shl), ID($sshl), ID($shr), ID($sshr), ID($shift), ID($shiftx),
ID($concat), ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_)))
{
string btor_op;
if (cell->type == "$add") btor_op = "add";
if (cell->type == "$sub") btor_op = "sub";
if (cell->type == "$mul") btor_op = "mul";
if (cell->type.in("$shl", "$sshl")) btor_op = "sll";
if (cell->type == "$shr") btor_op = "srl";
if (cell->type == "$sshr") btor_op = "sra";
if (cell->type.in("$shift", "$shiftx")) btor_op = "shift";
if (cell->type.in("$and", "$_AND_")) btor_op = "and";
if (cell->type.in("$or", "$_OR_")) btor_op = "or";
if (cell->type.in("$xor", "$_XOR_")) btor_op = "xor";
if (cell->type == "$concat") btor_op = "concat";
if (cell->type == "$_NAND_") btor_op = "nand";
if (cell->type == "$_NOR_") btor_op = "nor";
if (cell->type.in("$xnor", "$_XNOR_")) btor_op = "xnor";
if (cell->type == ID($add)) btor_op = "add";
if (cell->type == ID($sub)) btor_op = "sub";
if (cell->type == ID($mul)) btor_op = "mul";
if (cell->type.in(ID($shl), ID($sshl))) btor_op = "sll";
if (cell->type == ID($shr)) btor_op = "srl";
if (cell->type == ID($sshr)) btor_op = "sra";
if (cell->type.in(ID($shift), ID($shiftx))) btor_op = "shift";
if (cell->type.in(ID($and), ID($_AND_))) btor_op = "and";
if (cell->type.in(ID($or), ID($_OR_))) btor_op = "or";
if (cell->type.in(ID($xor), ID($_XOR_))) btor_op = "xor";
if (cell->type == ID($concat)) btor_op = "concat";
if (cell->type == ID($_NAND_)) btor_op = "nand";
if (cell->type == ID($_NOR_)) btor_op = "nor";
if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
if (btor_op == "shift" && !b_signed)
btor_op = "srl";
if (cell->type.in("$shl", "$sshl", "$shr", "$sshr"))
if (cell->type.in(ID($shl), ID($sshl), ID($shr), ID($sshr)))
b_signed = false;
if (cell->type == "$sshr" && !a_signed)
if (cell->type == ID($sshr) && !a_signed)
btor_op = "srl";
int sid = get_bv_sid(width);
@ -266,19 +266,19 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$div", "$mod"))
if (cell->type.in(ID($div), ID($mod)))
{
string btor_op;
if (cell->type == "$div") btor_op = "div";
if (cell->type == "$mod") btor_op = "rem";
if (cell->type == ID($div)) btor_op = "div";
if (cell->type == ID($mod)) btor_op = "rem";
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
@ -300,7 +300,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$_ANDNOT_", "$_ORNOT_"))
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
@ -309,12 +309,12 @@ struct BtorWorker
int nid1 = next_nid++;
int nid2 = next_nid++;
if (cell->type == "$_ANDNOT_") {
if (cell->type == ID($_ANDNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d and %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
if (cell->type == "$_ORNOT_") {
if (cell->type == ID($_ORNOT_)) {
btorf("%d not %d %d\n", nid1, sid, nid_b);
btorf("%d or %d %d %d %s\n", nid2, sid, nid_a, nid1, getinfo(cell).c_str());
}
@ -324,24 +324,24 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$_OAI3_", "$_AOI3_"))
if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C"));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid1 = next_nid++;
int nid2 = next_nid++;
int nid3 = next_nid++;
if (cell->type == "$_OAI3_") {
if (cell->type == ID($_OAI3_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
}
if (cell->type == "$_AOI3_") {
if (cell->type == ID($_AOI3_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid1, nid_c);
btorf("%d not %d %d %s\n", nid3, sid, nid2, getinfo(cell).c_str());
@ -352,27 +352,27 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$_OAI4_", "$_AOI4_"))
if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort("\\C"));
int nid_d = get_sig_nid(cell->getPort("\\D"));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_d = get_sig_nid(cell->getPort(ID::D));
int nid1 = next_nid++;
int nid2 = next_nid++;
int nid3 = next_nid++;
int nid4 = next_nid++;
if (cell->type == "$_OAI4_") {
if (cell->type == ID($_OAI4_)) {
btorf("%d or %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d or %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d and %d %d %d\n", nid3, sid, nid1, nid2);
btorf("%d not %d %d %s\n", nid4, sid, nid3, getinfo(cell).c_str());
}
if (cell->type == "$_AOI4_") {
if (cell->type == ID($_AOI4_)) {
btorf("%d and %d %d %d\n", nid1, sid, nid_a, nid_b);
btorf("%d and %d %d %d\n", nid2, sid, nid_c, nid_d);
btorf("%d or %d %d %d\n", nid3, sid, nid1, nid2);
@ -384,30 +384,30 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$lt", "$le", "$eq", "$eqx", "$ne", "$nex", "$ge", "$gt"))
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($eqx), ID($ne), ID($nex), ID($ge), ID($gt)))
{
string btor_op;
if (cell->type == "$lt") btor_op = "lt";
if (cell->type == "$le") btor_op = "lte";
if (cell->type.in("$eq", "$eqx")) btor_op = "eq";
if (cell->type.in("$ne", "$nex")) btor_op = "neq";
if (cell->type == "$ge") btor_op = "gte";
if (cell->type == "$gt") btor_op = "gt";
if (cell->type == ID($lt)) btor_op = "lt";
if (cell->type == ID($le)) btor_op = "lte";
if (cell->type.in(ID($eq), ID($eqx))) btor_op = "eq";
if (cell->type.in(ID($ne), ID($nex))) btor_op = "neq";
if (cell->type == ID($ge)) btor_op = "gte";
if (cell->type == ID($gt)) btor_op = "gt";
log_assert(!btor_op.empty());
int width = 1;
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool b_signed = cell->hasParam("\\B_SIGNED") ? cell->getParam("\\B_SIGNED").as_bool() : false;
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid = next_nid++;
if (cell->type.in("$lt", "$le", "$ge", "$gt")) {
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
btorf("%d %c%s %d %d %d %s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
} else {
btorf("%d %s %d %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, nid_b, getinfo(cell).c_str());
@ -426,16 +426,16 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$not", "$neg", "$_NOT_"))
if (cell->type.in(ID($not), ID($neg), ID($_NOT_)))
{
string btor_op;
if (cell->type.in("$not", "$_NOT_")) btor_op = "not";
if (cell->type == "$neg") btor_op = "neg";
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
if (cell->type == ID($neg)) btor_op = "neg";
log_assert(!btor_op.empty());
int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
bool a_signed = cell->hasParam("\\A_SIGNED") ? cell->getParam("\\A_SIGNED").as_bool() : false;
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
int sid = get_bv_sid(width);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
@ -456,12 +456,12 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$logic_and", "$logic_or", "$logic_not"))
if (cell->type.in(ID($logic_and), ID($logic_or), ID($logic_not)))
{
string btor_op;
if (cell->type == "$logic_and") btor_op = "and";
if (cell->type == "$logic_or") btor_op = "or";
if (cell->type == "$logic_not") btor_op = "not";
if (cell->type == ID($logic_and)) btor_op = "and";
if (cell->type == ID($logic_or)) btor_op = "or";
if (cell->type == ID($logic_not)) btor_op = "not";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
@ -500,12 +500,12 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$reduce_and", "$reduce_or", "$reduce_bool", "$reduce_xor", "$reduce_xnor"))
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($reduce_xor), ID($reduce_xnor)))
{
string btor_op;
if (cell->type == "$reduce_and") btor_op = "redand";
if (cell->type.in("$reduce_or", "$reduce_bool")) btor_op = "redor";
if (cell->type.in("$reduce_xor", "$reduce_xnor")) btor_op = "redxor";
if (cell->type == ID($reduce_and)) btor_op = "redand";
if (cell->type.in(ID($reduce_or), ID($reduce_bool))) btor_op = "redor";
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) btor_op = "redxor";
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
@ -513,7 +513,7 @@ struct BtorWorker
int nid = next_nid++;
if (cell->type == "$reduce_xnor") {
if (cell->type == ID($reduce_xnor)) {
int nid2 = next_nid++;
btorf("%d %s %d %d %s\n", nid, btor_op.c_str(), sid, nid_a, getinfo(cell).c_str());
btorf("%d not %d %d %d\n", nid2, sid, nid);
@ -536,7 +536,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$mux", "$_MUX_", "$_NMUX_"))
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
@ -550,7 +550,7 @@ struct BtorWorker
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
if (cell->type == "$_NMUX_") {
if (cell->type == ID($_NMUX_)) {
int tmp = nid;
nid = next_nid++;
btorf("%d ite %d %d %d %d\n", tmp, sid, nid_s, nid_b, nid_a);
@ -563,7 +563,7 @@ struct BtorWorker
goto okay;
}
if (cell->type == "$pmux")
if (cell->type == ID($pmux))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
@ -589,21 +589,21 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$dff", "$ff", "$_DFF_P_", "$_DFF_N_", "$_FF_"))
if (cell->type.in(ID($dff), ID($ff), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
{
SigSpec sig_d = sigmap(cell->getPort("\\D"));
SigSpec sig_q = sigmap(cell->getPort("\\Q"));
SigSpec sig_d = sigmap(cell->getPort(ID::D));
SigSpec sig_q = sigmap(cell->getPort(ID::Q));
if (!info_filename.empty() && cell->type.in("$dff", "$_DFF_P_", "$_DFF_N_"))
if (!info_filename.empty() && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
{
SigSpec sig_c = sigmap(cell->getPort(cell->type == "$dff" ? "\\CLK" : "\\C"));
SigSpec sig_c = sigmap(cell->getPort(cell->type == ID($dff) ? ID::CLK : ID::C));
int nid = get_sig_nid(sig_c);
bool negedge = false;
if (cell->type == "$_DFF_N_")
if (cell->type == ID($_DFF_N_))
negedge = true;
if (cell->type == "$dff" && !cell->getParam("\\CLK_POLARITY").as_bool())
if (cell->type == ID($dff) && !cell->getParam(ID::CLK_POLARITY).as_bool())
negedge = true;
info_clocks[nid] |= negedge ? 2 : 1;
@ -651,7 +651,7 @@ struct BtorWorker
goto okay;
}
if (cell->type.in("$anyconst", "$anyseq"))
if (cell->type.in(ID($anyconst), ID($anyseq)))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
@ -660,7 +660,7 @@ struct BtorWorker
btorf("%d state %d\n", nid, sid);
if (cell->type == "$anyconst") {
if (cell->type == ID($anyconst)) {
int nid2 = next_nid++;
btorf("%d next %d %d %d\n", nid2, sid, nid, nid);
}
@ -669,7 +669,7 @@ struct BtorWorker
goto okay;
}
if (cell->type == "$initstate")
if (cell->type == ID($initstate))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
@ -688,16 +688,16 @@ struct BtorWorker
goto okay;
}
if (cell->type == "$mem")
if (cell->type == ID($mem))
{
int abits = cell->getParam("\\ABITS").as_int();
int width = cell->getParam("\\WIDTH").as_int();
int nwords = cell->getParam("\\SIZE").as_int();
int rdports = cell->getParam("\\RD_PORTS").as_int();
int wrports = cell->getParam("\\WR_PORTS").as_int();
int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam(ID::WIDTH).as_int();
int nwords = cell->getParam(ID::SIZE).as_int();
int rdports = cell->getParam(ID::RD_PORTS).as_int();
int wrports = cell->getParam(ID::WR_PORTS).as_int();
Const wr_clk_en = cell->getParam("\\WR_CLK_ENABLE");
Const rd_clk_en = cell->getParam("\\RD_CLK_ENABLE");
Const wr_clk_en = cell->getParam(ID::WR_CLK_ENABLE);
Const rd_clk_en = cell->getParam(ID::RD_CLK_ENABLE);
bool asyncwr = wr_clk_en.is_fully_zero();
@ -709,18 +709,18 @@ struct BtorWorker
log_error("Memory %s.%s has sync read ports.\n",
log_id(module), log_id(cell));
SigSpec sig_rd_addr = sigmap(cell->getPort("\\RD_ADDR"));
SigSpec sig_rd_data = sigmap(cell->getPort("\\RD_DATA"));
SigSpec sig_rd_addr = sigmap(cell->getPort(ID::RD_ADDR));
SigSpec sig_rd_data = sigmap(cell->getPort(ID::RD_DATA));
SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1);
int sid = get_mem_sid(abits, width);
Const initdata = cell->getParam("\\INIT");
Const initdata = cell->getParam(ID::INIT);
initdata.exts(nwords*width);
int nid_init_val = -1;
@ -1053,8 +1053,8 @@ struct BtorWorker
for (auto wire : module->wires())
{
if (wire->attributes.count("\\init")) {
Const attrval = wire->attributes.at("\\init");
if (wire->attributes.count(ID::init)) {
Const attrval = wire->attributes.at(ID::init);
for (int i = 0; i < GetSize(wire) && i < GetSize(attrval); i++)
if (attrval[i] == State::S0 || attrval[i] == State::S1)
initbits[sigmap(SigBit(wire, i))] = (attrval[i] == State::S1);
@ -1098,13 +1098,13 @@ struct BtorWorker
for (auto cell : module->cells())
{
if (cell->type == "$assume")
if (cell->type == ID($assume))
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++;
int nid = next_nid++;
@ -1116,13 +1116,13 @@ struct BtorWorker
btorf_pop(log_id(cell));
}
if (cell->type == "$assert")
if (cell->type == ID($assert))
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
@ -1143,13 +1143,13 @@ struct BtorWorker
btorf_pop(log_id(cell));
}
if (cell->type == "$cover" && cover_mode)
if (cell->type == ID($cover) && cover_mode)
{
btorf_push(log_id(cell));
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort("\\A"));
int nid_en = get_sig_nid(cell->getPort("\\EN"));
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_en_and_a = next_nid++;
btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
@ -1197,15 +1197,15 @@ struct BtorWorker
btorf_push(stringf("next %s", log_id(cell)));
if (cell->type == "$mem")
if (cell->type == ID($mem))
{
int abits = cell->getParam("\\ABITS").as_int();
int width = cell->getParam("\\WIDTH").as_int();
int wrports = cell->getParam("\\WR_PORTS").as_int();
int abits = cell->getParam(ID::ABITS).as_int();
int width = cell->getParam(ID::WIDTH).as_int();
int wrports = cell->getParam(ID::WR_PORTS).as_int();
SigSpec sig_wr_addr = sigmap(cell->getPort("\\WR_ADDR"));
SigSpec sig_wr_data = sigmap(cell->getPort("\\WR_DATA"));
SigSpec sig_wr_en = sigmap(cell->getPort("\\WR_EN"));
SigSpec sig_wr_addr = sigmap(cell->getPort(ID::WR_ADDR));
SigSpec sig_wr_data = sigmap(cell->getPort(ID::WR_DATA));
SigSpec sig_wr_en = sigmap(cell->getPort(ID::WR_EN));
int data_sid = get_bv_sid(width);
int bool_sid = get_bv_sid(1);
@ -1254,7 +1254,7 @@ struct BtorWorker
}
else
{
SigSpec sig = sigmap(cell->getPort("\\D"));
SigSpec sig = sigmap(cell->getPort(ID::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d %s\n", next_nid++, sid, nid, nid_q, getinfo(cell).c_str());