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ecp5: Add abc9 option
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
parent
bc22e2e3ee
commit
9566573054
8 changed files with 188 additions and 66 deletions
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@ -82,6 +82,9 @@ struct SynthEcp5Pass : public ScriptPass
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log(" -abc2\n");
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log(" run two passes of 'abc' for slightly improved logic density\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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log(" -vpr\n");
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log(" generate an output netlist (and BLIF file) suitable for VPR\n");
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log(" (this feature is experimental and incomplete)\n");
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@ -93,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
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}
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string top_opt, blif_file, edif_file, json_file;
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bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, vpr;
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bool noccu2, nodffe, nobram, nodram, nomux, flatten, retime, abc2, abc9, vpr;
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void clear_flags() YS_OVERRIDE
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{
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@ -110,6 +113,7 @@ struct SynthEcp5Pass : public ScriptPass
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retime = false;
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abc2 = false;
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vpr = false;
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abc9 = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -184,6 +188,10 @@ struct SynthEcp5Pass : public ScriptPass
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vpr = true;
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continue;
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}
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if (args[argidx] == "-abc9") {
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abc9 = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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@ -203,7 +211,7 @@ struct SynthEcp5Pass : public ScriptPass
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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@ -264,10 +272,15 @@ struct SynthEcp5Pass : public ScriptPass
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run("abc", " (only if -abc2)");
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}
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run("techmap -map +/ecp5/latches_map.v");
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if (nomux)
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run("abc -lut 4 -dress");
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else
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run("abc -lut 4:7 -dress");
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if (abc9) {
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run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
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} else {
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if (nomux)
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run("abc -lut 4 -dress");
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else
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run("abc -lut 4:7 -dress");
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}
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run("clean");
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}
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