diff --git a/kernel/log.cc b/kernel/log.cc index 0dceb0343..ab8cc9041 100644 --- a/kernel/log.cc +++ b/kernel/log.cc @@ -588,7 +588,7 @@ void log_dump_val_worker(RTLIL::State v) { std::string log_signal(const RTLIL::SigSpec &sig, bool autoint) { std::stringstream buf; - RTLIL_BACKEND::dump_sigspec(buf, sig, autoint); + RTLIL_BACKEND::dump_sigspec(buf, sig, autoint, RTLIL_BACKEND::DumpMode::Readable); return buf.str(); } @@ -643,21 +643,21 @@ const char *log_id(const RTLIL::Process *obj, const char *nullstr) void log_module(RTLIL::Module *module, std::string indent) { std::stringstream buf; - RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false); + RTLIL_BACKEND::dump_module(buf, indent, module, module->design, false, true, false, RTLIL_BACKEND::DumpMode::Readable); log("%s", buf.str()); } void log_cell(RTLIL::Cell *cell, std::string indent) { std::stringstream buf; - RTLIL_BACKEND::dump_cell(buf, indent, cell); + RTLIL_BACKEND::dump_cell(buf, indent, cell, cell->module ? cell->module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); log("%s", buf.str()); } void log_wire(RTLIL::Wire *wire, std::string indent) { std::stringstream buf; - RTLIL_BACKEND::dump_wire(buf, indent, wire); + RTLIL_BACKEND::dump_wire(buf, indent, wire, wire->module ? wire->module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); log("%s", buf.str()); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 80cbe4571..1808f3fc1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1811,7 +1811,7 @@ void RTLIL::Design::pop_selection() std::string RTLIL::Design::to_rtlil_str(bool only_selected) const { std::ostringstream f; - RTLIL_BACKEND::dump_design(f, const_cast(this), only_selected); + RTLIL_BACKEND::dump_design(f, const_cast(this), only_selected, true, false, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } @@ -4970,7 +4970,7 @@ RTLIL::SigSpec RTLIL::Module::FutureFF(Twine &&name, const RTLIL::SigSpec &sig_e std::string RTLIL::Module::to_rtlil_str() const { std::ostringstream f; - RTLIL_BACKEND::dump_module(f, "", const_cast(this), design, false); + RTLIL_BACKEND::dump_module(f, "", const_cast(this), design, false, true, false, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } @@ -5048,7 +5048,7 @@ void RTLIL::Wire::absorb_attrs(dict &&buf) std::string RTLIL::Wire::to_rtlil_str() const { std::ostringstream f; - RTLIL_BACKEND::dump_wire(f, "", this); + RTLIL_BACKEND::dump_wire(f, "", this, module ? module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } @@ -5077,7 +5077,7 @@ RTLIL::Memory::Memory() std::string RTLIL::Memory::to_rtlil_str() const { std::ostringstream f; - RTLIL_BACKEND::dump_memory(f, "", this); + RTLIL_BACKEND::dump_memory(f, "", this, module ? module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } @@ -5091,7 +5091,7 @@ RTLIL::Process::Process() : module(nullptr) std::string RTLIL::Process::to_rtlil_str() const { std::ostringstream f; - RTLIL_BACKEND::dump_proc(f, "", this); + RTLIL_BACKEND::dump_proc(f, "", this, module ? module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } @@ -5161,7 +5161,7 @@ void RTLIL::Cell::absorb_attrs(dict &&buf) std::string RTLIL::Cell::to_rtlil_str() const { std::ostringstream f; - RTLIL_BACKEND::dump_cell(f, "", this); + RTLIL_BACKEND::dump_cell(f, "", this, module ? module->design : nullptr, RTLIL_BACKEND::DumpMode::Readable); return f.str(); } diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 92074e737..a5f1f9586 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -3345,6 +3345,14 @@ void RTLIL::Process::rewrite_sigspecs2(T &functor) it->rewrite_sigspecs2(functor); } +// The masq accessors below recover their containing Wire/Cell/Module by +// subtracting offsetof from `this`. Those types are non-standard-layout (base +// classes + virtuals), so offsetof is conditionally-supported, but it is +// well-defined on GCC/Clang for these fixed field offsets. +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Winvalid-offsetof" +#endif inline TwineRef RTLIL::WireNameMasq::ref() const { const RTLIL::Wire *w = reinterpret_cast( reinterpret_cast(this) - offsetof(RTLIL::Wire, name)); @@ -3460,6 +3468,9 @@ inline std::string RTLIL::ModuleNameMasq::unescaped() const { return std::string(); return m->design->twines.unescaped_str(id); } +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif // -Winvalid-offsetof for masq accessors inline RTLIL::ModuleNameMasq::operator TwineRef() const { return ref(); }