mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 03:32:29 +00:00
Code Activity

Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH

Browse source
This commit is contained in:
Xark 2020-06-14 00:45:22 -07:00
parent 74e93e083f
commit 9509444ef2
1 changed files with 7 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

14
techlibs/ice40/cells_sim.v
View file

@ -2508,7 +2508,7 @@ module SB_SPRAM256KA (
always @(negedge POWEROFF) begin
for (i = 0; i <= 16383; i = i+1)
mem[i] = 'bx;
mem[i] = 16'bx;
end
always @(posedge CLOCK, posedge off) begin
@ -2516,17 +2516,17 @@ module SB_SPRAM256KA (
DATAOUT <= 0;
end else
if (STANDBY) begin
DATAOUT <= 'bx;
DATAOUT <= 16'bx;
end else
if (CHIPSELECT) begin
if (!WREN) begin
DATAOUT <= mem[ADDRESS];
end else begin
if (MASKWREN[0]) mem[ADDRESS][ 3: 0] = DATAIN[ 3: 0];
if (MASKWREN[1]) mem[ADDRESS][ 7: 4] = DATAIN[ 7: 4];
if (MASKWREN[2]) mem[ADDRESS][11: 8] = DATAIN[11: 8];
if (MASKWREN[3]) mem[ADDRESS][15:12] = DATAIN[15:12];
DATAOUT <= 'bx;
if (MASKWREN[0]) mem[ADDRESS][ 3: 0] <= DATAIN[ 3: 0];
if (MASKWREN[1]) mem[ADDRESS][ 7: 4] <= DATAIN[ 7: 4];
if (MASKWREN[2]) mem[ADDRESS][11: 8] <= DATAIN[11: 8];
if (MASKWREN[3]) mem[ADDRESS][15:12] <= DATAIN[15:12];
DATAOUT <= 16'bx;
end
end
end