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Merge pull request #1535 from YosysHQ/eddie/write_xaiger_improve

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write_xaiger improvements
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Eddie Hung 2019-11-27 01:04:29 -08:00 • committed by GitHub
commit 95053d9010
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2 changed files with 5 additions and 22 deletions
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18
backends/aiger/xaiger.cc
View file

@ -153,11 +153,6 @@ struct XAigerWriter
if (wire->port_input) if (wire->port_input)
sigmap.add(wire); sigmap.add(wire);
// promote output wires
for (auto wire : module->wires())
if (wire->port_output)
sigmap.add(wire);
for (auto wire : module->wires()) for (auto wire : module->wires())
{ {
bool keep = wire->attributes.count("\\keep"); bool keep = wire->attributes.count("\\keep");
@ -173,12 +168,13 @@ struct XAigerWriter
} }
if (keep) if (keep)
keep_bits.insert(bit); keep_bits.insert(wirebit);
if (wire->port_input || keep) { if (wire->port_input || keep) {
if (bit != wirebit) if (bit != wirebit)
alias_map[bit] = wirebit; alias_map[bit] = wirebit;
input_bits.insert(wirebit); input_bits.insert(wirebit);
undriven_bits.erase(bit);
} }
if (wire->port_output || keep) { if (wire->port_output || keep) {
@ -186,6 +182,8 @@ struct XAigerWriter
if (bit != wirebit) if (bit != wirebit)
alias_map[wirebit] = bit; alias_map[wirebit] = bit;
output_bits.insert(wirebit); output_bits.insert(wirebit);
if (!wire->port_input)
unused_bits.erase(bit);
} }
else else
log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit)); log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
@ -193,12 +191,6 @@ struct XAigerWriter
} }
} }
for (auto bit : input_bits)
undriven_bits.erase(sigmap(bit));
for (auto bit : output_bits)
if (!bit.wire->port_input)
unused_bits.erase(bit);
// TODO: Speed up toposort -- ultimately we care about // TODO: Speed up toposort -- ultimately we care about
// box ordering, but not individual AIG cells // box ordering, but not individual AIG cells
dict<SigBit, pool<IdString>> bit_drivers, bit_users; dict<SigBit, pool<IdString>> bit_drivers, bit_users;
@ -824,7 +816,7 @@ struct XAigerBackend : public Backend {
log(" write ASCII version of AIGER format\n"); log(" write ASCII version of AIGER format\n");
log("\n"); log("\n");
log(" -map <filename>\n"); log(" -map <filename>\n");
log(" write an extra file with port and latch symbols\n"); log(" write an extra file with port and box symbols\n");
log("\n"); log("\n");
log(" -vmap <filename>\n"); log(" -vmap <filename>\n");
log(" like -map, but more verbose\n"); log(" like -map, but more verbose\n");

9
tests/simple_abc9/abc9.v
View file

@ -218,12 +218,6 @@ module MUXF8(input I0, I1, S, output O);
endmodule endmodule
// Citation: https://github.com/alexforencich/verilog-ethernet // Citation: https://github.com/alexforencich/verilog-ethernet
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
// returns before b4321a31
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
// driver.
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
// driver.
module abc9_test022 module abc9_test022
( (
input wire clk, input wire clk,
@ -237,9 +231,6 @@ module abc9_test022
endmodule endmodule
// Citation: https://github.com/riscv/riscv-bitmanip // Citation: https://github.com/riscv/riscv-bitmanip
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
// returns before 14233843
// Warning: Wire abc9_test023.\dout [1] is used but has no driver.
module abc9_test023 #( module abc9_test023 #(
parameter integer N = 2, parameter integer N = 2,
parameter integer M = 2 parameter integer M = 2