mirror of
https://github.com/YosysHQ/yosys
synced 2025-09-02 16:20:51 +00:00
Merge remote-tracking branch 'origin/master' into xaig_dff
This commit is contained in:
Eddie Hung
commit
94f15f023c
47 changed files with 2053 additions and 184 deletions
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@ -32,10 +32,9 @@ equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivale
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|||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd dffs # Constrain all select calls below inside the top module
|
||||
select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDRE
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select -assert-count 1 t:LUT2
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||||
select -assert-count 1 t:FDSE
|
||||
|
||||
select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D
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||||
select -assert-none t:BUFG t:FDSE %% t:* %D
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||||
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||||
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||||
design -load read
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||||
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@ -46,6 +45,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
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cd ndffnr # Constrain all select calls below inside the top module
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||||
select -assert-count 1 t:BUFG
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select -assert-count 1 t:FDRE_1
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select -assert-count 1 t:LUT2
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select -assert-count 1 t:INV
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select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D
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select -assert-none t:BUFG t:FDRE_1 t:INV %% t:* %D
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47
tests/arch/xilinx/attributes_test.ys
Normal file
47
tests/arch/xilinx/attributes_test.ys
Normal file
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@ -0,0 +1,47 @@
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# Check that blockram memory without parameters is not modified
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Check that distributed memory without parameters is not modified
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top distributed_ram
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synth_xilinx -top distributed_ram
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cd distributed_ram # Constrain all select calls below inside the top module
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select -assert-count 8 t:RAM32X1D
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# Set ram_style distributed to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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prep
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setattr -mod -set ram_style "distributed" block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 32 t:RAM128X1D
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# Set synthesis, logic_block to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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prep
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setattr -mod -set logic_block 1 block_ram
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synth_xilinx -top block_ram
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 0 t:RAMB18E1
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select -assert-count 32 t:RAM128X1D
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# Set ram_style block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual
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cd distributed_ram_manual # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual_syn
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cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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97
tests/arch/xilinx/blockram.ys
Normal file
97
tests/arch/xilinx/blockram.ys
Normal file
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@ -0,0 +1,97 @@
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### TODO: Not running equivalence checking because BRAM models does not exists
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### currently. Checking instance counts instead.
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# Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 18 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 14 -set DATA_WIDTH 1 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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|
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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# Anything memory bits < 1024 -> LUTRAM
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design -reset
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read_verilog ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 0 t:RAMB18E1
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select -assert-count 4 t:RAM128X1D
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# More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
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design -reset
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read_verilog ../common/blockram.v
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||||
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 36 sync_ram_sdp
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB36E1
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### With parameters
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
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setattr -set ram_style "block" m:memory
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
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setattr -set ram_block 1 m:memory
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||||
synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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|
||||
design -reset
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read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
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setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
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||||
synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 0 t:RAMB18E1
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||||
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||||
design -reset
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||||
read_verilog ../common/blockram.v
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hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1
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||||
setattr -set logic_block 1 m:memory
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synth_xilinx -top sync_ram_sdp
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cd sync_ram_sdp
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select -assert-count 0 t:RAMB18E1
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||||
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||||
design -reset
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||||
read_verilog ../common/blockram.v
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||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
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setattr -set ram_style "block" m:memory
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synth_xilinx -top sync_ram_sdp
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||||
cd sync_ram_sdp
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select -assert-count 1 t:RAMB18E1
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||||
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||||
design -reset
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||||
read_verilog ../common/blockram.v
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||||
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
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||||
setattr -set ram_block 1 m:memory
|
||||
synth_xilinx -top sync_ram_sdp
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||||
cd sync_ram_sdp
|
||||
select -assert-count 1 t:RAMB18E1
|
||||
34
tests/arch/xilinx/bug1460.ys
Normal file
34
tests/arch/xilinx/bug1460.ys
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
read_verilog <<EOT
|
||||
module register_file(
|
||||
input wire clk,
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||||
input wire write_enable,
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input wire [63:0] write_data,
|
||||
input wire [4:0] write_reg,
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||||
input wire [4:0] read1_reg,
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||||
input wire [4:0] read2_reg,
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||||
input wire [4:0] read3_reg,
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output reg [63:0] read1_data,
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output reg [63:0] read2_data,
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output reg [63:0] read3_data
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);
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|
||||
reg [63:0] registers[0:31];
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||||
|
||||
always @(posedge clk) begin
|
||||
if (write_enable == 1'b1) begin
|
||||
registers[write_reg] <= write_data;
|
||||
end
|
||||
end
|
||||
|
||||
always @(all) begin
|
||||
read1_data <= registers[read1_reg];
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read2_data <= registers[read2_reg];
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||||
read3_data <= registers[read3_reg];
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||||
end
|
||||
endmodule
|
||||
EOT
|
||||
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||||
synth_xilinx
|
||||
cd register_file
|
||||
select -assert-count 32 t:RAM32M
|
||||
select -assert-none t:* t:BUFG %d t:RAM32M %d
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||||
|
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@ -11,8 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
|
|||
cd fsm # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 5 t:FDRE
|
||||
select -assert-count 1 t:LUT3
|
||||
select -assert-count 2 t:LUT4
|
||||
select -assert-count 4 t:LUT6
|
||||
select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D
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||||
select -assert-count 4 t:FDRE
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT2
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||||
select -assert-count 3 t:LUT5
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||||
select -assert-count 1 t:LUT6
|
||||
select -assert-none t:BUFG t:FDRE t:FDSE t:LUT2 t:LUT5 t:LUT6 %% t:* %D
|
||||
|
|
|
|||
137
tests/arch/xilinx/lutram.ys
Normal file
137
tests/arch/xilinx/lutram.ys
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
#read_verilog ../common/lutram.v
|
||||
#hierarchy -top lutram_1w1r -chparam A_WIDTH 4
|
||||
#proc
|
||||
#memory -nomap
|
||||
#equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
#memory
|
||||
#opt -full
|
||||
#
|
||||
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
#
|
||||
#design -load postopt
|
||||
#cd lutram_1w1r
|
||||
#select -assert-count 1 t:BUFG
|
||||
#select -assert-count 8 t:FDRE
|
||||
#select -assert-count 8 t:RAM16X1D
|
||||
#select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w1r -chparam A_WIDTH 5
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM32X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w1r
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM64X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w3r
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w3r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 24 t:FDRE
|
||||
select -assert-count 4 t:RAM32M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w3r -chparam A_WIDTH 6
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w3r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 24 t:FDRE
|
||||
select -assert-count 8 t:RAM64M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 6 t:FDRE
|
||||
select -assert-count 1 t:RAM32M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
|
||||
|
||||
|
||||
design -reset
|
||||
read_verilog ../common/lutram.v
|
||||
hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd lutram_1w1r
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 6 t:FDRE
|
||||
select -assert-count 2 t:RAM64M
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
|
||||
|
|
@ -23,9 +23,10 @@ miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
|||
sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd macc2 # Constrain all select calls below inside the top module
|
||||
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 1 t:DSP48E1
|
||||
select -assert-count 1 t:FDRE
|
||||
select -assert-count 1 t:LUT2
|
||||
select -assert-count 41 t:LUT3
|
||||
select -assert-count 40 t:LUT3
|
||||
select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D
|
||||
|
|
|
|||
|
|
@ -1,17 +0,0 @@
|
|||
read_verilog ../common/memory.v
|
||||
hierarchy -top top
|
||||
proc
|
||||
memory -nomap
|
||||
equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
|
||||
memory
|
||||
opt -full
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter
|
||||
|
||||
design -load postopt
|
||||
cd top
|
||||
select -assert-count 1 t:BUFG
|
||||
select -assert-count 8 t:FDRE
|
||||
select -assert-count 8 t:RAM64X1D
|
||||
select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
|
||||
|
|
@ -40,6 +40,8 @@ proc
|
|||
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
|
||||
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
||||
cd mux16 # Constrain all select calls below inside the top module
|
||||
select -assert-count 5 t:LUT6
|
||||
select -assert-min 5 t:LUT6
|
||||
select -assert-max 7 t:LUT6
|
||||
select -assert-max 2 t:MUXF7
|
||||
|
||||
select -assert-none t:LUT6 %% t:* %D
|
||||
select -assert-none t:LUT6 t:MUXF7 %% t:* %D
|
||||
|
|
|
|||
216
tests/arch/xilinx/xilinx_dffopt.ys
Normal file
216
tests/arch/xilinx/xilinx_dffopt.ys
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
read_verilog << EOT
|
||||
|
||||
// FDRE, mergeable CE and R.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDRE ff (.D(tmp[0]), .CE(tmp[1]), .R(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDRE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDRE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDSE, mergeable CE and S, inversions.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDSE #(.IS_D_INVERTED(1'b1), .IS_S_INVERTED(1'b1)) ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDCE, mergeable CE.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h6)) lut2 (.I0(i[3]), .I1(i[4]), .O(tmp[2]));
|
||||
|
||||
FDCE ff (.D(tmp[0]), .CE(tmp[1]), .CLR(tmp[2]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -async2sync -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDCE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 3 t:LUT2
|
||||
select -assert-none t:FDCE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDSE, mergeable CE and S, but CE only not worth it.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
|
||||
FDSE ff (.D(tmp[0]), .CE(i[7]), .S(tmp[1]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 1 t:LUT5
|
||||
select -assert-count 2 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT5 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDSE
|
||||
select -assert-count 2 t:LUT2
|
||||
select -assert-none t:FDSE t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
|
||||
|
||||
read_verilog << EOT
|
||||
|
||||
// FDRSE, mergeable CE, S, R.
|
||||
|
||||
module t0 (...);
|
||||
input wire clk;
|
||||
input wire [7:0] i;
|
||||
output wire [7:0] o;
|
||||
|
||||
wire [7:0] tmp ;
|
||||
|
||||
LUT2 #(.INIT(4'h6)) lut0 (.I0(i[0]), .I1(i[1]), .O(tmp[0]));
|
||||
LUT2 #(.INIT(4'h6)) lut1 (.I0(i[1]), .I1(i[2]), .O(tmp[1]));
|
||||
LUT2 #(.INIT(4'h8)) lut2 (.I0(i[2]), .I1(i[0]), .O(tmp[2]));
|
||||
LUT2 #(.INIT(4'h6)) lut3 (.I0(i[3]), .I1(i[4]), .O(tmp[3]));
|
||||
|
||||
FDRSE ff (.D(tmp[0]), .CE(tmp[1]), .S(tmp[2]), .R(tmp[3]), .Q(o[0]));
|
||||
|
||||
endmodule
|
||||
|
||||
EOT
|
||||
|
||||
design -save t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRSE
|
||||
select -assert-count 1 t:LUT6
|
||||
select -assert-count 4 t:LUT2
|
||||
select -assert-none t:FDRSE t:LUT6 t:LUT2 %% t:* %D
|
||||
|
||||
design -load t0
|
||||
|
||||
equiv_opt -blacklist xilinx_dffopt_blacklist.txt -assert -map +/xilinx/cells_sim.v xilinx_dffopt -lut4
|
||||
design -load postopt
|
||||
clean
|
||||
|
||||
select -assert-count 1 t:FDRSE
|
||||
select -assert-count 1 t:LUT4
|
||||
select -assert-count 4 t:LUT2
|
||||
select -assert-none t:FDRSE t:LUT4 t:LUT2 %% t:* %D
|
||||
|
||||
design -reset
|
||||
13
tests/arch/xilinx/xilinx_dffopt_blacklist.txt
Normal file
13
tests/arch/xilinx/xilinx_dffopt_blacklist.txt
Normal file
|
|
@ -0,0 +1,13 @@
|
|||
lut0
|
||||
lut1
|
||||
lut2
|
||||
lut3
|
||||
ff
|
||||
ff.D
|
||||
ff.R
|
||||
ff.S
|
||||
ff.CE
|
||||
ff.d
|
||||
ff.r
|
||||
ff.s
|
||||
ff.ce
|
||||
Loading…
Add table
Add a link
Reference in a new issue