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https://github.com/YosysHQ/yosys
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Added memory_bram (not functional yet)
This commit is contained in:
Clifford Wolf
parent
1e08621e7e
commit
94e6b70736
4 changed files with 307 additions and 1 deletions
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@ -199,7 +199,7 @@ inline void memhasher() { if (memhasher_active) memhasher_do(); }
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std::string stringf(const char *fmt, ...) YS_ATTRIBUTE(format(printf, 1, 2));
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std::string vstringf(const char *fmt, va_list ap);
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int readsome(std::istream &f, char *s, int n);
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std::string next_token(std::string &text, const char *sep);
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std::string next_token(std::string &text, const char *sep = " \t\r\n");
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bool patmatch(const char *pattern, const char *string);
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int run_command(const std::string &command, std::function<void(const std::string&)> process_line = std::function<void(const std::string&)>());
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std::string make_temp_file(std::string template_str = "/tmp/yosys_XXXXXX");
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@ -4,5 +4,6 @@ OBJS += passes/memory/memory_dff.o
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OBJS += passes/memory/memory_share.o
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OBJS += passes/memory/memory_collect.o
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OBJS += passes/memory/memory_unpack.o
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OBJS += passes/memory/memory_bram.o
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OBJS += passes/memory/memory_map.o
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285
passes/memory/memory_bram.cc
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285
passes/memory/memory_bram.cc
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@ -0,0 +1,285 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct rules_t
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{
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struct bram_t {
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IdString name;
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int groups, abits, dbits, init;
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vector<int> wports, rports, wenabl, transp, clocks, clkpol;
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};
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struct match_t {
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IdString name;
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dict<string, int> min_limits, max_limits;
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};
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dict<IdString, bram_t> brams;
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vector<match_t> matches;
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std::ifstream infile;
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vector<string> tokens;
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int linecount;
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string line;
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void syntax_error()
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{
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if (line.empty())
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log_error("Unexpected end of rules file in line %d.\n", linecount);
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log_error("Syntax error in rules file line %d: %s\n", linecount, line.c_str());
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}
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bool next_line()
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{
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linecount++;
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tokens.clear();
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while (std::getline(infile, line)) {
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for (string tok = next_token(line); !tok.empty(); tok = next_token(line)) {
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if (tok[0] == '#')
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break;
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tokens.push_back(tok);
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}
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if (!tokens.empty())
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return true;
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}
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return false;
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}
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bool parse_single_int(const char *stmt, int &value)
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{
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if (GetSize(tokens) == 2 && tokens[0] == stmt) {
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value = atoi(tokens[1].c_str());
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return true;
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}
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return false;
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}
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bool parse_int_vect(const char *stmt, vector<int> &value)
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{
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if (GetSize(tokens) >= 2 && tokens[0] == stmt) {
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value.resize(GetSize(tokens)-1);
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for (int i = 1; i < GetSize(tokens); i++)
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value[i] = atoi(tokens[i].c_str());
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return true;
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}
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return false;
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}
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void parse_bram()
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{
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if (GetSize(tokens) != 2)
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syntax_error();
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bram_t data;
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data.name = RTLIL::escape_id(tokens[1]);
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while (next_line())
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{
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if (GetSize(tokens) == 1 && tokens[0] == "endbram") {
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brams[data.name] = data;
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return;
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}
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if (parse_single_int("groups", data.groups))
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continue;
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if (parse_single_int("abits", data.abits))
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continue;
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if (parse_single_int("dbits", data.dbits))
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continue;
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if (parse_single_int("init", data.init))
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continue;
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if (parse_int_vect("wports", data.wports))
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continue;
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if (parse_int_vect("rports", data.rports))
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continue;
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if (parse_int_vect("wenabl", data.wenabl))
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continue;
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if (parse_int_vect("transp", data.transp))
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continue;
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if (parse_int_vect("clocks", data.clocks))
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continue;
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if (parse_int_vect("clkpol", data.clkpol))
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continue;
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break;
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}
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syntax_error();
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}
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void parse_match()
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{
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if (GetSize(tokens) != 2)
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syntax_error();
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match_t data;
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data.name = RTLIL::escape_id(tokens[1]);
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while (next_line())
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{
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if (GetSize(tokens) == 1 && tokens[0] == "endmatch") {
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matches.push_back(data);
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return;
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}
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if (GetSize(tokens) == 3 && tokens[0] == "min") {
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data.min_limits[tokens[1]] = atoi(tokens[2].c_str());
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continue;
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}
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if (GetSize(tokens) == 3 && tokens[0] == "max") {
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data.max_limits[tokens[1]] = atoi(tokens[2].c_str());
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continue;
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}
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break;
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}
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syntax_error();
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}
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void parse(std::string filename)
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{
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infile.open(filename);
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linecount = 0;
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if (infile.fail())
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log_error("Can't open rules file `%s'.\n", filename.c_str());
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while (next_line())
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{
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if (tokens[0] == "bram") parse_bram();
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else if (tokens[0] == "match") parse_match();
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else syntax_error();
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}
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infile.close();
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}
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};
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void replace_cell(Cell*, const rules_t::bram_t&, const rules_t::match_t&)
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{
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log(" FIXME: The core of memory_bram is not implemented yet.\n");
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}
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void handle_cell(Cell *cell, const rules_t &rules)
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{
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log("Processing %s.%s:\n", log_id(cell->module), log_id(cell));
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dict<string, int> mem_properties;
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mem_properties["words"] = cell->getParam("\\SIZE").as_int();
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mem_properties["abits"] = cell->getParam("\\ABITS").as_int();
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mem_properties["dbits"] = cell->getParam("\\WIDTH").as_int();
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mem_properties["wports"] = cell->getParam("\\WR_PORTS").as_int();
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mem_properties["rports"] = cell->getParam("\\RD_PORTS").as_int();
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mem_properties["bits"] = mem_properties["words"] * mem_properties["dbits"];
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mem_properties["ports"] = mem_properties["wports"] + mem_properties["rports"];
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log(" Properties:");
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for (auto &it : mem_properties)
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log(" %s=%d", it.first.c_str(), it.second);
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log("\n");
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for (int i = 0; i < GetSize(rules.matches); i++)
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{
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for (auto it : rules.matches[i].min_limits) {
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if (!mem_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(rules.matches[i].name));
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if (mem_properties[it.first] >= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'min %s %d' not met.\n",
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i, log_id(rules.matches[i].name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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for (auto it : rules.matches[i].max_limits) {
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if (!mem_properties.count(it.first))
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log_error("Unknown property '%s' in match rule for bram type %s.\n",
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it.first.c_str(), log_id(rules.matches[i].name));
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if (mem_properties[it.first] <= it.second)
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continue;
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log(" Rule #%d for bram type %s rejected: requirement 'max %s %d' not met.\n",
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i, log_id(rules.matches[i].name), it.first.c_str(), it.second);
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goto next_match_rule;
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}
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log(" Rule #%d for bram type %s accepted.\n", i, log_id(rules.matches[i].name));
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if (!rules.brams.count(rules.matches[i].name))
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log_error("No bram description for resource %s found!\n", log_id(rules.matches[i].name));
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replace_cell(cell, rules.brams.at(rules.matches[i].name), rules.matches[i]);
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return;
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next_match_rule:;
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}
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log(" No acceptable bram resources found.\n");
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}
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struct MemoryBramPass : public Pass {
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MemoryBramPass() : Pass("memory_bram", "map memories to block rams") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" memory_bram -rules <rule_file> [selection]\n");
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log("\n");
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log("This pass converts the multi-port $mem memory cells into block ram instances.\n");
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log("The given rules file describes the available resources and how they should be\n");
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log("used.\n");
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log("\n");
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}
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virtual void execute(vector<string> args, Design *design)
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{
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rules_t rules;
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log_header("Executing MEMORY_BRAM pass (mapping $mem cells to block memories).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-rules" && argidx+1 < args.size()) {
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rules.parse(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto mod : design->selected_modules())
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for (auto cell : mod->selected_cells())
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if (cell->type == "$mem")
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handle_cell(cell, rules);
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}
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} MemoryBramPass;
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PRIVATE_NAMESPACE_END
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20
techlibs/xilinx/brams.txt
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20
techlibs/xilinx/brams.txt
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@ -0,0 +1,20 @@
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# This is a very simplified description of the capabilities of
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# the Xilinx RAMB36 core. But it is a start..
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#
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bram XILINX_RAMB36_SDP32
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init 1
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abits 10
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dbits 32
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groups 2
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wports 1 0
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rports 0 1
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wenabl 2 0
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transp 0 2
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clocks 1 2
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endbram
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match XILINX_RAMB36_SDP32
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min bits 1024
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endmatch
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