From 94c789e9c86824d40c4c5bdd9d7ea9d33ccfdb78 Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Wed, 4 Mar 2026 17:48:35 -0500 Subject: [PATCH] setundef: respect selection for cells, processes, and connections Previously, setundef would rewrite sigspecs in all cells, processes, and connections regardless of the active selection. Only modules and memories were correctly filtered by selection. Fix by using module->selected_cells() for cells, adding a module->selected() check for processes, and checking wire selection on the lhs of each connection before rewriting. Fixes #5624 --- passes/cmds/setundef.cc | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 5d2ccfcc8..b3d76a51f 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -502,14 +502,22 @@ struct SetundefPass : public Pass { } } - for (auto &it : module->cells_) - if (!it.second->get_bool_attribute(ID::xprop_decoder)) - it.second->rewrite_sigspecs(worker); + for (auto cell : module->selected_cells()) + if (!cell->get_bool_attribute(ID::xprop_decoder)) + cell->rewrite_sigspecs(worker); for (auto &it : module->processes) - it.second->rewrite_sigspecs(worker); + if (module->selected(it.second)) + it.second->rewrite_sigspecs(worker); for (auto &it : module->connections_) { - worker(it.first); - worker(it.second); + SigSpec lhs = it.first; + bool selected = false; + for (auto &chunk : lhs.chunks()) + if (chunk.wire && module->design->selected(module, chunk.wire)) + selected = true; + if (selected) { + worker(it.first); + worker(it.second); + } } if (worker.next_bit_mode == MODE_ANYSEQ || worker.next_bit_mode == MODE_ANYCONST)