From 2b3a148fc41f77e6933a97c964fb610d9dc313ab Mon Sep 17 00:00:00 2001 From: Anhijkt Date: Sat, 5 Apr 2025 13:46:38 +0300 Subject: [PATCH 01/10] ice40_dsp: fix const handling --- techlibs/ice40/ice40_dsp.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 63bc8de4b..2cfb97b2a 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -32,8 +32,8 @@ code sigA sigB sigH ++i; return sig.extract(0, i); }; - sigA = unextend(port(mul, \A)); - sigB = unextend(port(mul, \B)); + sigA = port(mul, \A).is_fully_const() ? port(mul, \A) : unextend(port(mul, \A)); + sigB = port(mul, \B).is_fully_const() ? port(mul, \B) : unextend(port(mul, \B)); SigSpec O; if (mul->type == $mul) From 41a7d4bb819c715cc428a482b938315f68c6b358 Mon Sep 17 00:00:00 2001 From: Anhijkt Date: Wed, 9 Apr 2025 21:21:46 +0300 Subject: [PATCH 02/10] ice40_dsp: add test --- tests/arch/ice40/ice40_dsp_const.ys | 80 +++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 tests/arch/ice40/ice40_dsp_const.ys diff --git a/tests/arch/ice40/ice40_dsp_const.ys b/tests/arch/ice40/ice40_dsp_const.ys new file mode 100644 index 000000000..c9c76a1ac --- /dev/null +++ b/tests/arch/ice40/ice40_dsp_const.ys @@ -0,0 +1,80 @@ +read_verilog << EOT +module top(input wire [14:0] a, output wire [18:0] b); +assign b = a*$unsigned(5'b01111); +endmodule +EOT + +prep +ice40_dsp + +read_verilog << EOT +module ref(a, b); + wire _0_; + wire _1_; + wire _2_; + wire [12:0] _3_; + (* src = "< Date: Thu, 10 Apr 2025 17:42:39 +0300 Subject: [PATCH 03/10] ice40_dsp: change unextend call condition --- techlibs/ice40/ice40_dsp.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index 2cfb97b2a..ff7c5cb65 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -32,8 +32,8 @@ code sigA sigB sigH ++i; return sig.extract(0, i); }; - sigA = port(mul, \A).is_fully_const() ? port(mul, \A) : unextend(port(mul, \A)); - sigB = port(mul, \B).is_fully_const() ? port(mul, \B) : unextend(port(mul, \B)); + sigA = param(mul, \A_SIGNED).as_bool() ? unextend(port(mul, \A)) : port(mul, \A); + sigB = param(mul, \B_SIGNED).as_bool() ? unextend(port(mul, \B)) : port(mul, \B); SigSpec O; if (mul->type == $mul) From 163e339c692494133a4648fb157fabed8da9753b Mon Sep 17 00:00:00 2001 From: Anhijkt Date: Fri, 11 Apr 2025 19:41:35 +0300 Subject: [PATCH 04/10] ice40_dsp: add unextend_unsigned function --- techlibs/ice40/ice40_dsp.pmg | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg index ff7c5cb65..7e4c3ace2 100644 --- a/techlibs/ice40/ice40_dsp.pmg +++ b/techlibs/ice40/ice40_dsp.pmg @@ -23,7 +23,7 @@ match mul endmatch code sigA sigB sigH - auto unextend = [](const SigSpec &sig) { + auto unextend_signed = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) if (sig[i] != sig[i-1]) @@ -32,8 +32,16 @@ code sigA sigB sigH ++i; return sig.extract(0, i); }; - sigA = param(mul, \A_SIGNED).as_bool() ? unextend(port(mul, \A)) : port(mul, \A); - sigB = param(mul, \B_SIGNED).as_bool() ? unextend(port(mul, \B)) : port(mul, \B); + auto unextend_unsigned = [](const SigSpec &sig) { + int i; + for (i = GetSize(sig)-1; i > 0; i--) + if (sig[i] != SigBit(State::S0)) + break; + ++i; + return sig.extract(0, i); + }; + sigA = param(mul, \A_SIGNED).as_bool() ? unextend_signed(port(mul, \A)) : unextend_unsigned(port(mul, \A)); + sigB = param(mul, \B_SIGNED).as_bool() ? unextend_signed(port(mul, \B)) : unextend_unsigned(port(mul, \B)); SigSpec O; if (mul->type == $mul) From c343462c16e9bebc6dd3d487121173d89c7ceb6e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Apr 2025 14:16:02 +0200 Subject: [PATCH 05/10] gatemate: WRITE_THROUGH mode change --- techlibs/gatemate/brams.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/gatemate/brams.txt b/techlibs/gatemate/brams.txt index be22856ac..d39aafcbf 100644 --- a/techlibs/gatemate/brams.txt +++ b/techlibs/gatemate/brams.txt @@ -34,7 +34,6 @@ ram block $__CC_BRAM_TDP_ { } portoption "WR_MODE" "WRITE_THROUGH" { rdwr new; - wrtrans all new; } wrbe_separate; optional_rw; From 2fcb61adb5101c2c6539de0d4a8b9000326a928a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Joachim=20Stro=CC=88mbergson?= Date: Wed, 23 Apr 2025 17:21:32 +0200 Subject: [PATCH 06/10] Change to use blocking assignments in non-clocked processes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Joachim StroĢˆmbergson --- techlibs/greenpak4/cells_sim_digital.v | 62 +++++++++++++------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 43d35d08f..f1393be0c 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -48,7 +48,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT); //Combinatorially output underflow flag whenever we wrap low always @(*) begin - OUT <= (count == 14'h0); + OUT = (count == 14'h0); end //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. @@ -133,10 +133,10 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, //Combinatorially output underflow flag whenever we wrap low always @(*) begin if(UP) - OUT <= (count == 14'h3fff); + OUT = (count == 14'h3fff); else - OUT <= (count == 14'h0); - POUT <= count[7:0]; + OUT = (count == 14'h0); + POUT = count[7:0]; end //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. @@ -272,10 +272,10 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, //Combinatorially output underflow flag whenever we wrap low always @(*) begin if(UP) - OUT <= (count == 8'hff); + OUT = (count == 8'hff); else - OUT <= (count == 8'h0); - POUT <= count; + OUT = (count == 8'h0); + POUT = count; end //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. @@ -413,8 +413,8 @@ module GP_COUNT8( //Combinatorially output underflow flag whenever we wrap low always @(*) begin - OUT <= (count == 8'h0); - POUT <= count; + OUT = (count == 8'h0); + POUT = count; end //POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm. @@ -488,23 +488,23 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2 always @(*) begin case(SEL) 2'd00: begin - OUTA <= IN0; - OUTB <= IN3; + OUTA = IN0; + OUTB = IN3; end 2'd01: begin - OUTA <= IN1; - OUTB <= IN2; + OUTA = IN1; + OUTB = IN2; end 2'd02: begin - OUTA <= IN2; - OUTB <= IN1; + OUTA = IN2; + OUTB = IN1; end 2'd03: begin - OUTA <= IN3; - OUTB <= IN0; + OUTA = IN3; + OUTB = IN0; end endcase @@ -635,7 +635,7 @@ module GP_DLATCH(input D, input nCLK, output reg Q); initial Q = INIT; always @(*) begin if(!nCLK) - Q <= D; + Q = D; end endmodule @@ -644,7 +644,7 @@ module GP_DLATCHI(input D, input nCLK, output reg nQ); initial nQ = INIT; always @(*) begin if(!nCLK) - nQ <= ~D; + nQ = ~D; end endmodule @@ -653,9 +653,9 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q); initial Q = INIT; always @(*) begin if(!nRST) - Q <= 1'b0; + Q = 1'b0; else if(!nCLK) - Q <= D; + Q = D; end endmodule @@ -664,9 +664,9 @@ module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ); initial nQ = INIT; always @(*) begin if(!nRST) - nQ <= 1'b1; + nQ = 1'b1; else if(!nCLK) - nQ <= ~D; + nQ = ~D; end endmodule @@ -675,9 +675,9 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q); initial Q = INIT; always @(*) begin if(!nSET) - Q <= 1'b1; + Q = 1'b1; else if(!nCLK) - Q <= D; + Q = D; end endmodule @@ -686,9 +686,9 @@ module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ); initial nQ = INIT; always @(*) begin if(!nSET) - nQ <= 1'b0; + nQ = 1'b0; else if(!nCLK) - nQ <= ~D; + nQ = ~D; end endmodule @@ -698,9 +698,9 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q); initial Q = INIT; always @(*) begin if(!nSR) - Q <= SRMODE; + Q = SRMODE; else if(!nCLK) - Q <= D; + Q = D; end endmodule @@ -710,9 +710,9 @@ module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ); initial nQ = INIT; always @(*) begin if(!nSR) - nQ <= ~SRMODE; + nQ = ~SRMODE; else if(!nCLK) - nQ <= ~D; + nQ = ~D; end endmodule From bdc2597f792a602ec22f98d7cb3fc23710b6659a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 25 Apr 2025 01:00:08 +0200 Subject: [PATCH 07/10] simplify: fix struct wiretype attr memory leak --- frontends/ast/simplify.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index d35756d4e..3411d6c03 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -1919,6 +1919,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) { // replace instance with wire representing the packed structure newNode = make_packed_struct(template_node, str, attributes); + if (newNode->attributes.count(ID::wiretype)) + delete newNode->attributes[ID::wiretype]; newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str)); // add original input/output attribute to resolved wire newNode->is_input = this->is_input; From 94af24c801736bd89a493f4c92dc7b55af928b25 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Fri, 25 Apr 2025 00:23:50 +0000 Subject: [PATCH 08/10] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 1cef095e3..72d854212 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.52+102 +YOSYS_VER := 0.52+104 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2) From 3d1f2161dcc1bfdc6f1749bbf8c67a3a64d45c7b Mon Sep 17 00:00:00 2001 From: Catherine Date: Thu, 14 Nov 2024 21:49:53 +0000 Subject: [PATCH 09/10] cxxrtl: strip `$paramod` from module name in scope info. --- backends/cxxrtl/cxxrtl_backend.cc | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 052699ad6..819b2c1df 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -2410,7 +2410,12 @@ struct CxxrtlWorker { auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell); cell_attrs.erase(ID::module_not_derived); f << indent << "scopes->add(path, " << escape_cxx_string(get_hdl_name(cell)) << ", "; - f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", "; + if (module_attrs.count(ID(hdlname))) { + f << escape_cxx_string(module_attrs.at(ID(hdlname)).decode_string()); + } else { + f << escape_cxx_string(cell->get_string_attribute(ID(module))); + } + f << ", "; dump_serialized_metadata(module_attrs); f << ", "; dump_serialized_metadata(cell_attrs); From 58e7cfa559fac94b8e3503ae6f940d3012004003 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sun, 27 Apr 2025 00:25:27 +0000 Subject: [PATCH 10/10] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 72d854212..393408603 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.52+104 +YOSYS_VER := 0.52+117 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)