diff --git a/Makefile b/Makefile
index db9e519e0..6b66bd640 100644
--- a/Makefile
+++ b/Makefile
@@ -176,7 +176,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.52+102
+YOSYS_VER := 0.52+117
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index 052699ad6..819b2c1df 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -2410,7 +2410,12 @@ struct CxxrtlWorker {
 						auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
 						cell_attrs.erase(ID::module_not_derived);
 						f << indent << "scopes->add(path, " << escape_cxx_string(get_hdl_name(cell)) << ", ";
-						f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", ";
+						if (module_attrs.count(ID(hdlname))) {
+							f << escape_cxx_string(module_attrs.at(ID(hdlname)).decode_string());
+						} else {
+							f << escape_cxx_string(cell->get_string_attribute(ID(module)));
+						}
+						f << ", ";
 						dump_serialized_metadata(module_attrs);
 						f << ", ";
 						dump_serialized_metadata(cell_attrs);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index d35756d4e..3411d6c03 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1919,6 +1919,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 			if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
 				// replace instance with wire representing the packed structure
 				newNode = make_packed_struct(template_node, str, attributes);
+				if (newNode->attributes.count(ID::wiretype))
+					delete newNode->attributes[ID::wiretype];
 				newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
 				// add original input/output attribute to resolved wire
 				newNode->is_input = this->is_input;
diff --git a/techlibs/gatemate/brams.txt b/techlibs/gatemate/brams.txt
index be22856ac..d39aafcbf 100644
--- a/techlibs/gatemate/brams.txt
+++ b/techlibs/gatemate/brams.txt
@@ -34,7 +34,6 @@ ram block $__CC_BRAM_TDP_ {
 		}
 		portoption "WR_MODE" "WRITE_THROUGH" {
 			rdwr new;
-			wrtrans all new;
 		}
 		wrbe_separate;
 		optional_rw;
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 43d35d08f..f1393be0c 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -48,7 +48,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
-		OUT <= (count == 14'h0);
+		OUT = (count == 14'h0);
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -133,10 +133,10 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		if(UP)
-			OUT <= (count == 14'h3fff);
+			OUT = (count == 14'h3fff);
 		else
-			OUT <= (count == 14'h0);
-		POUT <= count[7:0];
+			OUT = (count == 14'h0);
+		POUT = count[7:0];
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -272,10 +272,10 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
 		if(UP)
-			OUT <= (count == 8'hff);
+			OUT = (count == 8'hff);
 		else
-			OUT <= (count == 8'h0);
-		POUT <= count;
+			OUT = (count == 8'h0);
+		POUT = count;
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -413,8 +413,8 @@ module GP_COUNT8(
 
 	//Combinatorially output underflow flag whenever we wrap low
 	always @(*) begin
-		OUT <= (count == 8'h0);
-		POUT <= count;
+		OUT = (count == 8'h0);
+		POUT = count;
 	end
 
 	//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
@@ -488,23 +488,23 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2
 	always @(*) begin
 		case(SEL)
 			2'd00: begin
-				OUTA <= IN0;
-				OUTB <= IN3;
+				OUTA = IN0;
+				OUTB = IN3;
 			end
 
 			2'd01: begin
-				OUTA <= IN1;
-				OUTB <= IN2;
+				OUTA = IN1;
+				OUTB = IN2;
 			end
 
 			2'd02: begin
-				OUTA <= IN2;
-				OUTB <= IN1;
+				OUTA = IN2;
+				OUTB = IN1;
 			end
 
 			2'd03: begin
-				OUTA <= IN3;
-				OUTB <= IN0;
+				OUTA = IN3;
+				OUTB = IN0;
 			end
 
 		endcase
@@ -635,7 +635,7 @@ module GP_DLATCH(input D, input nCLK, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -644,7 +644,7 @@ module GP_DLATCHI(input D, input nCLK, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -653,9 +653,9 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nRST)
-			Q <= 1'b0;
+			Q = 1'b0;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -664,9 +664,9 @@ module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nRST)
-			nQ <= 1'b1;
+			nQ = 1'b1;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -675,9 +675,9 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nSET)
-			Q <= 1'b1;
+			Q = 1'b1;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -686,9 +686,9 @@ module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nSET)
-			nQ <= 1'b0;
+			nQ = 1'b0;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
@@ -698,9 +698,9 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
 	initial Q = INIT;
 	always @(*) begin
 		if(!nSR)
-			Q <= SRMODE;
+			Q = SRMODE;
 		else if(!nCLK)
-			Q <= D;
+			Q = D;
 	end
 endmodule
 
@@ -710,9 +710,9 @@ module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
 	initial nQ = INIT;
 	always @(*) begin
 		if(!nSR)
-			nQ <= ~SRMODE;
+			nQ = ~SRMODE;
 		else if(!nCLK)
-			nQ <= ~D;
+			nQ = ~D;
 	end
 endmodule
 
diff --git a/techlibs/ice40/ice40_dsp.pmg b/techlibs/ice40/ice40_dsp.pmg
index 63bc8de4b..7e4c3ace2 100644
--- a/techlibs/ice40/ice40_dsp.pmg
+++ b/techlibs/ice40/ice40_dsp.pmg
@@ -23,7 +23,7 @@ match mul
 endmatch
 
 code sigA sigB sigH
-	auto unextend = [](const SigSpec &sig) {
+	auto unextend_signed = [](const SigSpec &sig) {
 		int i;
 		for (i = GetSize(sig)-1; i > 0; i--)
 			if (sig[i] != sig[i-1])
@@ -32,8 +32,16 @@ code sigA sigB sigH
 		++i;
 		return sig.extract(0, i);
 	};
-	sigA = unextend(port(mul, \A));
-	sigB = unextend(port(mul, \B));
+	auto unextend_unsigned = [](const SigSpec &sig) {
+		int i; 
+		for (i = GetSize(sig)-1; i > 0; i--)
+			if (sig[i] != SigBit(State::S0))
+				break;
+		++i;
+		return sig.extract(0, i);
+	};
+	sigA = param(mul, \A_SIGNED).as_bool() ? unextend_signed(port(mul, \A)) : unextend_unsigned(port(mul, \A));
+	sigB = param(mul, \B_SIGNED).as_bool() ? unextend_signed(port(mul, \B)) : unextend_unsigned(port(mul, \B));
 
 	SigSpec O;
 	if (mul->type == $mul)
diff --git a/tests/arch/ice40/ice40_dsp_const.ys b/tests/arch/ice40/ice40_dsp_const.ys
new file mode 100644
index 000000000..c9c76a1ac
--- /dev/null
+++ b/tests/arch/ice40/ice40_dsp_const.ys
@@ -0,0 +1,80 @@
+read_verilog << EOT
+module top(input wire [14:0] a, output wire [18:0] b);
+assign b = a*$unsigned(5'b01111);
+endmodule
+EOT
+
+prep
+ice40_dsp
+
+read_verilog << EOT
+module ref(a, b);
+  wire _0_;
+  wire _1_;
+  wire _2_;
+  wire [12:0] _3_;
+  (* src = "<<EOT:1.30-1.31" *)
+  input [14:0] a;
+  wire [14:0] a;
+  (* src = "<<EOT:1.52-1.53" *)
+  output [18:0] b;
+  wire [18:0] b;
+  SB_MAC16 #(
+    .A_REG(1'h0),
+    .A_SIGNED(32'd0),
+    .BOTADDSUB_CARRYSELECT(2'h0),
+    .BOTADDSUB_LOWERINPUT(2'h2),
+    .BOTADDSUB_UPPERINPUT(1'h1),
+    .BOTOUTPUT_SELECT(2'h3),
+    .BOT_8x8_MULT_REG(1'h0),
+    .B_REG(1'h0),
+    .B_SIGNED(32'd0),
+    .C_REG(1'h0),
+    .D_REG(1'h0),
+    .MODE_8x8(1'h0),
+    .NEG_TRIGGER(1'h0),
+    .PIPELINE_16x16_MULT_REG1(1'h0),
+    .PIPELINE_16x16_MULT_REG2(1'h0),
+    .TOPADDSUB_CARRYSELECT(2'h3),
+    .TOPADDSUB_LOWERINPUT(2'h2),
+    .TOPADDSUB_UPPERINPUT(1'h1),
+    .TOPOUTPUT_SELECT(2'h3),
+    .TOP_8x8_MULT_REG(1'h0)
+  ) _4_ (
+    .A({ 1'h0, a }),
+    .ACCUMCI(1'hx),
+    .ACCUMCO(_1_),
+    .ADDSUBBOT(1'h0),
+    .ADDSUBTOP(1'h0),
+    .AHOLD(1'h0),
+    .B(16'b1111),
+    .BHOLD(1'h0),
+    .C(16'h0000),
+    .CE(1'h0),
+    .CHOLD(1'h0),
+    .CI(1'hx),
+    .CLK(1'h0),
+    .CO(_2_),
+    .D(16'h0000),
+    .DHOLD(1'h0),
+    .IRSTBOT(1'h0),
+    .IRSTTOP(1'h0),
+    .O({ _3_, b }),
+    .OHOLDBOT(1'h0),
+    .OHOLDTOP(1'h0),
+    .OLOADBOT(1'h0),
+    .OLOADTOP(1'h0),
+    .ORSTBOT(1'h0),
+    .ORSTTOP(1'h0),
+    .SIGNEXTIN(1'hx),
+    .SIGNEXTOUT(_0_)
+  );
+endmodule
+EOT
+
+techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
+
+equiv_make top ref equiv 
+select -assert-any -module equiv t:$equiv 
+equiv_induct 
+equiv_status -assert