mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-24 01:25:33 +00:00
Code Activity

Use selection helpers

Browse source 
Catch more uses of selection constructor without assigning a design.
This commit is contained in:
Krystine Sherwin 2024-11-20 09:38:33 +13:00
parent 25bbc6effc
commit 9484d169c8
No known key found for this signature in database
22 changed files with 84 additions and 78 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/driver.cc
View file

@ -106,7 +106,7 @@ void run(const char *command)
log_last_error = "";
} catch (...) {
while (GetSize(yosys_get_design()->selection_stack) > selSize)
yosys_get_design()->selection_stack.pop_back();
yosys_get_design()->pop_selection();
throw;
}
}

24
kernel/register.cc
View file

@ -318,18 +318,18 @@ void Pass::call(RTLIL::Design *design, std::vector<std::string> args)
pass_register[args[0]]->execute(args, design);
pass_register[args[0]]->post_execute(state);
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
design->pop_selection();
}
void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &selection, std::string command)
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
design->selection_stack.push_back(selection);
design->push_selection(selection);
Pass::call(design, command);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -337,11 +337,11 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module.clear();
design->selection_stack.push_back(selection);
design->push_selection(selection);
Pass::call(design, args);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -349,12 +349,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
design->push_empty_selection();
design->select(module);
Pass::call(design, command);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -362,12 +362,12 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vec
{
std::string backup_selected_active_module = design->selected_active_module;
design->selected_active_module = module->name.str();
design->selection_stack.push_back(RTLIL::Selection(false));
design->selection_stack.back().select(module);
design->push_empty_selection();
design->select(module);
Pass::call(design, args);
design->selection_stack.pop_back();
design->pop_selection();
design->selected_active_module = backup_selected_active_module;
}
@ -745,7 +745,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f
}
while (design->selection_stack.size() > orig_sel_stack_pos)
design->selection_stack.pop_back();
design->pop_selection();
}
struct SimHelper {

8
kernel/rtlil.cc
View file

@ -887,7 +887,7 @@ RTLIL::Design::Design()
hashidx_ = hashidx_count;
refcount_modules_ = 0;
selection_stack.push_back(RTLIL::Selection(true, false, this));
push_full_selection();
#ifdef WITH_PYTHON
RTLIL::Design::get_all_designs()->insert(std::pair<unsigned int, RTLIL::Design*>(hashidx_, this));
@ -1115,7 +1115,7 @@ bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_module(mod_name);
return selection().selected_module(mod_name);
}
bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
@ -1124,7 +1124,7 @@ bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_whole_module(mod_name);
return selection().selected_whole_module(mod_name);
}
bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL::IdString& memb_name) const
@ -1133,7 +1133,7 @@ bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL
return false;
if (selection_stack.size() == 0)
return true;
return selection_stack.back().selected_member(mod_name, memb_name);
return selection().selected_member(mod_name, memb_name);
}
bool RTLIL::Design::selected_module(RTLIL::Module *mod) const

6
kernel/rtlil.h
View file

@ -1254,7 +1254,7 @@ struct RTLIL::Design
}
bool full_selection() const {
return selection_stack.back().full_selection;
return selection().full_selection;
}
template<typename T1> bool selected(T1 *module) const {
@ -1267,14 +1267,14 @@ struct RTLIL::Design
template<typename T1> void select(T1 *module) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
RTLIL::Selection &sel = selection();
sel.select(module);
}
}
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
RTLIL::Selection &sel = selection();
sel.select(module, member);
}
}

10
kernel/yosys.cc
View file

@ -674,11 +674,11 @@ const char *create_prompt(RTLIL::Design *design, int recursion_counter)
str += "yosys";
if (!design->selected_active_module.empty())
str += stringf(" [%s]", RTLIL::unescape_id(design->selected_active_module).c_str());
if (!design->selection_stack.empty() && !design->selection_stack.back().full_selection) {
if (!design->selection_stack.empty() && !design->full_selection()) {
if (design->selected_active_module.empty())
str += "*";
else if (design->selection_stack.back().selected_modules.size() != 1 || design->selection_stack.back().selected_members.size() != 0 ||
design->selection_stack.back().selected_modules.count(design->selected_active_module) == 0)
else if (design->selection().selected_modules.size() != 1 || design->selection().selected_members.size() != 0 ||
design->selection().selected_modules.count(design->selected_active_module) == 0)
str += "*";
}
snprintf(buffer, 100, "%s> ", str.c_str());
@ -799,7 +799,7 @@ static int tcl_yosys_cmd(ClientData, Tcl_Interp *interp, int argc, const char *a
if (in_repl) {
auto design = yosys_get_design();
while (design->selection_stack.size() > 1)
design->selection_stack.pop_back();
design->pop_selection();
log_reset_stack();
}
Tcl_SetResult(interp, (char *)"Yosys command produced an error", TCL_STATIC);
@ -1458,7 +1458,7 @@ void shell(RTLIL::Design *design)
Pass::call(design, command);
} catch (log_cmd_error_exception) {
while (design->selection_stack.size() > 1)
design->selection_stack.pop_back();
design->pop_selection();
log_reset_stack();
}
design->check();