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Towards Xilinx bram support
This commit is contained in:
Clifford Wolf
parent
4a0b3a5423
commit
9474928672
5 changed files with 178 additions and 28 deletions
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@ -87,7 +87,6 @@ struct rules_t
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tokens.clear();
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string line;
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while (std::getline(infile, line)) {
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log("> %s\n", line.c_str());
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for (string tok = next_token(line); !tok.empty(); tok = next_token(line)) {
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if (tok[0] == '#')
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break;
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@ -11,7 +11,7 @@ bram $__XILINX_RAMB36_SDP72
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP36
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bram $__XILINX_RAMB18_SDP36
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abits 10
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dbits 36
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groups 2
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@ -23,7 +23,7 @@ bram $__XILINX_RAMB36_SDP36
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP18
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bram $__XILINX_RAMB18_TDP18
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abits 11
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dbits 18
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groups 2
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@ -35,7 +35,7 @@ bram $__XILINX_RAMB36_SDP18
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP9
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bram $__XILINX_RAMB18_TDP9
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abits 12
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dbits 9
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groups 2
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@ -47,7 +47,7 @@ bram $__XILINX_RAMB36_SDP9
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP4
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bram $__XILINX_RAMB18_TDP4
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abits 13
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dbits 4
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groups 2
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@ -59,7 +59,7 @@ bram $__XILINX_RAMB36_SDP4
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP2
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bram $__XILINX_RAMB18_TDP2
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abits 14
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dbits 2
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groups 2
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@ -71,7 +71,7 @@ bram $__XILINX_RAMB36_SDP2
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clkpol 2 3
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endbram
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bram $__XILINX_RAMB36_SDP1
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bram $__XILINX_RAMB18_TDP1
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abits 15
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dbits 1
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groups 2
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@ -84,39 +84,36 @@ bram $__XILINX_RAMB36_SDP1
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endbram
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match $__XILINX_RAMB36_SDP72
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min bits 4096
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min efficiency 5
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shuffle_enable 8
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# min efficiency 20
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or_next_if_better
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endmatch
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match $__XILINX_RAMB18_SDP36
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min bits 4096
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min efficiency 5
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shuffle_enable 4
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# or_next_if_better
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endmatch
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# match $__XILINX_RAMB36_SDP36
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# shuffle_enable 4
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# min efficiency 20
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB36_SDP18
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# match $__XILINX_RAMB18_TDP18
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# shuffle_enable 2
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# min efficiency 20
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB36_SDP9
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# min efficiency 20
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# match $__XILINX_RAMB18_TDP9
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB36_SDP4
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# min efficiency 20
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# match $__XILINX_RAMB18_TDP4
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB36_SDP2
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# min efficiency 20
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# match $__XILINX_RAMB18_TDP2
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# or_next_if_better
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# endmatch
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#
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# match $__XILINX_RAMB36_SDP1
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# min efficiency 20
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# match $__XILINX_RAMB18_TDP1
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# endmatch
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@ -79,3 +79,155 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [35:0] A1DATA;
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input [8:0] B1ADDR;
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input [35:0] B1DATA;
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input [3:0] B1EN;
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wire [15:0] A1ADDR_16 = {A1ADDR, 5'b0};
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wire [15:0] B1ADDR_16 = {B1ADDR, 5'b0};
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wire [3:0] DIP, DOP;
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wire [31:0] DI, DO;
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wire [35:0] A1DATA_BUF;
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reg [35:0] B1DATA_Q;
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reg [3:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA[26:18] = transparent_cycle[2] ? B1DATA_Q[26:18] : A1DATA_BUF[26:18];
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assign A1DATA[35:27] = transparent_cycle[3] ? B1DATA_Q[35:27] : A1DATA_BUF[35:27];
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assign A1DATA_BUF = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.WRITE_WIDTH_B(36),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DOBDO(DO[31:16]),
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.DOADO(DO[15:0]),
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.DOPBDOP(DOP[3:2]),
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.DOPADOP(DOP[1:0]),
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.DIBDI(DI[31:16]),
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.DIADI(DI[15:0]),
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.DIPBDIP(DIP[3:2]),
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.DIPADIP(DIP[1:0]),
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.ADDRARDADDR(A1ADDR_16),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(4'b0),
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.ADDRBWRADDR(B1ADDR_16),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE(B1EN)
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);
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endmodule
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// ------------------------------------------------------------------------
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module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
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parameter TRANSP2 = 1;
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parameter CLKPOL2 = 1;
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parameter CLKPOL3 = 1;
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input CLK2;
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input CLK3;
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input [8:0] A1ADDR;
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output [17:0] A1DATA;
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input [8:0] B1ADDR;
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input [17:0] B1DATA;
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input [1:0] B1EN;
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wire [13:0] A1ADDR_14 = {A1ADDR, 4'b0};
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wire [13:0] B1ADDR_14 = {B1ADDR, 4'b0};
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wire [1:0] DIP, DOP;
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wire [15:0] DI, DO;
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wire [17:0] A1DATA_BUF;
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reg [17:0] B1DATA_Q;
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reg [1:0] transparent_cycle;
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wire [1023:0] _TECHMAP_DO_ = "proc; opt -fast";
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generate if (CLKPOL2)
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always @(posedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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else
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always @(negedge CLK2) begin transparent_cycle <= TRANSP2 && A1ADDR == B1ADDR ? B1EN : 0; B1DATA_Q <= B1DATA; end
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endgenerate
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assign A1DATA[ 8: 0] = transparent_cycle[0] ? B1DATA_Q[ 8: 0] : A1DATA_BUF[ 8: 0];
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assign A1DATA[17: 9] = transparent_cycle[1] ? B1DATA_Q[17: 9] : A1DATA_BUF[17: 9];
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assign A1DATA_BUF = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
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assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
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RAMB18E1 #(
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.RAM_MODE("TDP"),
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.READ_WIDTH_A(18),
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.READ_WIDTH_B(18),
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.WRITE_WIDTH_A(18),
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.WRITE_WIDTH_B(18),
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.WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"),
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.WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST")
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) _TECHMAP_REPLACE_ (
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.DIADI(16'b0),
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.DIPADIP(2'b0),
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.DOADO(DO[15:0]),
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.DOPADOP(DOP[1:0]),
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.ADDRARDADDR(A1ADDR_14),
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.CLKARDCLK(CLKPOL2 ? CLK2 : ~CLK2),
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.ENARDEN(|1),
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.REGCEAREGCE(|1),
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.RSTRAMARSTRAM(|0),
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.RSTREGARSTREG(|0),
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.WEA(2'b0),
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.DIBDI(DI[15:0]),
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.DIPBDIP(DIP[1:0]),
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.ADDRBWRADDR(B1ADDR_14),
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.CLKBWRCLK(CLKPOL3 ? CLK3 : ~CLK3),
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.ENBWREN(|1),
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.REGCEB(|0),
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.RSTRAMB(|0),
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.RSTREGB(|0),
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.WEBWE({2'b00, B1EN})
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);
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endmodule
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@ -1,5 +1,7 @@
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#!/bin/bash
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set -e
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use_xsim=false
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unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims
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@ -70,7 +70,7 @@ module bram1_tb #(
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expected_rd[j] = RD_DATA[j];
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end
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$display("#OUT# | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
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$display("#OUT# %3d | WA=%x WD=%x WE=%x | RA=%x RD=%x | %s", i, WR_ADDR, WR_DATA, WR_EN, RD_ADDR, RD_DATA, expected_rd === RD_DATA ? "ok" : "ERROR");
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if (expected_rd !== RD_DATA) begin -> error; error_ind = ~error_ind; end
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end
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end
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