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Towards Xilinx bram support

This commit is contained in:
Clifford Wolf 2015-01-06 15:26:33 +01:00
parent 4a0b3a5423
commit 9474928672
5 changed files with 178 additions and 28 deletions

View file

@ -1,5 +1,7 @@
#!/bin/bash
set -e
use_xsim=false
unisims=/opt/Xilinx/Vivado/2014.4/data/verilog/src/unisims